diff options
| author | Thomas Langer <thomas.langer@lantiq.com> | 2008-12-16 14:07:55 +0000 |
|---|---|---|
| committer | Thomas Langer <thomas.langer@lantiq.com> | 2008-12-16 14:07:55 +0000 |
| commit | 7570eebcdd5628978cbdbab2fb7cb99abbc62360 (patch) | |
| tree | 46e045fd88294505c849b475f46e1556278ae300 | |
| parent | e7336673b14fe311ae493eee86ba8983792bcf02 (diff) | |
| download | mtk-20170518-7570eebcdd5628978cbdbab2fb7cb99abbc62360.zip mtk-20170518-7570eebcdd5628978cbdbab2fb7cb99abbc62360.tar.gz mtk-20170518-7570eebcdd5628978cbdbab2fb7cb99abbc62360.tar.bz2 | |
cleanup sources and prepare for 2.6.27
SVN-Revision: 13660
35 files changed, 1931 insertions, 1543 deletions
diff --git a/target/linux/ifxmips/Makefile b/target/linux/ifxmips/Makefile index a04f19d..69502d1 100644 --- a/target/linux/ifxmips/Makefile +++ b/target/linux/ifxmips/Makefile @@ -12,6 +12,7 @@ BOARDNAME:=Infineon Mips FEATURES:=squashfs jffs2 SUBTARGETS:=generic nfs LINUX_VERSION:=2.6.26.8 +#LINUX_VERSION:=2.6.27.9 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES+=uboot-ifxmips diff --git a/target/linux/ifxmips/config-2.6.26 b/target/linux/ifxmips/config-2.6.26 index f6f4b69..656fa01 100644 --- a/target/linux/ifxmips/config-2.6.26 +++ b/target/linux/ifxmips/config-2.6.26 @@ -22,11 +22,11 @@ CONFIG_CPU_HAS_SYNC=y # CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y +CONFIG_CPU_MIPSR2=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_R3000 is not set @@ -113,6 +113,7 @@ CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set +# CONFIG_MIPS_VPE_LOADER is not set CONFIG_MTD=y # CONFIG_MTD_ABSENT is not set CONFIG_MTD_BLKDEVS=y @@ -166,7 +167,6 @@ CONFIG_MTD_PARTITIONS=y # CONFIG_NE2K_PCI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NO_IOPORT is not set -# CONFIG_OCF_OCF is not set CONFIG_PAGEFLAGS_EXTENDED=y # CONFIG_PAGE_SIZE_16KB is not set CONFIG_PAGE_SIZE_4KB=y @@ -180,6 +180,7 @@ CONFIG_PCI_DOMAINS=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set +# CONFIG_PROM_EMU is not set # CONFIG_R6040 is not set CONFIG_RFKILL_LEDS=y CONFIG_RTC_LIB=y @@ -208,10 +209,12 @@ CONFIG_SSB_POSSIBLE=y CONFIG_SWAP_IO_SPACE=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y # CONFIG_TC35815 is not set # CONFIG_TICK_ONESHOT is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/target/linux/ifxmips/config-2.6.27 b/target/linux/ifxmips/config-2.6.27 new file mode 100644 index 0000000..27cc9ed --- /dev/null +++ b/target/linux/ifxmips/config-2.6.27 @@ -0,0 +1,257 @@ +CONFIG_32BIT=y +# CONFIG_64BIT is not set +# CONFIG_8139TOO is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_POPULATES_NODE_MAP=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ATM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_BCM47XX is not set +CONFIG_BITREVERSE=y +# CONFIG_BT is not set +CONFIG_CEVT_R4K=y +CONFIG_CLASSIC_RCU=y +CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit" +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR2=y +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_VR41XX is not set +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CSRC_R4K=y +CONFIG_DEVPORT=y +# CONFIG_DM9000 is not set +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GPIO_DEVICE=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_CLK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_IDE=y +# CONFIG_HAVE_IOREMAP_PROT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_STD_PC_SERIAL_PORT=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +# CONFIG_I2C is not set +# CONFIG_IDE is not set +CONFIG_IFXMIPS=y +CONFIG_IFXMIPS_EEPROM=y +CONFIG_IFXMIPS_GPIO_RST_BTN=y +# CONFIG_IFXMIPS_MEI is not set +CONFIG_IFXMIPS_MII0=y +# CONFIG_IFXMIPS_PROM_ASC0 is not set +CONFIG_IFXMIPS_PROM_ASC1=y +CONFIG_IFXMIPS_SSC=y +CONFIG_IFXMIPS_WDT=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_KALLSYMS=y +CONFIG_KMOD=y +# CONFIG_LEDS_ALIX is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_IFXMIPS=y +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MIKROTIK_RB532 is not set +CONFIG_MIPS=y +# CONFIG_MIPS_COBALT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_IFXMIPS=y +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_NATSEMI is not set +CONFIG_NF_CT_ACCT=y +# CONFIG_NO_IOPORT is not set +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PAGE_SIZE_16KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_PROM_EMU is not set +# CONFIG_R6040 is not set +CONFIG_RFKILL_LEDS=y +CONFIG_RTC_LIB=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_IFXMIPS=y +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SWAP is not set +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +# CONFIG_TC35815 is not set +# CONFIG_TICK_ONESHOT is not set +CONFIG_TRAD_SIGNALS=y +CONFIG_USB=m +CONFIG_USB_AMD5536UDC=y +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_DWC_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_FILE_STORAGE is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_GADGET_AMD5536UDC=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_ZERO is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIA_RHINE is not set +CONFIG_VIDEO_MEDIA=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c index 9377379..2a803ff 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c @@ -70,7 +70,7 @@ struct ifxmips_board { int num_devs; }; -spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(ebu_lock); EXPORT_SYMBOL_GPL(ebu_lock); static unsigned char ifxmips_ethaddr[6]; @@ -245,7 +245,7 @@ static int __init ifxmips_set_ethaddr(char *str) { #define IS_HEX(x) \ (((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \ - || (x >= 'A' && x <= 'F'))?(1):(0)) + || (x >= 'A' && x <= 'F')) ? (1) : (0)) int i; str = strchr(str, '='); if (!str) @@ -354,8 +354,8 @@ int __init ifxmips_init_devices(void) #endif ifxmips_led_data.leds = board->ifxmips_leds; - printk(KERN_INFO "%s:%s[%d]adding %d devs\n", - __FILE__, __func__, __LINE__, board->num_devs); + printk(KERN_INFO "%s: adding %d devs\n", + __func__, board->num_devs); ifxmips_gpio.resource = &board->reset_resource; ifxmips_gpio_dev.resource = &board->gpiodev_resource; diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c index fc3658b..40a6b99 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c @@ -14,7 +14,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2007 Xu Liang, infineon - * Copyright (C) 2008 John Crispin <blogic@openwrt.org> + * Copyright (C) 2008 John Crispin <blogic@openwrt.org> */ #include <linux/kernel.h> @@ -24,8 +24,8 @@ #include <linux/fs.h> #include <linux/miscdevice.h> #include <linux/init.h> -#include <asm/uaccess.h> -#include <asm/unistd.h> +#include <linux/uaccess.h> +#include <linux/unistd.h> #include <asm/irq.h> #include <asm/div64.h> #include <linux/errno.h> @@ -204,7 +204,7 @@ cgu_get_fpi_bus_clock(int fpi) void cgu_setup_pci_clk(int external_clock) { - //set clock to 33Mhz + //set clock to 33Mhz ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR); if(external_clock) diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c index a57b803..b31c622 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c @@ -15,9 +15,9 @@ #include <linux/vmalloc.h> #include <linux/interrupt.h> #include <linux/delay.h> -#include <asm/uaccess.h> +#include <linux/uaccess.h> #include <linux/errno.h> -#include <asm/io.h> +#include <linux/io.h> #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_irq.h> @@ -32,16 +32,16 @@ #define DMA_INT_BUDGET 100 /*budget for interrupt handling */ #define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */ -extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr); -extern void ifxmips_enable_irq (unsigned int irq_nr); -extern void ifxmips_disable_irq (unsigned int irq_nr); +extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); +extern void ifxmips_enable_irq(unsigned int irq_nr); +extern void ifxmips_disable_irq(unsigned int irq_nr); u64 *g_desc_list; _dma_device_info dma_devs[MAX_DMA_DEVICE_NUM]; _dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM]; -char global_device_name[MAX_DMA_DEVICE_NUM][20] = - { {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} }; +static const char *global_device_name[MAX_DMA_DEVICE_NUM] = + { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" }; _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = { {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0}, @@ -67,34 +67,30 @@ _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = { }; _dma_chan_map *chan_map = default_dma_map; -volatile u32 g_ifxmips_dma_int_status = 0; -volatile int g_ifxmips_dma_in_process = 0;/*0=not in process,1=in process*/ +volatile u32 g_ifxmips_dma_int_status; +volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */ -void do_dma_tasklet (unsigned long); -DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0); +void do_dma_tasklet(unsigned long); +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); -u8* -common_buffer_alloc (int len, int *byte_offset, void **opt) +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) { - u8 *buffer = (u8 *) kmalloc (len * sizeof (u8), GFP_KERNEL); + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); *byte_offset = 0; return buffer; } -void -common_buffer_free (u8 *dataptr, void *opt) +void common_buffer_free(u8 *dataptr, void *opt) { - if (dataptr) - kfree(dataptr); + kfree(dataptr); } -void -enable_ch_irq (_dma_channel_info *pCh) +void enable_ch_irq(_dma_channel_info *pCh) { int chan_no = (int)(pCh - dma_chan); - int flag; + unsigned long flag; local_irq_save(flag); ifxmips_w32(chan_no, IFXMIPS_DMA_CS); @@ -104,10 +100,9 @@ enable_ch_irq (_dma_channel_info *pCh) ifxmips_enable_irq(pCh->irq); } -void -disable_ch_irq (_dma_channel_info *pCh) +void disable_ch_irq(_dma_channel_info *pCh) { - int flag; + unsigned long flag; int chan_no = (int) (pCh - dma_chan); local_irq_save(flag); @@ -119,24 +114,22 @@ disable_ch_irq (_dma_channel_info *pCh) ifxmips_mask_and_ack_irq(pCh->irq); } -void -open_chan (_dma_channel_info *pCh) +void open_chan(_dma_channel_info *pCh) { - int flag; + unsigned long flag; int chan_no = (int)(pCh - dma_chan); local_irq_save(flag); ifxmips_w32(chan_no, IFXMIPS_DMA_CS); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL); - if(pCh->dir == IFXMIPS_DMA_RX) + if (pCh->dir == IFXMIPS_DMA_RX) enable_ch_irq(pCh); local_irq_restore(flag); } -void -close_chan(_dma_channel_info *pCh) +void close_chan(_dma_channel_info *pCh) { - int flag; + unsigned long flag; int chan_no = (int) (pCh - dma_chan); local_irq_save(flag); @@ -146,8 +139,7 @@ close_chan(_dma_channel_info *pCh) local_irq_restore(flag); } -void -reset_chan (_dma_channel_info *pCh) +void reset_chan(_dma_channel_info *pCh) { int chan_no = (int) (pCh - dma_chan); @@ -155,23 +147,22 @@ reset_chan (_dma_channel_info *pCh) ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); } -void -rx_chan_intr_handler (int chan_no) +void rx_chan_intr_handler(int chan_no) { _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; _dma_channel_info *pCh = &dma_chan[chan_no]; struct rx_desc *rx_desc_p; int tmp; - int flag; + unsigned long flag; /*handle command complete interrupt */ - rx_desc_p = (struct rx_desc*)pCh->desc_base + pCh->curr_desc; + rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc; if (rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C && rx_desc_p->status.field.data_length < 1536){ - /*Every thing is correct, then we inform the upper layer */ + /* Every thing is correct, then we inform the upper layer */ pDev->current_rx_chan = pCh->rel_chan_no; - if(pDev->intr_handler) + if (pDev->intr_handler) pDev->intr_handler(pDev, RCV_INT); pCh->weight--; } else { @@ -186,88 +177,76 @@ rx_chan_intr_handler (int chan_no) } } -inline void -tx_chan_intr_handler (int chan_no) +inline void tx_chan_intr_handler(int chan_no) { - _dma_device_info *pDev = (_dma_device_info*)dma_chan[chan_no].dma_dev; + _dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; _dma_channel_info *pCh = &dma_chan[chan_no]; - int tmp; - int flag; - - local_irq_save(flag); - tmp = ifxmips_r32(IFXMIPS_DMA_CS); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); - ifxmips_w32(tmp, IFXMIPS_DMA_CS); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); + int tmp; + unsigned long flag; + + local_irq_save(flag); + tmp = ifxmips_r32(IFXMIPS_DMA_CS); + ifxmips_w32(chan_no, IFXMIPS_DMA_CS); + ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); + ifxmips_w32(tmp, IFXMIPS_DMA_CS); + g_ifxmips_dma_int_status &= ~(1 << chan_no); + local_irq_restore(flag); pDev->current_tx_chan = pCh->rel_chan_no; if (pDev->intr_handler) pDev->intr_handler(pDev, TRANSMIT_CPT_INT); } -void -do_dma_tasklet (unsigned long unused) +void do_dma_tasklet(unsigned long unused) { int i; int chan_no = 0; int budget = DMA_INT_BUDGET; int weight = 0; - int flag; + unsigned long flag; - while (g_ifxmips_dma_int_status) - { - if (budget-- < 0) - { + while (g_ifxmips_dma_int_status) { + if (budget-- < 0) { tasklet_schedule(&dma_tasklet); return; } chan_no = -1; weight = 0; - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { - if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) - { - if (dma_chan[i].weight > weight) - { + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { + if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) { + if (dma_chan[i].weight > weight) { chan_no = i; - weight = dma_chan[chan_no].weight; - } + weight = dma_chan[chan_no].weight; + } } } - if (chan_no >= 0) - { + if (chan_no >= 0) { if (chan_map[chan_no].dir == IFXMIPS_DMA_RX) rx_chan_intr_handler(chan_no); else tx_chan_intr_handler(chan_no); } else { for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { dma_chan[i].weight = dma_chan[i].default_weight; - } } } - local_irq_save(flag); + local_irq_save(flag); g_ifxmips_dma_in_process = 0; - if (g_ifxmips_dma_int_status) - { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - local_irq_restore(flag); + if (g_ifxmips_dma_int_status) { + g_ifxmips_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } + local_irq_restore(flag); } -irqreturn_t -dma_interrupt (int irq, void *dev_id) +irqreturn_t dma_interrupt(int irq, void *dev_id) { _dma_channel_info *pCh; int chan_no = 0; int tmp; - pCh = (_dma_channel_info*)dev_id; + pCh = (_dma_channel_info *)dev_id; chan_no = (int)(pCh - dma_chan); if (chan_no < 0 || chan_no > 19) BUG(); @@ -278,24 +257,20 @@ dma_interrupt (int irq, void *dev_id) ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN); ifxmips_mask_and_ack_irq(irq); - if (!g_ifxmips_dma_in_process) - { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } + if (!g_ifxmips_dma_in_process) { + g_ifxmips_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } return IRQ_HANDLED; } -_dma_device_info* -dma_device_reserve (char *dev_name) +_dma_device_info *dma_device_reserve(char *dev_name) { int i; - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { - if (strcmp(dev_name, dma_devs[i].device_name) == 0) - { + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) { + if (strcmp(dev_name, dma_devs[i].device_name) == 0) { if (dma_devs[i].reserved) return NULL; dma_devs[i].reserved = 1; @@ -305,64 +280,59 @@ dma_device_reserve (char *dev_name) return &dma_devs[i]; } +EXPORT_SYMBOL(dma_device_reserve); -void -dma_device_release (_dma_device_info *dev) +void dma_device_release(_dma_device_info *dev) { dev->reserved = 0; } +EXPORT_SYMBOL(dma_device_release); -void -dma_device_register(_dma_device_info *dev) +void dma_device_register(_dma_device_info *dev) { int i, j; int chan_no = 0; u8 *buffer; int byte_offset; - int flag; + unsigned long flag; _dma_device_info *pDev; _dma_channel_info *pCh; struct rx_desc *rx_desc_p; struct tx_desc *tx_desc_p; - for (i = 0; i < dev->max_tx_chan_num; i++) - { + for (i = 0; i < dev->max_tx_chan_num; i++) { pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { + if (pCh->control == IFXMIPS_DMA_CH_ON) { chan_no = (int)(pCh - dma_chan); - for (j = 0; j < pCh->desc_len; j++) - { - tx_desc_p = (struct tx_desc*)pCh->desc_base + j; + for (j = 0; j < pCh->desc_len; j++) { + tx_desc_p = (struct tx_desc *)pCh->desc_base + j; memset(tx_desc_p, 0, sizeof(struct tx_desc)); } local_irq_save(flag); ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /*check if the descriptor length is changed */ + /* check if the descriptor length is changed */ if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){}; + while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2) + ; ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */ + ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */ local_irq_restore(flag); } } - for (i = 0; i < dev->max_rx_chan_num; i++) - { + for (i = 0; i < dev->max_rx_chan_num; i++) { pCh = dev->rx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { + if (pCh->control == IFXMIPS_DMA_CH_ON) { chan_no = (int)(pCh - dma_chan); - for (j = 0; j < pCh->desc_len; j++) - { - rx_desc_p = (struct rx_desc*)pCh->desc_base + j; - pDev = (_dma_device_info*)(pCh->dma_dev); - buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void*)&(pCh->opt[j])); + for (j = 0; j < pCh->desc_len; j++) { + rx_desc_p = (struct rx_desc *)pCh->desc_base + j; + pDev = (_dma_device_info *)(pCh->dma_dev); + buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j])); if (!buffer) break; @@ -377,13 +347,14 @@ dma_device_register(_dma_device_info *dev) local_irq_save(flag); ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /*check if the descriptor length is changed */ + /* check if the descriptor length is changed */ if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){}; - ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */ + while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2) + ; + ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */ ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL); local_irq_restore(flag); @@ -391,51 +362,47 @@ dma_device_register(_dma_device_info *dev) } } } +EXPORT_SYMBOL(dma_device_register); -void -dma_device_unregister (_dma_device_info *dev) +void dma_device_unregister(_dma_device_info *dev) { int i, j; int chan_no; _dma_channel_info *pCh; struct rx_desc *rx_desc_p; struct tx_desc *tx_desc_p; - int flag; + unsigned long flag; - for (i = 0; i < dev->max_tx_chan_num; i++) - { + for (i = 0; i < dev->max_tx_chan_num; i++) { pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) - { + if (pCh->control == IFXMIPS_DMA_CH_ON) { chan_no = (int)(dev->tx_chan[i] - dma_chan); - local_irq_save (flag); + local_irq_save(flag); ifxmips_w32(chan_no, IFXMIPS_DMA_CS); pCh->curr_desc = 0; pCh->prev_desc = 0; pCh->control = IFXMIPS_DMA_CH_OFF; - ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */ + ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */ + ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */ ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {}; - local_irq_restore (flag); + while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) + ; + local_irq_restore(flag); - for (j = 0; j < pCh->desc_len; j++) - { - tx_desc_p = (struct tx_desc*)pCh->desc_base + j; + for (j = 0; j < pCh->desc_len; j++) { + tx_desc_p = (struct tx_desc *)pCh->desc_base + j; if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) - || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) - { - dev->buffer_free ((u8 *) __va (tx_desc_p->Data_Pointer), (void*)pCh->opt[j]); + || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) { + dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]); } tx_desc_p->status.field.OWN = CPU_OWN; - memset (tx_desc_p, 0, sizeof (struct tx_desc)); + memset(tx_desc_p, 0, sizeof(struct tx_desc)); } - //TODO should free buffer that is not transferred by dma + /* TODO should free buffer that is not transferred by dma */ } } - for (i = 0; i < dev->max_rx_chan_num; i++) - { + for (i = 0; i < dev->max_rx_chan_num; i++) { pCh = dev->rx_chan[i]; chan_no = (int)(dev->rx_chan[i] - dma_chan); ifxmips_disable_irq(pCh->irq); @@ -447,30 +414,29 @@ dma_device_unregister (_dma_device_info *dev) pCh->control = IFXMIPS_DMA_CH_OFF; ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */ + ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */ + ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */ ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {}; + while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) + ; - local_irq_restore (flag); - for (j = 0; j < pCh->desc_len; j++) - { + local_irq_restore(flag); + for (j = 0; j < pCh->desc_len; j++) { rx_desc_p = (struct rx_desc *) pCh->desc_base + j; - if ((rx_desc_p->status.field.OWN == CPU_OWN + if ((rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C) || (rx_desc_p->status.field.OWN == DMA_OWN && rx_desc_p->status.field.data_length > 0)) { - dev->buffer_free ((u8 *) - __va (rx_desc_p-> - Data_Pointer), - (void *) pCh->opt[j]); + dev->buffer_free((u8 *) + __va(rx_desc_p->Data_Pointer), + (void *) pCh->opt[j]); } } } } +EXPORT_SYMBOL(dma_device_unregister); -int -dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt) +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) { u8 *buf; int len; @@ -479,35 +445,29 @@ dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt) _dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan]; struct rx_desc *rx_desc_p; - /*get the rx data first */ + /* get the rx data first */ rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc; if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C)) - { return 0; - } - buf = (u8 *) __va (rx_desc_p->Data_Pointer); - *(u32*)dataptr = (u32)buf; + buf = (u8 *) __va(rx_desc_p->Data_Pointer); + *(u32 *)dataptr = (u32)buf; len = rx_desc_p->status.field.data_length; if (opt) - { - *(int*)opt = (int)pCh->opt[pCh->curr_desc]; - } + *(int *)opt = (int)pCh->opt[pCh->curr_desc]; - /*replace with a new allocated buffer */ + /* replace with a new allocated buffer */ buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p); - if (buf) - { - dma_cache_inv ((unsigned long) buf, - pCh->packet_size); + if (buf) { + dma_cache_inv((unsigned long) buf, pCh->packet_size); pCh->opt[pCh->curr_desc] = p; - wmb (); + wmb(); - rx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) buf); + rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf); rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size; - wmb (); + wmb(); } else { *(u32 *) dataptr = 0; if (opt) @@ -515,55 +475,53 @@ dma_device_read (struct dma_device_info *dma_dev, u8 ** dataptr, void **opt) len = 0; } - /*increase the curr_desc pointer */ + /* increase the curr_desc pointer */ pCh->curr_desc++; if (pCh->curr_desc == pCh->desc_len) pCh->curr_desc = 0; return len; } +EXPORT_SYMBOL(dma_device_read); -int -dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *opt) +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt) { - int flag; + unsigned long flag; u32 tmp, byte_offset; _dma_channel_info *pCh; int chan_no; struct tx_desc *tx_desc_p; - local_irq_save (flag); + local_irq_save(flag); pCh = dma_dev->tx_chan[dma_dev->current_tx_chan]; chan_no = (int)(pCh - (_dma_channel_info *) dma_chan); - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc; - while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) - { - dma_dev->buffer_free((u8 *) __va (tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]); - memset(tx_desc_p, 0, sizeof (struct tx_desc)); + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc; + while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) { + dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]); + memset(tx_desc_p, 0, sizeof(struct tx_desc)); pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len); - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->prev_desc; + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc; } - tx_desc_p = (struct tx_desc*)pCh->desc_base + pCh->curr_desc; - /*Check whether this descriptor is available */ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) - { - /*if not , the tell the upper layer device */ + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc; + /* Check whether this descriptor is available */ + if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) { + /* if not, the tell the upper layer device */ dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); local_irq_restore(flag); - printk (KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__); + printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__); return 0; } pCh->opt[pCh->curr_desc] = opt; - /*byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */ - byte_offset = ((u32) CPHYSADDR ((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4); - dma_cache_wback ((unsigned long) dataptr, len); - wmb (); - tx_desc_p->Data_Pointer = (u32) CPHYSADDR ((u32) dataptr) - byte_offset; - wmb (); + /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */ + byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4); + dma_cache_wback((unsigned long) dataptr, len); + wmb(); + tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset; + wmb(); tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len; - wmb (); + wmb(); pCh->curr_desc++; if (pCh->curr_desc == pCh->desc_len) @@ -571,8 +529,7 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void * /*Check whether this descriptor is available */ tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc; - if (tx_desc_p->status.field.OWN == DMA_OWN) - { + if (tx_desc_p->status.field.OWN == DMA_OWN) { /*if not , the tell the upper layer device */ dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); } @@ -581,39 +538,34 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void * tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL); if (!(tmp & 1)) - pCh->open (pCh); + pCh->open(pCh); - local_irq_restore (flag); + local_irq_restore(flag); return len; } +EXPORT_SYMBOL(dma_device_write); -int -map_dma_chan(_dma_chan_map *map) +int map_dma_chan(_dma_chan_map *map) { int i, j; int result; for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { strcpy(dma_devs[i].device_name, global_device_name[i]); - } - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { dma_chan[i].irq = map[i].irq; - result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, "dma-core", (void*)&dma_chan[i]); - if (result) - { - printk("error, cannot get dma_irq!\n"); + result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]); + if (result) { + printk(KERN_WARNING "error, cannot get dma_irq!\n"); free_irq(dma_chan[i].irq, (void *) &dma_interrupt); return -EFAULT; } } - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - { + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) { dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */ dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */ dma_devs[i].max_rx_chan_num = 0; @@ -623,20 +575,17 @@ map_dma_chan(_dma_chan_map *map) dma_devs[i].intr_handler = NULL; dma_devs[i].tx_burst_len = 4; dma_devs[i].rx_burst_len = 4; - if (i == 0) - { + if (i == 0) { ifxmips_w32(0, IFXMIPS_DMA_PS); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */ } - if (i == 1) - { + if (i == 1) { ifxmips_w32(1, IFXMIPS_DMA_PS); ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */ } - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) - { + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) { dma_chan[j].byte_offset = 0; dma_chan[j].open = &open_chan; dma_chan[j].close = &close_chan; @@ -651,26 +600,23 @@ map_dma_chan(_dma_chan_map *map) dma_chan[j].prev_desc = 0; } - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) - { - if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) - { - if (map[j].dir == IFXMIPS_DMA_RX) - { + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) { + if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) { + if (map[j].dir == IFXMIPS_DMA_RX) { dma_chan[j].dir = IFXMIPS_DMA_RX; dma_devs[i].max_rx_chan_num++; dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j]; dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void*)&dma_devs[i]; - } else if(map[j].dir == IFXMIPS_DMA_TX) - { /*TX direction */ + dma_chan[j].dma_dev = (void *)&dma_devs[i]; + } else if (map[j].dir == IFXMIPS_DMA_TX) { + /*TX direction */ dma_chan[j].dir = IFXMIPS_DMA_TX; dma_devs[i].max_tx_chan_num++; dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j]; dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void*)&dma_devs[i]; + dma_chan[j].dma_dev = (void *)&dma_devs[i]; } else { - printk ("WRONG DMA MAP!\n"); + printk(KERN_WARNING "WRONG DMA MAP!\n"); } } } @@ -679,32 +625,28 @@ map_dma_chan(_dma_chan_map *map) return 0; } -void -dma_chip_init(void) +void dma_chip_init(void) { int i; - // enable DMA from PMU + /* enable DMA from PMU */ ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); - // reset DMA + /* reset DMA */ ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL); - // diable all interrupts + /* disable all interrupts */ ifxmips_w32(0, IFXMIPS_DMA_IRNEN); - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { ifxmips_w32(i, IFXMIPS_DMA_CS); ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL); ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL); ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL); - } } -int -ifxmips_dma_init (void) +int ifxmips_dma_init(void) { int i; @@ -712,18 +654,16 @@ ifxmips_dma_init (void) if (map_dma_chan(default_dma_map)) BUG(); - g_desc_list = (u64*)KSEG1ADDR(__get_free_page(GFP_DMA)); + g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA)); - if (g_desc_list == NULL) - { - printk("no memory for desriptor\n"); + if (g_desc_list == NULL) { + printk(KERN_WARNING "no memory for desriptor\n"); return -ENOMEM; } memset(g_desc_list, 0, PAGE_SIZE); - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - { + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8; dma_chan[i].curr_desc = 0; dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET; @@ -738,21 +678,13 @@ ifxmips_dma_init (void) arch_initcall(ifxmips_dma_init); -void -dma_cleanup(void) +void dma_cleanup(void) { int i; free_page(KSEG0ADDR((unsigned long) g_desc_list)); for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - free_irq(dma_chan[i].irq, (void*)&dma_interrupt); + free_irq(dma_chan[i].irq, (void *)&dma_interrupt); } -EXPORT_SYMBOL (dma_device_reserve); -EXPORT_SYMBOL (dma_device_release); -EXPORT_SYMBOL (dma_device_register); -EXPORT_SYMBOL (dma_device_unregister); -EXPORT_SYMBOL (dma_device_read); -EXPORT_SYMBOL (dma_device_write); - -MODULE_LICENSE ("GPL"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c index eef5146..bd34b91 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c @@ -16,7 +16,7 @@ * Copyright (C) 2004 btxu Generate from INCA-IP project * Copyright (C) 2005 Jin-Sze.Sow Comments edited * Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #include <linux/module.h> @@ -35,9 +35,8 @@ #include <linux/netlink.h> #include <linux/platform_device.h> #include <net/sock.h> -#include <asm/uaccess.h> -#include <asm/semaphore.h> -#include <asm/uaccess.h> +#include <linux/uaccess.h> +#include <linux/semaphore.h> #include <asm/ifxmips/ifxmips.h> #define MAX_PORTS 2 diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c b/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c index b47074d..730455e 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c @@ -14,7 +14,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #include <linux/init.h> @@ -30,17 +30,16 @@ #include <asm/ifxmips/ifxmips_irq.h> #include <asm/irq_cpu.h> -void -ifxmips_disable_irq(unsigned int irq_nr) +void ifxmips_disable_irq(unsigned int irq_nr) { int i; u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET){ - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier); + for (i = 0; i <= 4; i++) { + if (irq_nr < INT_NUM_IM_OFFSET) { + ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr), + ifxmips_ier); return; } ifxmips_ier += IFXMIPS_ICU_OFFSET; @@ -49,20 +48,18 @@ ifxmips_disable_irq(unsigned int irq_nr) } EXPORT_SYMBOL(ifxmips_disable_irq); -void -ifxmips_mask_and_ack_irq(unsigned int irq_nr) +void ifxmips_mask_and_ack_irq(unsigned int irq_nr) { int i; u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR; irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET) - { - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier); - ifxmips_w32((1 << irq_nr ), ifxmips_isr); + for (i = 0; i <= 4; i++) { + if (irq_nr < INT_NUM_IM_OFFSET) { + ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr), + ifxmips_ier); + ifxmips_w32((1 << irq_nr), ifxmips_isr); return; } ifxmips_ier += IFXMIPS_ICU_OFFSET; @@ -72,18 +69,16 @@ ifxmips_mask_and_ack_irq(unsigned int irq_nr) } EXPORT_SYMBOL(ifxmips_mask_and_ack_irq); -void -ifxmips_enable_irq(unsigned int irq_nr) +void ifxmips_enable_irq(unsigned int irq_nr) { int i; u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; irq_nr -= INT_NUM_IRQ0; - for(i = 0; i <= 4; i++) - { - if(irq_nr < INT_NUM_IM_OFFSET) - { - ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier); + for (i = 0; i <= 4; i++) { + if (irq_nr < INT_NUM_IM_OFFSET) { + ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr), + ifxmips_ier); return; } ifxmips_ier += IFXMIPS_ICU_OFFSET; @@ -92,22 +87,19 @@ ifxmips_enable_irq(unsigned int irq_nr) } EXPORT_SYMBOL(ifxmips_enable_irq); -static unsigned int -ifxmips_startup_irq(unsigned int irq) +static unsigned int ifxmips_startup_irq(unsigned int irq) { ifxmips_enable_irq(irq); return 0; } -static void -ifxmips_end_irq(unsigned int irq) +static void ifxmips_end_irq(unsigned int irq) { - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ifxmips_enable_irq (irq); + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ifxmips_enable_irq(irq); } -static struct hw_interrupt_type -ifxmips_irq_type = { +static struct hw_interrupt_type ifxmips_irq_type = { "IFXMIPS", .startup = ifxmips_startup_irq, .enable = ifxmips_enable_irq, @@ -119,8 +111,7 @@ ifxmips_irq_type = { .end = ifxmips_end_irq, }; -static inline int -ls1bit32(unsigned long x) +static inline int ls1bit32(unsigned long x) { __asm__ ( ".set push \n" @@ -132,72 +123,110 @@ ls1bit32(unsigned long x) return 31 - x; } -void -ifxmips_hw_irqdispatch(int module) +void ifxmips_hw_irqdispatch(int module) { u32 irq; irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET)); - if(irq == 0) + if (irq == 0) return; /* we need to do this due to a silicon bug */ irq = ls1bit32(irq); do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); - if((irq == 22) && (module == 0)){ - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT); - } + if ((irq == 22) && (module == 0)) + ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, + IFXMIPS_EBU_PCC_ISTAT); } -asmlinkage void -plat_irq_dispatch(void) +#ifdef CONFIG_CPU_MIPSR2_IRQ_VI +#define DEFINE_HWx_IRQDISPATCH(x) \ +static void ifxmips_hw ## x ## _irqdispatch(void)\ +{\ + ifxmips_hw_irqdispatch(x); \ +} +static void ifxmips_hw5_irqdispatch(void) +{ + do_IRQ(MIPS_CPU_TIMER_IRQ); +} +DEFINE_HWx_IRQDISPATCH(0) +DEFINE_HWx_IRQDISPATCH(1) +DEFINE_HWx_IRQDISPATCH(2) +DEFINE_HWx_IRQDISPATCH(3) +DEFINE_HWx_IRQDISPATCH(4) +/*DEFINE_HWx_IRQDISPATCH(5)*/ +#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */ + +asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; unsigned int i; - if(pending & CAUSEF_IP7) - { + if (pending & CAUSEF_IP7) { do_IRQ(MIPS_CPU_TIMER_IRQ); goto out; } else { - for(i = 0; i < 5; i++) - { - if(pending & (CAUSEF_IP2 << i)) - { + for (i = 0; i < 5; i++) { + if (pending & (CAUSEF_IP2 << i)) { ifxmips_hw_irqdispatch(i); goto out; } } } - printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); + printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); out: return; } -static struct irqaction -cascade = { +static struct irqaction cascade = { .handler = no_action, .flags = IRQF_DISABLED, .name = "cascade", }; -void __init -arch_init_irq(void) +void __init arch_init_irq(void) { int i; - for(i = 0; i < 5; i++) + for (i = 0; i < 5; i++) ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET)); mips_cpu_irq_init(); - for(i = 2; i <= 6; i++) + for (i = 2; i <= 6; i++) setup_irq(i, &cascade); - for(i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) - set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq); +#ifdef CONFIG_CPU_MIPSR2_IRQ_VI + if (cpu_has_vint) { + printk(KERN_INFO "Setting up vectored interrupts\n"); + set_vi_handler(2, ifxmips_hw0_irqdispatch); + set_vi_handler(3, ifxmips_hw1_irqdispatch); + set_vi_handler(4, ifxmips_hw2_irqdispatch); + set_vi_handler(5, ifxmips_hw3_irqdispatch); + set_vi_handler(6, ifxmips_hw4_irqdispatch); + set_vi_handler(7, ifxmips_hw5_irqdispatch); + } +#endif /* CONFIG_CPU_MIPSR2_IRQ_VI */ + + for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); + i++) + set_irq_chip_and_handler(i, &ifxmips_irq_type, + handle_level_irq); + + #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | + IE_IRQ3 | IE_IRQ4 | IE_IRQ5); + #else + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | + IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); + #endif +} - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +void __cpuinit arch_fixup_c0_irqs(void) +{ + /* FIXME: check for CPUID and only do fix for specific chips/versions */ + cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; + cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; } diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c index 880febc..ef8750b 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c @@ -14,7 +14,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #include <linux/init.h> @@ -23,49 +23,49 @@ #include <asm/bootinfo.h> #include <asm/ifxmips/ifxmips.h> -static char buf[1024]; +static char buf[1024]; /* for prom_printf() */ + +/* for voice cpu (MIPS24K) */ unsigned int *prom_cp1_base = NULL; unsigned int prom_cp1_size = 0; +/* for Multithreading (APRP) on MIPS34K */ +unsigned long physical_memsize = 0L; + #ifdef IFXMIPS_PROM_ASC0 #define IFXMIPS_ASC_DIFF 0 #else #define IFXMIPS_ASC_DIFF IFXMIPS_ASC_BASE_DIFF #endif -static inline u32 -asc_r32(unsigned long r) +static inline u32 asc_r32(unsigned long r) { - return ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); + return ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); } -static inline void -asc_w32(u32 v, unsigned long r) +static inline void asc_w32(u32 v, unsigned long r) { - ifxmips_w32(v, (u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); + ifxmips_w32(v, (u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); } -void -prom_free_prom_memory(void) +void prom_free_prom_memory(void) { } -void -prom_putchar(char c) +void prom_putchar(char c) { unsigned long flags; local_irq_save(flags); while((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF); - if(c == '\n') + if (c == '\n') asc_w32('\r', IFXMIPS_ASC_TBUF); asc_w32(c, IFXMIPS_ASC_TBUF); local_irq_restore(flags); } -void -prom_printf(const char * fmt, ...) +void prom_printf(const char *fmt, ...) { va_list args; int l; @@ -76,7 +76,7 @@ prom_printf(const char * fmt, ...) va_end(args); buf_end = buf + l; - for(p = buf; p < buf_end; p++) + for (p = buf; p < buf_end; p++) prom_putchar(*p); } @@ -88,41 +88,53 @@ EXPORT_SYMBOL(prom_get_cp1_base); unsigned int prom_get_cp1_size(void) { - return prom_cp1_size; + /* return size im MB */ + return prom_cp1_size>>20; } EXPORT_SYMBOL(prom_get_cp1_size); -void __init -prom_init(void) +void __init prom_init(void) { int argc = fw_arg0; char **argv = (char **) fw_arg1; char **envp = (char **) fw_arg2; - int memsize = 16; + int memsize = 16; /* assume 16M as default */ int i; mips_machtype = MACH_INFINEON_IFXMIPS; - argv = (char**)KSEG1ADDR((unsigned long)argv); - arcs_cmdline[0] = '\0'; - for(i = 1; i < argc; i++) - { - char *a = (char*)KSEG1ADDR(argv[i]); - if(!a) - continue; - if(strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, a); - strcat(arcs_cmdline, " "); + if (argc) { + argv = (char**)KSEG1ADDR((unsigned long)argv); + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) + { + char *a = (char *)KSEG1ADDR(argv[i]); + if (!argv[i]) + continue; + /* for voice cpu on Twinpass/Danube */ + if (cpu_data[0].cputype == CPU_24K) + if (!strncmp(a, "cp1_size=", 9)) { + prom_cp1_size = memparse(a + 9, &a); + continue; + } + if (strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline)) { + prom_printf("cmdline overflow, skipping: %s\n", a); + break; + } + strcat(arcs_cmdline, a); + strcat(arcs_cmdline, " "); + } + if (!*arcs_cmdline) + strcpy(&(arcs_cmdline[0]), + "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"); } - envp = (char**)KSEG1ADDR((unsigned long)envp); while(*envp) { - char *e = (char*)KSEG1ADDR(*envp); + char *e = (char *)KSEG1ADDR(*envp); - if(!strncmp(e, "memsize=", 8)) + if (!strncmp(e, "memsize=", 8)) { e += 8; memsize = simple_strtoul(e, NULL, 10); @@ -130,16 +142,16 @@ prom_init(void) envp++; } - prom_cp1_size = 2; - memsize -= prom_cp1_size; - prom_cp1_base = (unsigned int*)(0xA0000000 + (memsize * 1024 * 1024)); - - prom_printf("Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size); memsize *= 1024 * 1024; - if(!*arcs_cmdline) - strcpy(&(arcs_cmdline[0]), - "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"); + /* only on Twinpass/Danube a second CPU is used for Voice */ + if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size)) { + memsize -= prom_cp1_size; + prom_cp1_base = (unsigned int*)KSEG1ADDR(memsize); + + prom_printf("Using %dMB Ram and reserving %dMB for cp1\n", + memsize>>20, prom_cp1_size>>20); + } add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); } diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c index d94d8ac..c85d753 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c @@ -23,8 +23,7 @@ #include <asm/io.h> #include <asm/ifxmips/ifxmips.h> -static void -ifxmips_machine_restart(char *command) +static void ifxmips_machine_restart(char *command) { printk(KERN_NOTICE "System restart\n"); local_irq_disable(); @@ -33,24 +32,21 @@ ifxmips_machine_restart(char *command) for(;;); } -static void -ifxmips_machine_halt(void) +static void ifxmips_machine_halt(void) { printk(KERN_NOTICE "System halted.\n"); local_irq_disable(); for(;;); } -static void -ifxmips_machine_power_off(void) +static void ifxmips_machine_power_off(void) { printk (KERN_NOTICE "Please turn off the power now.\n"); local_irq_disable(); for(;;); } -void -ifxmips_reboot_setup(void) +void ifxmips_reboot_setup(void) { _machine_restart = ifxmips_machine_restart; _machine_halt = ifxmips_machine_halt; diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c index a29a54d..1cfac14 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c @@ -13,15 +13,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2004 peng.liu@infineon.com - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2004 peng.liu@infineon.com + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #include <linux/init.h> #include <asm/time.h> #include <asm/traps.h> -#include <asm/cpu.h> +#include <linux/cpu.h> #include <asm/irq.h> #include <asm/bootinfo.h> #include <asm/ifxmips/ifxmips.h> @@ -33,17 +33,18 @@ static unsigned int r4k_offset; static unsigned int r4k_cur; +/* required in arch/mips/kernel/kspd.c */ +unsigned long cpu_khz; + extern void ifxmips_reboot_setup(void); -unsigned int -ifxmips_get_cpu_ver(void) +unsigned int ifxmips_get_cpu_ver(void) { return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28; } EXPORT_SYMBOL(ifxmips_get_cpu_ver); -static __inline__ u32 -ifxmips_get_counter_resolution(void) +static inline u32 ifxmips_get_counter_resolution(void) { u32 res; __asm__ __volatile__( @@ -56,27 +57,27 @@ ifxmips_get_counter_resolution(void) : "=&r" (res) : /* no input */ : "memory"); - instruction_hazard(); - return res; + instruction_hazard(); + return res; } -void __init -plat_time_init(void) +void __init plat_time_init(void) { mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution(); r4k_cur = (read_c0_count() + r4k_offset); write_c0_compare(r4k_cur); ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI); - ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); // set clock divider to 1 + ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); /* set clock divider to 1 */ + cpu_khz = ifxmips_get_cpu_hz(); } -void __init -plat_mem_setup(void) +void __init plat_mem_setup(void) { u32 status; - prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver()); + prom_printf("This %s system has a cpu rev of %d\n", get_system_type(), ifxmips_get_cpu_ver()); + /* make sure to have no "reverse endian" for user mode! */ status = read_c0_status(); status &= (~(1<<25)); write_c0_status(status); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c index 738f420..248ced2 100644 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c +++ b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c @@ -369,7 +369,7 @@ ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value if (TIMER_FLAG_MASK_HANDLE (flag) != TIMER_FLAG_NO_HANDLE) { if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL) timer_dev.timer[timer - FIRST_TIMER].arg1 = - (unsigned long) find_task_by_pid ((int) arg1); + (unsigned long) find_task_by_vpid ((int) arg1); irnen_reg = 1 << (timer - FIRST_TIMER); diff --git a/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c b/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c index ea1303c..e1d3793 100644 --- a/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c +++ b/target/linux/ifxmips/files/drivers/char/ifxmips_eeprom.c @@ -16,11 +16,11 @@ * This driver was originally based on the INCA-IP driver, but due to * fundamental conceptual drawbacks there has been changed a lot. * - * Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn <gj@denx.de> - * Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies. + * Based on INCA-IP driver Copyright(c) 2003 Gary Jennejohn <gj@denx.de> + * Based on the VxWorks drivers Copyright(c) 2002, Infineon Technologies. * - * Copyright (C) 2006 infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright(C) 2006 infineon + * Copyright(C) 2007 John Crispin <blogic@openwrt.org> * */ @@ -43,38 +43,38 @@ #include <linux/delay.h> #include <linux/spinlock.h> #include <linux/slab.h> -#include <asm/system.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> -#include <asm/bitops.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/uaccess.h> +#include <linux/bitops.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/version.h> +#include <asm/system.h> #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_irq.h> #include <asm/ifxmips/ifx_ssc_defines.h> #include <asm/ifxmips/ifx_ssc.h> /* allow the user to set the major device number */ -static int ifxmips_eeprom_maj = 0; +static int ifxmips_eeprom_maj; -extern int ifx_ssc_init (void); -extern int ifx_ssc_open (struct inode *inode, struct file *filp); -extern int ifx_ssc_close (struct inode *inode, struct file *filp); -extern void ifx_ssc_cleanup_module (void); -extern int ifx_ssc_ioctl (struct inode *inode, struct file *filp, +extern int ifx_ssc_init(void); +extern int ifx_ssc_open(struct inode *inode, struct file *filp); +extern int ifx_ssc_close(struct inode *inode, struct file *filp); +extern void ifx_ssc_cleanup_module(void); +extern int ifx_ssc_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data); -extern ssize_t ifx_ssc_kwrite (int port, const char *kbuf, size_t len); -extern ssize_t ifx_ssc_kread (int port, char *kbuf, size_t len); +extern ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len); +extern ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len); -extern int ifx_ssc_cs_low (unsigned int pin); -extern int ifx_ssc_cs_high (unsigned int pin); -extern int ifx_ssc_txrx (char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len); -extern int ifx_ssc_tx (char *tx_buf, unsigned int tx_len); -extern int ifx_ssc_rx (char *rx_buf, unsigned int rx_len); +extern int ifx_ssc_cs_low(unsigned int pin); +extern int ifx_ssc_cs_high(unsigned int pin); +extern int ifx_ssc_txrx(char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len); +extern int ifx_ssc_tx(char *tx_buf, unsigned int tx_len); +extern int ifx_ssc_rx(char *rx_buf, unsigned int rx_len); #define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS @@ -88,8 +88,7 @@ extern int ifx_ssc_rx (char *rx_buf, unsigned int rx_len); #define EEPROM_PAGE_SIZE 4 #define EEPROM_SIZE 512 -static int -eeprom_rdsr (void) +static int eeprom_rdsr(void) { int ret = 0; unsigned char cmd = EEPROM_RDSR; @@ -108,15 +107,13 @@ eeprom_rdsr (void) return ret; } -void -eeprom_wip_over (void) +void eeprom_wip_over(void) { while (eeprom_rdsr()) - printk("waiting for eeprom\n"); + printk(KERN_INFO "waiting for eeprom\n"); } -static int -eeprom_wren (void) +static int eeprom_wren(void) { unsigned char cmd = EEPROM_WREN; int ret = 0; @@ -136,8 +133,7 @@ eeprom_wren (void) return ret; } -static int -eeprom_wrsr (void) +static int eeprom_wrsr(void) { int ret = 0; unsigned char cmd[2]; @@ -146,9 +142,8 @@ eeprom_wrsr (void) cmd[0] = EEPROM_WRSR; cmd[1] = 0; - if ((ret = eeprom_wren())) - { - printk ("eeprom_wren fails\n"); + if ((ret = eeprom_wren())) { + printk(KERN_ERR "eeprom_wren fails\n"); goto out1; } @@ -171,23 +166,21 @@ eeprom_wrsr (void) return ret; out: - local_irq_restore (flag); - eeprom_wip_over (); + local_irq_restore(flag); + eeprom_wip_over(); out1: return ret; } -static int -eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len) +static int eeprom_read(unsigned int addr, unsigned char *buf, unsigned int len) { int ret = 0; unsigned char write_buf[2]; unsigned int eff = 0; unsigned long flag; - while (1) - { + while (1) { eeprom_wip_over(); eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE); eff = (eff < len) ? eff : len; @@ -196,13 +189,13 @@ eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len) if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0) goto out; - write_buf[0] = EEPROM_READ | ((unsigned char) ((addr & 0x100) >> 5)); + write_buf[0] = EEPROM_READ | ((unsigned char)((addr & 0x100) >> 5)); write_buf[1] = (addr & 0xff); - if ((ret = ifx_ssc_txrx (write_buf, 2, buf, eff)) != eff) - { - printk("ssc_txrx fails %d\n", ret); - ifx_ssc_cs_high (EEPROM_CS); + ret = ifx_ssc_txrx(write_buf, 2, buf, eff); + if (ret != eff) { + printk(KERN_ERR "ssc_txrx fails %d\n", ret); + ifx_ssc_cs_high(EEPROM_CS); goto out; } @@ -210,7 +203,8 @@ eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len) len -= ret; addr += ret; - if ((ret = ifx_ssc_cs_high(EEPROM_CS))) + ret = ifx_ssc_cs_high(EEPROM_CS); + if (ret) goto out; local_irq_restore(flag); @@ -220,13 +214,12 @@ eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len) } out: - local_irq_restore (flag); + local_irq_restore(flag); out2: return ret; } -static int -eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len) +static int eeprom_write(unsigned int addr, unsigned char *buf, unsigned int len) { int ret = 0; unsigned int eff = 0; @@ -234,23 +227,21 @@ eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len) int i; unsigned char rx_buf[EEPROM_PAGE_SIZE]; - while (1) - { + while (1) { eeprom_wip_over(); - if ((ret = eeprom_wren())) - { - printk("eeprom_wren fails\n"); + if ((ret = eeprom_wren())) { + printk(KERN_ERR "eeprom_wren fails\n"); goto out; } - write_buf[0] = EEPROM_WRITE | ((unsigned char) ((addr & 0x100) >> 5)); + write_buf[0] = EEPROM_WRITE | ((unsigned char)((addr & 0x100) >> 5)); write_buf[1] = (addr & 0xff); eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE); eff = (eff < len) ? eff : len; - printk("EEPROM Write:\n"); + printk(KERN_INFO "EEPROM Write:\n"); for (i = 0; i < eff; i++) { printk("%2x ", buf[i]); if ((i % 16) == 15) @@ -261,16 +252,14 @@ eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len) if ((ret = ifx_ssc_cs_low(EEPROM_CS))) goto out; - if ((ret = ifx_ssc_tx (write_buf, 2)) < 0) - { - printk("ssc_tx fails %d\n", ret); + if ((ret = ifx_ssc_tx(write_buf, 2)) < 0) { + printk(KERN_ERR "ssc_tx fails %d\n", ret); ifx_ssc_cs_high(EEPROM_CS); goto out; } - if ((ret = ifx_ssc_tx (buf, eff)) != eff) - { - printk("ssc_tx fails %d\n", ret); + if ((ret = ifx_ssc_tx(buf, eff)) != eff) { + printk(KERN_ERR "ssc_tx fails %d\n", ret); ifx_ssc_cs_high(EEPROM_CS); goto out; } @@ -279,16 +268,14 @@ eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len) len -= ret; addr += ret; - if ((ret = ifx_ssc_cs_high (EEPROM_CS))) + if ((ret = ifx_ssc_cs_high(EEPROM_CS))) goto out; - printk ("<=="); + printk(KERN_INFO "<=="); eeprom_read((addr - eff), rx_buf, eff); for (i = 0; i < eff; i++) - { - printk ("[%x]", rx_buf[i]); - } - printk ("\n"); + printk("[%x]", rx_buf[i]); + printk("\n"); if (len <= 0) break; @@ -298,81 +285,71 @@ out: return ret; } -int -ifxmips_eeprom_open (struct inode *inode, struct file *filp) +int ifxmips_eeprom_open(struct inode *inode, struct file *filp) { filp->f_pos = 0; return 0; } -int -ifxmips_eeprom_close (struct inode *inode, struct file *filp) +int ifxmips_eeprom_close(struct inode *inode, struct file *filp) { return 0; } -int -ifxmips_eeprom_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int ifxmips_eeprom_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) { return 0; } -ssize_t -ifxmips_eeprom_read (char *buf, size_t len, unsigned int addr) +ssize_t ifxmips_eeprom_read(char *buf, size_t len, unsigned int addr) { int ret = 0; unsigned int data; - printk("addr:=%d\n", addr); - printk("len:=%d\n", len); + printk(KERN_INFO "addr:=%d\n", addr); + printk(KERN_INFO "len:=%d\n", len); - if ((addr + len) > EEPROM_SIZE) - { - printk("invalid len\n"); + if ((addr + len) > EEPROM_SIZE) { + printk(KERN_ERR "invalid len\n"); addr = 0; len = EEPROM_SIZE / 2; } - if ((ret = ifx_ssc_open((struct inode *) 0, NULL))) - { - printk("ifxmips_eeprom_open fails\n"); + if ((ret = ifx_ssc_open((struct inode *)0, NULL))) { + printk(KERN_ERR "ifxmips_ssc_open fails\n"); goto out; } data = (unsigned int)IFX_SSC_MODE_RXTX; - if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) - { - printk("set RXTX mode fails\n"); + if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) { + printk(KERN_ERR "set RXTX mode fails\n"); goto out; } - if ((ret = eeprom_wrsr())) - { - printk("EEPROM reset fails\n"); + if ((ret = eeprom_wrsr())) { + printk(KERN_ERR "EEPROM reset fails\n"); goto out; } - if ((ret = eeprom_read(addr, buf, len))) - { - printk("eeprom read fails\n"); + if ((ret = eeprom_read(addr, buf, len))) { + printk(KERN_ERR "eeprom read fails\n"); goto out; } out: - if (ifx_ssc_close((struct inode *) 0, NULL)) - printk("ifxmips_eeprom_close fails\n"); + if (ifx_ssc_close((struct inode *)0, NULL)) + printk(KERN_ERR "ifxmips_ssc_close fails\n"); return len; } EXPORT_SYMBOL(ifxmips_eeprom_read); -static ssize_t -ifxmips_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * off) +static ssize_t ifxmips_eeprom_fops_read(struct file *filp, char *ubuf, size_t len, loff_t *off) { int ret = 0; unsigned char ssc_rx_buf[EEPROM_SIZE]; - long flag; + unsigned long flag; if (*off >= EEPROM_SIZE) return 0; @@ -385,15 +362,13 @@ ifxmips_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * of local_irq_save(flag); - if ((ret = ifxmips_eeprom_read(ssc_rx_buf, len, *off)) < 0) - { - printk("read fails, err=%x\n", ret); + if ((ret = ifxmips_eeprom_read(ssc_rx_buf, len, *off)) < 0) { + printk(KERN_ERR "read fails, err=%x\n", ret); local_irq_restore(flag); return ret; } - if (copy_to_user((void*)ubuf, ssc_rx_buf, ret) != 0) - { + if (copy_to_user((void *)ubuf, ssc_rx_buf, ret) != 0) { local_irq_restore(flag); ret = -EFAULT; } @@ -404,46 +379,42 @@ ifxmips_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * of return len; } -ssize_t -ifxmips_eeprom_write (char *buf, size_t len, unsigned int addr) +ssize_t ifxmips_eeprom_write(char *buf, size_t len, unsigned int addr) { int ret = 0; unsigned int data; - if ((ret = ifx_ssc_open ((struct inode *) 0, NULL))) - { - printk ("ifxmips_eeprom_open fails\n"); + if ((ret = ifx_ssc_open((struct inode *)0, NULL))) { + printk(KERN_ERR "ifxmips_ssc_open fails\n"); goto out; } data = (unsigned int) IFX_SSC_MODE_RXTX; - if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) - { - printk ("set RXTX mode fails\n"); + if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) { + printk(KERN_ERR "set RXTX mode fails\n"); goto out; } - if ((ret = eeprom_wrsr ())) { - printk ("EEPROM reset fails\n"); + if ((ret = eeprom_wrsr())) { + printk(KERN_ERR "EEPROM reset fails\n"); goto out; } - if ((ret = eeprom_write (addr, buf, len))) { - printk ("eeprom write fails\n"); + if ((ret = eeprom_write(addr, buf, len))) { + printk(KERN_ERR "eeprom write fails\n"); goto out; } out: - if (ifx_ssc_close ((struct inode *) 0, NULL)) - printk ("ifxmips_eeprom_close fails\n"); + if (ifx_ssc_close((struct inode *)0, NULL)) + printk(KERN_ERR "ifxmips_ssc_close fails\n"); return ret; } EXPORT_SYMBOL(ifxmips_eeprom_write); -static ssize_t -ifxmips_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff_t * off) +static ssize_t ifxmips_eeprom_fops_write(struct file *filp, const char *ubuf, size_t len, loff_t *off) { int ret = 0; unsigned char ssc_tx_buf[EEPROM_SIZE]; @@ -454,10 +425,10 @@ ifxmips_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff if (len + *off > EEPROM_SIZE) len = EEPROM_SIZE - *off; - if ((ret = copy_from_user (ssc_tx_buf, ubuf, len))) + if ((ret = copy_from_user(ssc_tx_buf, ubuf, len))) return EFAULT; - ret = ifxmips_eeprom_write (ssc_tx_buf, len, *off); + ret = ifxmips_eeprom_write(ssc_tx_buf, len, *off); if (ret > 0) *off = ret; @@ -465,8 +436,7 @@ ifxmips_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff return ret; } -loff_t -ifxmips_eeprom_llseek (struct file * filp, loff_t off, int whence) +loff_t ifxmips_eeprom_llseek(struct file *filp, loff_t off, int whence) { loff_t newpos; switch (whence) { @@ -491,51 +461,47 @@ ifxmips_eeprom_llseek (struct file * filp, loff_t off, int whence) } static struct file_operations ifxmips_eeprom_fops = { - owner:THIS_MODULE, - llseek:ifxmips_eeprom_llseek, - read:ifxmips_eeprom_fops_read, - write:ifxmips_eeprom_fops_write, - ioctl:ifxmips_eeprom_ioctl, - open:ifxmips_eeprom_open, - release:ifxmips_eeprom_close, + .owner = THIS_MODULE, + .llseek = ifxmips_eeprom_llseek, + .read = ifxmips_eeprom_fops_read, + .write = ifxmips_eeprom_fops_write, + .ioctl = ifxmips_eeprom_ioctl, + .open = ifxmips_eeprom_open, + .release = ifxmips_eeprom_close, }; -int __init -ifxmips_eeprom_init (void) +int __init ifxmips_eeprom_init(void) { int ret = 0; ifxmips_eeprom_maj = register_chrdev(0, "eeprom", &ifxmips_eeprom_fops); - if (ifxmips_eeprom_maj < 0) - { - printk("failed to register eeprom device\n"); + if (ifxmips_eeprom_maj < 0) { + printk(KERN_ERR "failed to register eeprom device\n"); ret = -EINVAL; - + goto out; } - printk("ifxmips_eeprom : /dev/eeprom mayor %d\n", ifxmips_eeprom_maj); + printk(KERN_INFO "ifxmips_eeprom : /dev/eeprom mayor %d\n", ifxmips_eeprom_maj); out: return ret; } -void __exit -ifxmips_eeprom_cleanup_module (void) +void __exit ifxmips_eeprom_cleanup_module(void) { - /*if (unregister_chrdev (ifxmips_eeprom_maj, "eeprom")) { - printk ("Unable to unregister major %d for the EEPROM\n", + /*if (unregister_chrdev(ifxmips_eeprom_maj, "eeprom")) { + printk(KERN_ERR "Unable to unregister major %d for the EEPROM\n", maj); }*/ } -module_exit (ifxmips_eeprom_cleanup_module); -module_init (ifxmips_eeprom_init); - -MODULE_LICENSE ("GPL"); -MODULE_AUTHOR ("Peng Liu"); -MODULE_DESCRIPTION ("IFAP EEPROM driver"); -MODULE_SUPPORTED_DEVICE ("ifxmips_eeprom"); +module_exit(ifxmips_eeprom_cleanup_module); +module_init(ifxmips_eeprom_init); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Peng Liu"); +MODULE_DESCRIPTION("IFAP EEPROM driver"); +MODULE_SUPPORTED_DEVICE("ifxmips_eeprom"); diff --git a/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c b/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c index 35b32e8..5d61356 100644 --- a/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c +++ b/target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c @@ -13,17 +13,19 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2006 infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright(C) 2006 infineon + * Copyright(C) 2007 John Crispin <blogic@openwrt.org> * */ -// ### TO DO: general issues: -// - power management -// - interrupt handling (direct/indirect) -// - pin/mux-handling (just overall concept due to project dependency) -// - multiple instances capability -// - slave functionality +/* +### TO DO: general issues: + - power management + - interrupt handling (direct/indirect) + - pin/mux-handling (just overall concept due to project dependency) + - multiple instances capability + - slave functionality +*/ #include <linux/module.h> #include <linux/errno.h> @@ -42,24 +44,23 @@ #include <linux/delay.h> #include <linux/spinlock.h> #include <linux/slab.h> - -#include <asm/system.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> -#include <asm/bitops.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/uaccess.h> +#include <linux/bitops.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/version.h> +#include <asm/system.h> #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_irq.h> #include <asm/ifxmips/ifx_ssc_defines.h> #include <asm/ifxmips/ifx_ssc.h> /* allow the user to set the major device number */ -static int maj = 0; +static int maj; /* * This is the per-channel data structure containing pointers, flags @@ -69,28 +70,25 @@ static int maj = 0; static struct ifx_ssc_port *isp; /* other forward declarations */ -static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info); -static void tx_int (struct ifx_ssc_port *); +static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info); +static void tx_int(struct ifx_ssc_port *); -extern unsigned int ifxmips_get_fpi_hz (void); -extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr); +extern unsigned int ifxmips_get_fpi_hz(void); +extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); -static inline unsigned int -ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info) +static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info) { unsigned int rmc; rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET; - if (rmc == 0) - { - printk ("ifx_ssc_get_kernel_clk rmc==0 \n"); + if (rmc == 0) { + printk("ifx_ssc_get_kernel_clk rmc==0 \n"); return 0; } - return ifxmips_get_fpi_hz () / rmc; + return ifxmips_get_fpi_hz() / rmc; } -inline static void -rx_int (struct ifx_ssc_port *info) +static inline void rx_int(struct ifx_ssc_port *info) { int fifo_fill_lev, bytes_in_buf, i; unsigned long tmp_val; @@ -99,9 +97,9 @@ rx_int (struct ifx_ssc_port *info) /* number of words waiting in the RX FIFO */ fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET; bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr; - // transfer with 32 bits per entry + /* transfer with 32 bits per entry */ while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) { - tmp_ptr = (unsigned long *) info->rxbuf_ptr; + tmp_ptr = (unsigned long *)info->rxbuf_ptr; *tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB); info->rxbuf_ptr += 4; info->stats.rxBytes += 4; @@ -109,7 +107,7 @@ rx_int (struct ifx_ssc_port *info) bytes_in_buf -= 4; } - // now do the rest as mentioned in STATE.RXBV + /* now do the rest as mentioned in STATE.RXBV */ while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) { rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET; if (rx_valid_cnt == 0) @@ -120,8 +118,7 @@ rx_int (struct ifx_ssc_port *info) tmp_val = ifxmips_r32(IFXMIPS_SSC_RB); - for (i = 0; i < rx_valid_cnt; i++) - { + for (i = 0; i < rx_valid_cnt; i++) { *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff; bytes_in_buf--; info->rxbuf_ptr++; @@ -129,13 +126,11 @@ rx_int (struct ifx_ssc_port *info) info->stats.rxBytes += rx_valid_cnt; } - // check if transfer is complete - if (info->rxbuf_ptr >= info->rxbuf_end) - { + /* check if transfer is complete */ + if (info->rxbuf_ptr >= info->rxbuf_end) { disable_irq(IFXMIPS_SSC_RIR); - wake_up_interruptible (&info->rwait); - } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0)) - { + wake_up_interruptible(&info->rwait); + } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0)) { if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE) ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); else @@ -143,13 +138,12 @@ rx_int (struct ifx_ssc_port *info) } } -inline static void -tx_int (struct ifx_ssc_port *info) +static inline void tx_int(struct ifx_ssc_port *info) { int fifo_space, fill, i; fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - - ((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET); + -((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET); if (fifo_space == 0) return; @@ -159,71 +153,64 @@ tx_int (struct ifx_ssc_port *info) if (fill > fifo_space * 4) fill = fifo_space * 4; - for (i = 0; i < fill / 4; i++) - { - // at first 32 bit access - ifxmips_w32(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB); + for (i = 0; i < fill / 4; i++) { + /* at first 32 bit access */ + ifxmips_w32(*(UINT32 *)info->txbuf_ptr, IFXMIPS_SSC_TB); info->txbuf_ptr += 4; } fifo_space -= fill / 4; info->stats.txBytes += fill & ~0x3; fill &= 0x3; - if ((fifo_space > 0) & (fill > 1)) - { - // trailing 16 bit access - WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB); + if ((fifo_space > 0) & (fill > 1)) { + /* trailing 16 bit access */ + WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); info->txbuf_ptr += 2; info->stats.txBytes += 2; fifo_space--; fill -= 2; } - if ((fifo_space > 0) & (fill > 0)) - { - // trailing 8 bit access - WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB); + if ((fifo_space > 0) & (fill > 0)) { + /* trailing 8 bit access */ + WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); info->txbuf_ptr++; info->stats.txBytes++; } - // check if transmission complete - if (info->txbuf_ptr >= info->txbuf_end) - { + /* check if transmission complete */ + if (info->txbuf_ptr >= info->txbuf_end) { disable_irq(IFXMIPS_SSC_TIR); - kfree (info->txbuf); + kfree(info->txbuf); info->txbuf = NULL; } } -irqreturn_t -ifx_ssc_rx_int (int irq, void *dev_id) +irqreturn_t ifx_ssc_rx_int(int irq, void *dev_id) { - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; - rx_int (info); + struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; + rx_int(info); return IRQ_HANDLED; } -irqreturn_t -ifx_ssc_tx_int (int irq, void *dev_id) +irqreturn_t ifx_ssc_tx_int(int irq, void *dev_id) { - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; - tx_int (info); + struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; + tx_int(info); return IRQ_HANDLED; } -irqreturn_t -ifx_ssc_err_int (int irq, void *dev_id) +irqreturn_t ifx_ssc_err_int(int irq, void *dev_id) { - struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id; + struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; unsigned int state; unsigned int write_back = 0; unsigned long flags; - local_irq_save (flags); + local_irq_save(flags); state = ifxmips_r32(IFXMIPS_SSC_STATE); if ((state & IFX_SSC_STATE_RX_UFL) != 0) { @@ -254,54 +241,53 @@ ifx_ssc_err_int (int irq, void *dev_id) if (write_back) ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE); - local_irq_restore (flags); + local_irq_restore(flags); return IRQ_HANDLED; } -static void -ifx_ssc_abort (struct ifx_ssc_port *info) +static void ifx_ssc_abort(struct ifx_ssc_port *info) { unsigned long flags; bool enabled; - local_irq_save (flags); + local_irq_save(flags); disable_irq(IFXMIPS_SSC_RIR); disable_irq(IFXMIPS_SSC_TIR); disable_irq(IFXMIPS_SSC_EIR); - local_irq_restore (flags); + local_irq_restore(flags); - // disable SSC (also aborts a receive request!) - // ### TO DO: Perhaps it's better to abort after the receiption of a - // complete word. The disable cuts the transmission immediatly and - // releases the chip selects. This could result in unpredictable - // behavior of connected external devices! + /* disable SSC(also aborts a receive request!) */ + /* ### TO DO: Perhaps it's better to abort after the receiption of a + complete word. The disable cuts the transmission immediatly and + releases the chip selects. This could result in unpredictable + behavior of connected external devices! + */ enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0; ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - // flush fifos + /* flush fifos */ ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON); ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON); - // free txbuf - if (info->txbuf != NULL) - { - kfree (info->txbuf); + /* free txbuf */ + if (info->txbuf != NULL) { + kfree(info->txbuf); info->txbuf = NULL; } - // wakeup read process + /* wakeup read process */ if (info->rxbuf != NULL) - wake_up_interruptible (&info->rwait); + wake_up_interruptible(&info->rwait); - // clear pending int's + /* clear pending int's */ ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR); ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR); ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR); - // clear error flags + /* clear error flags */ ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE); if (enabled) @@ -313,19 +299,17 @@ ifx_ssc_abort (struct ifx_ssc_port *info) * This routine is called whenever a port is opened. It enforces * exclusive opening of a port and enables interrupts, etc. */ -int -ifx_ssc_open (struct inode *inode, struct file *filp) +int ifx_ssc_open(struct inode *inode, struct file *filp) { struct ifx_ssc_port *info; int line; int from_kernel = 0; - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) { + if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) { from_kernel = 1; line = (int) inode; - } else { - line = MINOR (filp->f_dentry->d_inode->i_rdev); - } + } else + line = MINOR(filp->f_dentry->d_inode->i_rdev); /* don't open more minor devices than we can support */ if (line < 0 || line >= PORT_CNT) @@ -353,7 +337,7 @@ ifx_ssc_open (struct inode *inode, struct file *filp) /* clear all error bits */ ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE); - // clear pending interrupts + /* clear pending interrupts */ ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR); ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR); ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR); @@ -364,16 +348,15 @@ ifx_ssc_open (struct inode *inode, struct file *filp) } EXPORT_SYMBOL(ifx_ssc_open); -int -ifx_ssc_close (struct inode *inode, struct file *filp) +int ifx_ssc_close(struct inode *inode, struct file *filp) { struct ifx_ssc_port *info; int idx; - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) + if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) idx = (int) inode; else - idx = MINOR (filp->f_dentry->d_inode->i_rdev); + idx = MINOR(filp->f_dentry->d_inode->i_rdev); if (idx < 0 || idx >= PORT_CNT) return -ENXIO; @@ -392,26 +375,25 @@ ifx_ssc_close (struct inode *inode, struct file *filp) } EXPORT_SYMBOL(ifx_ssc_close); -static ssize_t -ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel) +static ssize_t ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf, + size_t len, int from_kernel) { ssize_t ret_val; unsigned long flags; if (info->opts.modeRxTx == IFX_SSC_MODE_TX) return -EFAULT; - local_irq_save (flags); + local_irq_save(flags); info->rxbuf_ptr = info->rxbuf; info->rxbuf_end = info->rxbuf + len; - local_irq_restore (flags); + local_irq_restore(flags); /* Vinetic driver always works in IFX_SSC_MODE_RXTX */ /* TXRX in poll mode */ - while (info->rxbuf_ptr < info->rxbuf_end) - { + while (info->rxbuf_ptr < info->rxbuf_end) { if (info->txbuf_ptr < info->txbuf_end) - tx_int (info); + tx_int(info); - rx_int (info); + rx_int(info); }; ret_val = info->rxbuf_ptr - info->rxbuf; @@ -419,31 +401,29 @@ ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int return ret_val; } -static ssize_t -ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel) +static ssize_t ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, + size_t len, int from_kernel) { ssize_t ret_val; unsigned long flags; - DECLARE_WAITQUEUE (wait, current); + DECLARE_WAITQUEUE(wait, current); if (info->opts.modeRxTx == IFX_SSC_MODE_TX) return -EFAULT; - local_irq_save (flags); + local_irq_save(flags); info->rxbuf_ptr = info->rxbuf; info->rxbuf_end = info->rxbuf + len; - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) - { - if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf)) - { - local_irq_restore (flags); - printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__); + if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { + if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf)) { + local_irq_restore(flags); + printk("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__); return -EFAULT; } local_irq_restore(flags); - tx_int (info); + tx_int(info); if (info->txbuf_ptr < info->txbuf_end) enable_irq(IFXMIPS_SSC_TIR); @@ -460,18 +440,17 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_ ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ); } - __add_wait_queue (&info->rwait, &wait); - set_current_state (TASK_INTERRUPTIBLE); + __add_wait_queue(&info->rwait, &wait); + set_current_state(TASK_INTERRUPTIBLE); do { - local_irq_save (flags); + local_irq_save(flags); if (info->rxbuf_ptr >= info->rxbuf_end) break; - local_irq_restore (flags); + local_irq_restore(flags); - if (signal_pending (current)) - { + if (signal_pending(current)) { ret_val = -ERESTARTSYS; goto out; } @@ -479,38 +458,33 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_ } while (1); ret_val = info->rxbuf_ptr - info->rxbuf; - local_irq_restore (flags); + local_irq_restore(flags); out: current->state = TASK_RUNNING; - __remove_wait_queue (&info->rwait, &wait); + __remove_wait_queue(&info->rwait, &wait); - return (ret_val); + return ret_val; } -static ssize_t -ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf, - size_t len, int from_kernel) +static ssize_t ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf, + size_t len, int from_kernel) { if (info->opts.modeRxTx == IFX_SSC_MODE_RX) return -EFAULT; info->txbuf_ptr = info->txbuf; info->txbuf_end = len + info->txbuf; - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - { - tx_int (info); + if (info->opts.modeRxTx == IFX_SSC_MODE_TX) { + tx_int(info); if (info->txbuf_ptr < info->txbuf_end) - { enable_irq(IFXMIPS_SSC_TIR); - } } return len; } -ssize_t -ifx_ssc_kread (int port, char *kbuf, size_t len) +ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len) { struct ifx_ssc_port *info; ssize_t ret_val; @@ -523,20 +497,18 @@ ifx_ssc_kread (int port, char *kbuf, size_t len) info = &isp[port]; - if (info->rxbuf != NULL) - { - printk ("SSC device busy\n"); + if (info->rxbuf != NULL) { + printk("SSC device busy\n"); return -EBUSY; } info->rxbuf = kbuf; - if (info->rxbuf == NULL) - { - printk ("SSC device error\n"); + if (info->rxbuf == NULL) { + printk("SSC device error\n"); return -EINVAL; } - ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1); + ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1); info->rxbuf = NULL; disable_irq(IFXMIPS_SSC_RIR); @@ -545,8 +517,7 @@ ifx_ssc_kread (int port, char *kbuf, size_t len) } EXPORT_SYMBOL(ifx_ssc_kread); -ssize_t -ifx_ssc_kwrite (int port, const char *kbuf, size_t len) +ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len) { struct ifx_ssc_port *info; ssize_t ret_val; @@ -559,13 +530,13 @@ ifx_ssc_kwrite (int port, const char *kbuf, size_t len) info = &isp[port]; - // check if transmission in progress + /* check if transmission in progress */ if (info->txbuf != NULL) return -EBUSY; - info->txbuf = (char *) kbuf; + info->txbuf = (char *)kbuf; - ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1); + ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1); if (ret_val < 0) info->txbuf = NULL; @@ -574,72 +545,68 @@ ifx_ssc_kwrite (int port, const char *kbuf, size_t len) } EXPORT_SYMBOL(ifx_ssc_kwrite); -static ssize_t -ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off) +static ssize_t ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off) { ssize_t ret_val; int idx; struct ifx_ssc_port *info; - idx = MINOR (filp->f_dentry->d_inode->i_rdev); + idx = MINOR(filp->f_dentry->d_inode->i_rdev); info = &isp[idx]; if (info->rxbuf != NULL) return -EBUSY; - info->rxbuf = kmalloc (len + 3, GFP_KERNEL); + info->rxbuf = kmalloc(len + 3, GFP_KERNEL); if (info->rxbuf == NULL) return -ENOMEM; - ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0); - if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0) + ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0); + if (copy_to_user((void *)ubuf, info->rxbuf, ret_val) != 0) ret_val = -EFAULT; disable_irq(IFXMIPS_SSC_RIR); - kfree (info->rxbuf); + kfree(info->rxbuf); info->rxbuf = NULL; - return (ret_val); + return ret_val; } -static ssize_t -ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off) +static ssize_t ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off) { int idx; struct ifx_ssc_port *info; int ret_val; if (len == 0) - return (0); + return 0; - idx = MINOR (filp->f_dentry->d_inode->i_rdev); + idx = MINOR(filp->f_dentry->d_inode->i_rdev); info = &isp[idx]; if (info->txbuf != NULL) return -EBUSY; - info->txbuf = kmalloc (len + 3, GFP_KERNEL); + info->txbuf = kmalloc(len + 3, GFP_KERNEL); if (info->txbuf == NULL) return -ENOMEM; - ret_val = copy_from_user (info->txbuf, ubuf, len); + ret_val = copy_from_user(info->txbuf, ubuf, len); if (ret_val == 0) - ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0); + ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0); else ret_val = -EFAULT; - if (ret_val < 0) - { - kfree (info->txbuf); + if (ret_val < 0) { + kfree(info->txbuf); info->txbuf = NULL; } - return (ret_val); + return ret_val; } -static struct ifx_ssc_frm_status * -ifx_ssc_frm_status_get (struct ifx_ssc_port *info) +static struct ifx_ssc_frm_status *ifx_ssc_frm_status_get(struct ifx_ssc_port *info) { unsigned long tmp; @@ -655,9 +622,7 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info) return &info->frm_status; } - -static struct ifx_ssc_frm_opts * -ifx_ssc_frm_control_get (struct ifx_ssc_port *info) +static struct ifx_ssc_frm_opts *ifx_ssc_frm_control_get(struct ifx_ssc_port *info) { unsigned long tmp; @@ -672,8 +637,7 @@ ifx_ssc_frm_control_get (struct ifx_ssc_port *info) return &info->frm_opts; } -static int -ifx_ssc_frm_control_set (struct ifx_ssc_port *info) +static int ifx_ssc_frm_control_set(struct ifx_ssc_port *info) { unsigned long tmp; @@ -685,12 +649,12 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info) || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET))) return -EINVAL; - // read interrupt bits (they're not changed here) + /* read interrupt bits(they're not changed here) */ tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) & (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE); - // set all values with respect to it's bit position (for data and pause - // length set N-1) + /* set all values with respect to it's bit position(for data and pause + length set N-1) */ tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET; tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET; @@ -703,8 +667,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info) return 0; } -static int -ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val) +static int ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val) { unsigned long tmp; @@ -722,8 +685,7 @@ ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val) return 0; } -static int -ifx_ssc_sethwopts (struct ifx_ssc_port *info) +static int ifx_ssc_sethwopts(struct ifx_ssc_port *info) { unsigned long flags, bits; struct ifx_ssc_hwopts *opts = &info->opts; @@ -754,8 +716,7 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info) if (opts->clockPolarity) bits |= IFX_SSC_CON_CLOCK_FALL; - switch (opts->modeRxTx) - { + switch (opts->modeRxTx) { case IFX_SSC_MODE_TX: bits |= IFX_SSC_CON_RX_OFF; break; @@ -764,27 +725,27 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info) break; } - local_irq_save (flags); + local_irq_save(flags); ifxmips_w32(bits, IFXMIPS_SSC_CON); ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) | - (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON); + (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON); ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT); - //master mode + /* master mode */ if (opts->masterSelect) ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE); else ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE); - // init serial framing + /* init serial framing */ ifxmips_w32(0, IFXMIPS_SSC_SFCON); /* set up the port pins */ - //check for general requirements to switch (external) pad/pin characteristics + /* check for general requirements to switch(external) pad/pin characteristics */ /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */ /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */ - /* Set p0.15 to alternative 01, others to 00 (In/OUT) */ + /* Set p0.15 to alternative 01, others to 00(In/OUT) */ *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000); *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000))); *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000))); @@ -800,13 +761,12 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info) /*TODO: CS4 CS5 CS6 */ *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000); - local_irq_restore (flags); + local_irq_restore(flags); return 0; } -static int -ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud) +static int ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud) { unsigned int ifx_ssc_clock; unsigned int br; @@ -815,13 +775,12 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud) int retval = 0; ifx_ssc_clock = ifx_ssc_get_kernel_clk(info); - if (ifx_ssc_clock == 0) - { + if (ifx_ssc_clock == 0) { retval = -EINVAL; goto out; } - local_irq_save (flags); + local_irq_save(flags); enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED); ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); @@ -831,8 +790,8 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud) if (br > 0xffff || ((br == 0) && ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) { - local_irq_restore (flags); - printk ("%s: invalid baudrate %u\n", __func__, baud); + local_irq_restore(flags); + printk("%s: invalid baudrate %u\n", __func__, baud); return -EINVAL; } @@ -847,8 +806,7 @@ out: return retval; } -static int -ifx_ssc_hwinit (struct ifx_ssc_port *info) +static int ifx_ssc_hwinit(struct ifx_ssc_port *info) { unsigned long flags; bool enabled; @@ -856,26 +814,24 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info) enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED); ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE); - if (ifx_ssc_sethwopts (info) < 0) - { - printk ("%s: setting the hardware options failed\n", __func__); + if (ifx_ssc_sethwopts(info) < 0) { + printk("%s: setting the hardware options failed\n", __func__); return -EINVAL; } - if (ifx_ssc_set_baud (info, info->baud) < 0) - { - printk ("%s: setting the baud rate failed\n", __func__); + if (ifx_ssc_set_baud(info, info->baud) < 0) { + printk("%s: setting the baud rate failed\n", __func__); return -EINVAL; } - local_irq_save (flags); + local_irq_save(flags); /* TX FIFO */ ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON); /* RX FIFO */ ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON); - local_irq_restore (flags); + local_irq_restore(flags); if (enabled) ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE); @@ -883,8 +839,8 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info) return 0; } -int -ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data) +int ifx_ssc_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long data) { struct ifx_ssc_port *info; int line, ret_val = 0; @@ -892,49 +848,46 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne unsigned long tmp; int from_kernel = 0; - if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) - { + if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) { from_kernel = 1; line = (int) inode; - } else { - line = MINOR (filp->f_dentry->d_inode->i_rdev); - } + } else + line = MINOR(filp->f_dentry->d_inode->i_rdev); if (line < 0 || line >= PORT_CNT) return -ENXIO; info = &isp[line]; - switch (cmd) - { + switch (cmd) { case IFX_SSC_STATS_READ: /* data must be a pointer to a struct ifx_ssc_statistics */ if (from_kernel) - memcpy ((void *) data, (void *) &info->stats, - sizeof (struct ifx_ssc_statistics)); - else if (copy_to_user ((void *) data, - (void *) &info->stats, - sizeof (struct ifx_ssc_statistics))) + memcpy((void *)data, (void *)&info->stats, + sizeof(struct ifx_ssc_statistics)); + else if (copy_to_user((void *)data, + (void *)&info->stats, + sizeof(struct ifx_ssc_statistics))) ret_val = -EFAULT; break; case IFX_SSC_STATS_RESET: /* just resets the statistics counters */ - memset ((void *) &info->stats, 0, - sizeof (struct ifx_ssc_statistics)); + memset((void *)&info->stats, 0, + sizeof(struct ifx_ssc_statistics)); break; case IFX_SSC_BAUD_SET: /* if the buffers are not empty then the port is */ /* busy and we shouldn't change things on-the-fly! */ if (!info->txbuf || !info->rxbuf || - (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) { + (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) { ret_val = -EBUSY; break; } /* misuse flags */ if (from_kernel) - flags = *((unsigned long *) data); - else if (copy_from_user ((void *) &flags, - (void *) data, sizeof (flags))) { + flags = *((unsigned long *)data); + else if (copy_from_user((void *)&flags, + (void *)data, sizeof(flags))) { ret_val = -EFAULT; break; } @@ -942,7 +895,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne ret_val = -EINVAL; break; } - if (ifx_ssc_set_baud (info, flags) < 0) { + if (ifx_ssc_set_baud(info, flags) < 0) { ret_val = -EINVAL; break; } @@ -950,41 +903,41 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne break; case IFX_SSC_BAUD_GET: if (from_kernel) - *((unsigned int *) data) = info->baud; - else if (copy_to_user ((void *) data, - (void *) &info->baud, - sizeof (unsigned long))) + *((unsigned int *)data) = info->baud; + else if (copy_to_user((void *)data, + (void *)&info->baud, + sizeof(unsigned long))) ret_val = -EFAULT; break; case IFX_SSC_RXTX_MODE_SET: if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, - (void *) data, sizeof (tmp))) { + tmp = *((unsigned long *)data); + else if (copy_from_user((void *)&tmp, + (void *)data, sizeof(tmp))) { ret_val = -EFAULT; break; } - ret_val = ifx_ssc_rxtx_mode_set (info, tmp); + ret_val = ifx_ssc_rxtx_mode_set(info, tmp); break; case IFX_SSC_RXTX_MODE_GET: tmp = ifxmips_r32(IFXMIPS_SSC_CON) & (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)); if (from_kernel) - *((unsigned int *) data) = tmp; - else if (copy_to_user ((void *) data, - (void *) &tmp, sizeof (tmp))) + *((unsigned int *)data) = tmp; + else if (copy_to_user((void *)data, + (void *)&tmp, sizeof(tmp))) ret_val = -EFAULT; break; case IFX_SSC_ABORT: - ifx_ssc_abort (info); + ifx_ssc_abort(info); break; case IFX_SSC_GPO_OUT_SET: if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, - (void *) data, sizeof (tmp))) { + tmp = *((unsigned long *)data); + else if (copy_from_user((void *)&tmp, + (void *)data, sizeof(tmp))) { ret_val = -EFAULT; break; } @@ -996,88 +949,86 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne break; case IFX_SSC_GPO_OUT_CLR: if (from_kernel) - tmp = *((unsigned long *) data); - else if (copy_from_user ((void *) &tmp, (void *) data, sizeof (tmp))) { + tmp = *((unsigned long *)data); + else if (copy_from_user((void *)&tmp, (void *)data, sizeof(tmp))) { ret_val = -EFAULT; break; } if (tmp > IFX_SSC_MAX_GPO_OUT) ret_val = -EINVAL; - else { + else ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS), IFXMIPS_SSC_WHBGPOSTAT); - } break; case IFX_SSC_GPO_OUT_GET: tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT); if (from_kernel) - *((unsigned int *) data) = tmp; - else if (copy_to_user ((void *) data, - (void *) &tmp, sizeof (tmp))) + *((unsigned int *)data) = tmp; + else if (copy_to_user((void *)data, + (void *)&tmp, sizeof(tmp))) ret_val = -EFAULT; break; case IFX_SSC_FRM_STATUS_GET: - ifx_ssc_frm_status_get (info); + ifx_ssc_frm_status_get(info); if (from_kernel) - memcpy ((void *) data, (void *) &info->frm_status, - sizeof (struct ifx_ssc_frm_status)); - else if (copy_to_user ((void *) data, - (void *) &info->frm_status, - sizeof (struct ifx_ssc_frm_status))) + memcpy((void *)data, (void *)&info->frm_status, + sizeof(struct ifx_ssc_frm_status)); + else if (copy_to_user((void *)data, + (void *)&info->frm_status, + sizeof(struct ifx_ssc_frm_status))) ret_val = -EFAULT; break; case IFX_SSC_FRM_CONTROL_GET: - ifx_ssc_frm_control_get (info); + ifx_ssc_frm_control_get(info); if (from_kernel) - memcpy ((void *) data, (void *) &info->frm_opts, - sizeof (struct ifx_ssc_frm_opts)); - else if (copy_to_user ((void *) data, - (void *) &info->frm_opts, - sizeof (struct ifx_ssc_frm_opts))) + memcpy((void *)data, (void *)&info->frm_opts, + sizeof(struct ifx_ssc_frm_opts)); + else if (copy_to_user((void *)data, + (void *)&info->frm_opts, + sizeof(struct ifx_ssc_frm_opts))) ret_val = -EFAULT; break; case IFX_SSC_FRM_CONTROL_SET: if (from_kernel) - memcpy ((void *) &info->frm_opts, (void *) data, - sizeof (struct ifx_ssc_frm_opts)); - else if (copy_to_user ((void *) &info->frm_opts, - (void *) data, - sizeof (struct ifx_ssc_frm_opts))) { + memcpy((void *)&info->frm_opts, (void *)data, + sizeof(struct ifx_ssc_frm_opts)); + else if (copy_to_user((void *)&info->frm_opts, + (void *)data, + sizeof(struct ifx_ssc_frm_opts))) { ret_val = -EFAULT; break; } - ret_val = ifx_ssc_frm_control_set (info); + ret_val = ifx_ssc_frm_control_set(info); break; case IFX_SSC_HWOPTS_SET: /* data must be a pointer to a struct ifx_ssc_hwopts */ /* if the buffers are not empty then the port is */ /* busy and we shouldn't change things on-the-fly! */ if (!info->txbuf || !info->rxbuf || - (ifxmips_r32(IFXMIPS_SSC_STATE) + (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) { ret_val = -EBUSY; break; } if (from_kernel) - memcpy ((void *) &info->opts, (void *) data, - sizeof (struct ifx_ssc_hwopts)); - else if (copy_from_user ((void *) &info->opts, - (void *) data, sizeof(struct ifx_ssc_hwopts))) { + memcpy((void *)&info->opts, (void *)data, + sizeof(struct ifx_ssc_hwopts)); + else if (copy_from_user((void *)&info->opts, + (void *)data, sizeof(struct ifx_ssc_hwopts))) { ret_val = -EFAULT; break; } - if (ifx_ssc_hwinit (info) < 0) { + if (ifx_ssc_hwinit(info) < 0) ret_val = -EIO; - } break; case IFX_SSC_HWOPTS_GET: /* data must be a pointer to a struct ifx_ssc_hwopts */ if (from_kernel) - memcpy ((void *) data, (void *) &info->opts, - sizeof (struct ifx_ssc_hwopts)); - else if (copy_to_user ((void *) data, - (void *) &info->opts, - sizeof (struct ifx_ssc_hwopts))) + memcpy((void *)data, (void *)&info->opts, + sizeof(struct ifx_ssc_hwopts)); + else if (copy_to_user((void *)data, + (void *)&info->opts, + sizeof(struct ifx_ssc_hwopts))) ret_val = -EFAULT; break; default: @@ -1089,16 +1040,15 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne EXPORT_SYMBOL(ifx_ssc_ioctl); static struct file_operations ifx_ssc_fops = { - .owner = THIS_MODULE, - .read = ifx_ssc_read, - .write = ifx_ssc_write, - .ioctl = ifx_ssc_ioctl, - .open = ifx_ssc_open, - .release = ifx_ssc_close, + .owner = THIS_MODULE, + .read = ifx_ssc_read, + .write = ifx_ssc_write, + .ioctl = ifx_ssc_ioctl, + .open = ifx_ssc_open, + .release = ifx_ssc_close, }; -int __init -ifx_ssc_init (void) +int __init ifx_ssc_init(void) { struct ifx_ssc_port *info; int i, nbytes; @@ -1107,27 +1057,25 @@ ifx_ssc_init (void) ret_val = -ENOMEM; nbytes = PORT_CNT * sizeof(struct ifx_ssc_port); - isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL); + isp = kmalloc(nbytes, GFP_KERNEL); - if (isp == NULL) - { + if (isp == NULL) { printk("%s: no memory for isp\n", __func__); - return (ret_val); + return ret_val; } memset(isp, 0, nbytes); ret_val = -ENXIO; - if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk ("Unable to register major %d for the Infineon SSC\n", maj); - if (maj == 0) - { + i = register_chrdev(maj, "ssc", &ifx_ssc_fops); + if (i < 0) { + printk("Unable to register major %d for the Infineon SSC\n", maj); + if (maj == 0) { goto errout; } else { maj = 0; - if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk ("Unable to register major %d for the Infineon SSC\n", maj); + i = register_chrdev(maj, "ssc", &ifx_ssc_fops); + if (i < 0) { + printk("Unable to register major %d for the Infineon SSC\n", maj); goto errout; } } @@ -1161,56 +1109,53 @@ ifx_ssc_init (void) info->rxbuf = NULL; info->txbuf = NULL; /* values specific to SSC1 */ - if (i == 0) { + if (i == 0) info->mapbase = IFXMIPS_SSC_BASE_ADDR; - } ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC); - init_waitqueue_head (&info->rwait); + init_waitqueue_head(&info->rwait); - local_irq_save (flags); + local_irq_save(flags); - // init serial framing register + /* init serial framing register */ ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON); ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info); - if (ret_val) - { + if (ret_val) { printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_TIR); local_irq_restore(flags); goto errout; } ret_val = request_irq(IFXMIPS_SSC_RIR, ifx_ssc_rx_int, IRQF_DISABLED, "ifx_ssc_rx", info); - if (ret_val) - { - printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR); - local_irq_restore (flags); + if (ret_val) { + printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR); + local_irq_restore(flags); goto irqerr; } ret_val = request_irq(IFXMIPS_SSC_EIR, ifx_ssc_err_int, IRQF_DISABLED, "ifx_ssc_err", info); - if (ret_val) - { - printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR); - local_irq_restore (flags); + if (ret_val) { + printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR); + local_irq_restore(flags); goto irqerr; } ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN); - //enable_irq(IFXMIPS_SSC_TIR); - //enable_irq(IFXMIPS_SSC_RIR); - //enable_irq(IFXMIPS_SSC_EIR); + #if 0 + enable_irq(IFXMIPS_SSC_TIR); + enable_irq(IFXMIPS_SSC_RIR); + enable_irq(IFXMIPS_SSC_EIR); + #endif - local_irq_restore (flags); + local_irq_restore(flags); } for (i = 0; i < PORT_CNT; i++) { info = &isp[i]; - if (ifx_ssc_hwinit (info) < 0) - { - printk ("%s: hardware init failed for port %d\n", __func__, i); + if (ifx_ssc_hwinit(info) < 0) { + printk("%s: hardware init failed for port %d\n", __func__, i); goto irqerr; } } @@ -1223,12 +1168,11 @@ irqerr: free_irq(IFXMIPS_SSC_RIR, &isp[0]); free_irq(IFXMIPS_SSC_EIR, &isp[0]); errout: - kfree (isp); - return (ret_val); + kfree(isp); + return ret_val; } -void -ifx_ssc_cleanup_module (void) +void __exit ifx_ssc_cleanup_module(void) { int i; @@ -1238,39 +1182,37 @@ ifx_ssc_cleanup_module (void) free_irq(IFXMIPS_SSC_RIR, &isp[i]); free_irq(IFXMIPS_SSC_EIR, &isp[i]); } - kfree (isp); + kfree(isp); } module_init(ifx_ssc_init); module_exit(ifx_ssc_cleanup_module); - -inline int -ifx_ssc_cs_low (u32 pin) +inline int ifx_ssc_cs_low(u32 pin) { int ret = 0; - if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin))) - printk ("clear CS %d fails\n", pin); - wmb (); + ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin); + if (ret) + printk("clear CS %d fails\n", pin); + wmb(); return ret; } EXPORT_SYMBOL(ifx_ssc_cs_low); -inline int -ifx_ssc_cs_high (u32 pin) +inline int ifx_ssc_cs_high(u32 pin) { int ret = 0; - if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin))) - printk ("set CS %d fails\n", pin); - wmb (); + ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin); + if (ret) + printk("set CS %d fails\n", pin); + wmb(); return ret; } EXPORT_SYMBOL(ifx_ssc_cs_high); -static int -ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) +static int ssc_session(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) { int ret = 0; @@ -1280,132 +1222,111 @@ ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) u8 mode = 0; if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) { - printk ("invalid parameters\n"); + printk("invalid parameters\n"); ret = -EINVAL; goto ssc_session_exit; - } - else if (tx_buf == NULL || tx_len == 0) { + } else if (tx_buf == NULL || tx_len == 0) { if (rx_buf != NULL && rx_len != 0) { mode = IFX_SSC_MODE_RX; - } - else { - printk ("invalid parameters\n"); + } else { + printk("invalid parameters\n"); ret = -EINVAL; goto ssc_session_exit; } - } - else if (rx_buf == NULL || rx_len == 0) { - if (tx_buf != NULL && tx_len != 0) { + } else if (rx_buf == NULL || rx_len == 0) { + if (tx_buf != NULL && tx_len != 0) mode = IFX_SSC_MODE_TX; - } else { - printk ("invalid parameters\n"); + printk("invalid parameters\n"); ret = -EINVAL; goto ssc_session_exit; } - } - else { + } else mode = IFX_SSC_MODE_RXTX; - } - if (mode == IFX_SSC_MODE_RXTX) { + if (mode == IFX_SSC_MODE_RXTX) eff_size = tx_len + rx_len; - } - else if (mode == IFX_SSC_MODE_RX) { + else if (mode == IFX_SSC_MODE_RX) eff_size = rx_len; - } - else { + else eff_size = tx_len; - } //4 bytes alignment, required by driver /* change by TaiCheng */ //if (in_irq()){ if (1) { - ssc_tx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), + ssc_tx_buf = kmalloc(sizeof(char) * + ((eff_size + 3) & (~3)), GFP_ATOMIC); - ssc_rx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), + ssc_rx_buf = kmalloc(sizeof(char) * + ((eff_size + 3) & (~3)), GFP_ATOMIC); - } - else { - ssc_tx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), + } else { + ssc_tx_buf = kmalloc(sizeof(char) * + ((eff_size + 3) & (~3)), GFP_KERNEL); - ssc_rx_buf = - (char *) kmalloc (sizeof (char) * - ((eff_size + 3) & (~3)), + ssc_rx_buf = kmalloc(sizeof(char) * + ((eff_size + 3) & (~3)), GFP_KERNEL); } if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) { - printk ("no memory for size of %d\n", eff_size); + printk("no memory for size of %d\n", eff_size); ret = -ENOMEM; goto ssc_session_exit; } - memset ((void *) ssc_tx_buf, 0, eff_size); - memset ((void *) ssc_rx_buf, 0, eff_size); + memset((void *)ssc_tx_buf, 0, eff_size); + memset((void *)ssc_rx_buf, 0, eff_size); - if (tx_len > 0) { - memcpy (ssc_tx_buf, tx_buf, tx_len); - } + if (tx_len > 0) + memcpy(ssc_tx_buf, tx_buf, tx_len); - ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size); + ret = ifx_ssc_kwrite(0, ssc_tx_buf, eff_size); - if (ret > 0) { - ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite - } + if (ret > 0) + ssc_tx_buf = NULL; /* should be freed by ifx_ssc_kwrite */ if (ret != eff_size) { - printk ("ifx_ssc_write return %d\n", ret); + printk("ifx_ssc_write return %d\n", ret); goto ssc_session_exit; } - ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size); + ret = ifx_ssc_kread(0, ssc_rx_buf, eff_size); if (ret != eff_size) { - printk ("ifx_ssc_read return %d\n", ret); + printk("ifx_ssc_read return %d\n", ret); goto ssc_session_exit; } - memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len); + memcpy(rx_buf, ssc_rx_buf + tx_len, rx_len); - if (mode == IFX_SSC_MODE_TX) { + if (mode == IFX_SSC_MODE_TX) ret = tx_len; - } - else { + else ret = rx_len; - } - ssc_session_exit: +ssc_session_exit: if (ssc_tx_buf != NULL) - kfree (ssc_tx_buf); + kfree(ssc_tx_buf); if (ssc_rx_buf != NULL) - kfree (ssc_rx_buf); + kfree(ssc_rx_buf); + + if (ret < 0) + printk("ssc session fails\n"); - if (ret < 0) { - printk ("ssc session fails\n"); - } return ret; } -int -ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) +int ifx_ssc_txrx(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len) { return ssc_session(tx_buf, tx_len, rx_buf, rx_len); } EXPORT_SYMBOL(ifx_ssc_txrx); -int -ifx_ssc_tx (char *tx_buf, u32 tx_len) +int ifx_ssc_tx(char *tx_buf, u32 tx_len) { return ssc_session(tx_buf, tx_len, NULL, 0); } EXPORT_SYMBOL(ifx_ssc_tx); -int -ifx_ssc_rx (char *rx_buf, u32 rx_len) +int ifx_ssc_rx(char *rx_buf, u32 rx_len) { return ssc_session(NULL, 0, rx_buf, rx_len); } diff --git a/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c b/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c index 090516c..7efc032 100644 --- a/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c +++ b/target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c @@ -25,65 +25,61 @@ #include <linux/fs.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <asm/uaccess.h> -#include <asm/unistd.h> +#include <linux/uaccess.h> +#include <linux/unistd.h> #include <linux/errno.h> +#include <linux/leds.h> +#include <linux/delay.h> + #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_gpio.h> #include <asm/ifxmips/ifxmips_pmu.h> -#include <linux/leds.h> -#include <linux/delay.h> -#define DRVNAME "ifxmips_led" +#define DRVNAME "ifxmips_led" #define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING //#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING -#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ +#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ #define IFXMIPS_LED_GPIO_PORT 0 -#define IFXMIPS_MAX_LED 24 +#define IFXMIPS_MAX_LED 24 struct ifxmips_led { struct led_classdev cdev; u8 bit; }; -void -ifxmips_led_set (unsigned int led) +void ifxmips_led_set (unsigned int led) { led &= 0xffffff; ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0); } EXPORT_SYMBOL(ifxmips_led_set); -void -ifxmips_led_clear (unsigned int led) +void ifxmips_led_clear (unsigned int led) { led = ~(led & 0xffffff); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0); } EXPORT_SYMBOL(ifxmips_led_clear); -void -ifxmips_led_blink_set (unsigned int led) +void ifxmips_led_blink_set (unsigned int led) { led &= 0xffffff; ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0); } EXPORT_SYMBOL(ifxmips_led_blink_set); -void -ifxmips_led_blink_clear (unsigned int led) +void ifxmips_led_blink_clear (unsigned int led) { led = ~(led & 0xffffff); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0); } EXPORT_SYMBOL(ifxmips_led_blink_clear); -void -ifxmips_ledapi_set(struct led_classdev *led_cdev, enum led_brightness value) +void ifxmips_ledapi_set(struct led_classdev *led_cdev, enum led_brightness value) { struct ifxmips_led *led_dev = container_of(led_cdev, struct ifxmips_led, cdev); @@ -93,14 +89,12 @@ ifxmips_ledapi_set(struct led_classdev *led_cdev, enum led_brightness value) ifxmips_led_clear(1 << led_dev->bit); } -void -ifxmips_led_setup_gpio (void) +void ifxmips_led_setup_gpio (void) { int i = 0; /* we need to setup pins SH,D,ST (4,5,6) */ - for (i = 4; i < 7; i++) - { + for (i = 4; i < 7; i++) { ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i); ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i); ifxmips_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i); @@ -108,8 +102,7 @@ ifxmips_led_setup_gpio (void) } } -static int -ifxmips_led_probe(struct platform_device *dev) +static int ifxmips_led_probe(struct platform_device *dev) { int i = 0; @@ -142,12 +135,11 @@ ifxmips_led_probe(struct platform_device *dev) /* per default, the leds are turned on */ ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED); - for(i = 0; i < IFXMIPS_MAX_LED; i++) - { + for (i = 0; i < IFXMIPS_MAX_LED; i++) { struct ifxmips_led *tmp = kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL); tmp->cdev.brightness_set = ifxmips_ledapi_set; tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL); - sprintf((char*)tmp->cdev.name, "ifxmips:led:%02d", i); + sprintf((char *)tmp->cdev.name, "ifxmips:led:%02d", i); tmp->cdev.default_trigger = NULL; tmp->bit = i; led_classdev_register(&dev->dev, &tmp->cdev); @@ -156,14 +148,12 @@ ifxmips_led_probe(struct platform_device *dev) return 0; } -static int -ifxmips_led_remove(struct platform_device *pdev) +static int ifxmips_led_remove(struct platform_device *pdev) { return 0; } -static struct -platform_driver ifxmips_led_driver = { +static struct platform_driver ifxmips_led_driver = { .probe = ifxmips_led_probe, .remove = ifxmips_led_remove, .driver = { @@ -172,8 +162,7 @@ platform_driver ifxmips_led_driver = { }, }; -int __init -ifxmips_led_init (void) +int __init ifxmips_led_init (void) { int ret = platform_driver_register(&ifxmips_led_driver); if (ret) @@ -182,8 +171,7 @@ ifxmips_led_init (void) return ret; } -void __exit -ifxmips_led_exit (void) +void __exit ifxmips_led_exit (void) { platform_driver_unregister(&ifxmips_led_driver); } diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c b/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c index aed241b..b4faf05 100644 --- a/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c +++ b/target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c @@ -26,11 +26,12 @@ #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> #include <linux/mtd/cfi.h> +#include <linux/magic.h> +#include <linux/platform_device.h> + #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_prom.h> #include <asm/ifxmips/ifxmips_ebu.h> -#include <linux/magic.h> -#include <linux/platform_device.h> #ifndef CONFIG_MTD_PARTITIONS #error Please enable CONFIG_MTD_PARTITIONS diff --git a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c index fafb5a5..695e0b7 100644 --- a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c +++ b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c @@ -48,43 +48,39 @@ struct ifxmips_mii_priv { static struct net_device *ifxmips_mii0_dev; static unsigned char mac_addr[MAX_ADDR_LEN]; -void -ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data) +void ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data) { u32 val = MDIO_ACC_REQUEST | ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) | phy_data; - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); } EXPORT_SYMBOL(ifxmips_write_mdio); -unsigned short -ifxmips_read_mdio(u32 phy_addr, u32 phy_reg) +unsigned short ifxmips_read_mdio(u32 phy_addr, u32 phy_reg) { u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ | ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) ; ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); - while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){}; + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) ; val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; return val; } EXPORT_SYMBOL(ifxmips_read_mdio); -int -ifxmips_ifxmips_mii_open(struct net_device *dev) +int ifxmips_ifxmips_mii_open(struct net_device *dev) { - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)dev->priv; + struct dma_device_info *dma_dev = priv->dma_device; int i; - for (i = 0; i < dma_dev->max_rx_chan_num; i++) - { + for (i = 0; i < dma_dev->max_rx_chan_num; i++) { if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON) (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]); } @@ -92,10 +88,10 @@ ifxmips_ifxmips_mii_open(struct net_device *dev) return 0; } -int -ifxmips_mii_release(struct net_device *dev){ - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; +int ifxmips_mii_release(struct net_device *dev) +{ + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)dev->priv; + struct dma_device_info *dma_dev = priv->dma_device; int i; for (i = 0; i < dma_dev->max_rx_chan_num; i++) @@ -104,32 +100,28 @@ ifxmips_mii_release(struct net_device *dev){ return 0; } -int -ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev) +int ifxmips_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) { - struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)dev->priv; - unsigned char* buf = NULL; + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)dev->priv; + unsigned char *buf = NULL; struct sk_buff *skb = NULL; int len = 0; - len = dma_device_read(dma_dev, &buf, (void**)&skb); + len = dma_device_read(dma_dev, &buf, (void **)&skb); - if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) - { - printk(KERN_INFO "ifxmips_mii0: packet too large %d\n",len); + if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { + printk(KERN_INFO "ifxmips_mii0: packet too large %d\n", len); goto ifxmips_mii_hw_receive_err_exit; } /* remove CRC */ len -= 4; - if (skb == NULL) - { + if (skb == NULL) { printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n"); goto ifxmips_mii_hw_receive_err_exit; } - if (len > (skb->end - skb->tail)) - { + if (len > (skb->end - skb->tail)) { printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail); goto ifxmips_mii_hw_receive_err_exit; @@ -145,8 +137,7 @@ ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev) return 0; ifxmips_mii_hw_receive_err_exit: - if (len == 0) - { + if (len == 0) { if (skb) dev_kfree_skb_any(skb); priv->stats.rx_errors++; @@ -157,52 +148,48 @@ ifxmips_mii_hw_receive_err_exit: } } -int -ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev) +int ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev) { int ret = 0; struct ifxmips_mii_priv *priv = dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; + struct dma_device_info *dma_dev = priv->dma_device; ret = dma_device_write(dma_dev, buf, len, priv->skb); return ret; } -int -ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev) +int ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev) { int len; char *data; struct ifxmips_mii_priv *priv = dev->priv; - struct dma_device_info* dma_dev = priv->dma_device; + struct dma_device_info *dma_dev = priv->dma_device; len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; data = skb->data; priv->skb = skb; dev->trans_start = jiffies; - // TODO we got more than 1 dma channel, so we should do something intelligent - // here to select one + /* TODO: we got more than 1 dma channel, + so we should do something intelligent here to select one */ dma_dev->current_tx_chan = 0; wmb(); - if (ifxmips_mii_hw_tx(data, len, dev) != len) - { + if (ifxmips_mii_hw_tx(data, len, dev) != len) { dev_kfree_skb_any(skb); priv->stats.tx_errors++; priv->stats.tx_dropped++; } else { priv->stats.tx_packets++; - priv->stats.tx_bytes+=len; + priv->stats.tx_bytes += len; } return 0; } -void -ifxmips_mii_tx_timeout(struct net_device *dev) +void ifxmips_mii_tx_timeout(struct net_device *dev) { int i; - struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv; + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)dev->priv; priv->stats.tx_errors++; for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) @@ -211,13 +198,11 @@ ifxmips_mii_tx_timeout(struct net_device *dev) return; } -int -dma_intr_handler(struct dma_device_info* dma_dev, int status) +int dma_intr_handler(struct dma_device_info *dma_dev, int status) { int i; - switch(status) - { + switch (status) { case RCV_INT: ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev); break; @@ -225,9 +210,8 @@ dma_intr_handler(struct dma_device_info* dma_dev, int status) case TX_BUF_FULL_INT: printk(KERN_INFO "ifxmips_mii0: tx buffer full\n"); netif_stop_queue(ifxmips_mii0_dev); - for (i = 0; i < dma_dev->max_tx_chan_num; i++) - { - if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON) + for (i = 0; i < dma_dev->max_tx_chan_num; i++) { + if ((dma_dev->tx_chan[i])->control == IFXMIPS_DMA_CH_ON) dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); } break; @@ -243,8 +227,7 @@ dma_intr_handler(struct dma_device_info* dma_dev, int status) return 0; } -unsigned char* -ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) +unsigned char *ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) { unsigned char *buffer = NULL; struct sk_buff *skb = NULL; @@ -253,36 +236,32 @@ ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) if (skb == NULL) return NULL; - buffer = (unsigned char*)(skb->data); + buffer = (unsigned char *)(skb->data); skb_reserve(skb, 2); - *(int*)opt = (int)skb; + *(int *)opt = (int)skb; *byte_offset = 2; return buffer; } -void -ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt) +void ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt) { struct sk_buff *skb = NULL; - if (opt == NULL) - { + if (opt == NULL) { kfree(dataptr); } else { - skb = (struct sk_buff*)opt; + skb = (struct sk_buff *)opt; dev_kfree_skb_any(skb); } } -static struct net_device_stats* -ifxmips_get_stats(struct net_device *dev) +static struct net_device_stats *ifxmips_get_stats(struct net_device *dev) { return (struct net_device_stats *)dev->priv; } -static int -ifxmips_mii_dev_init(struct net_device *dev) +static int ifxmips_mii_dev_init(struct net_device *dev) { int i; struct ifxmips_mii_priv *priv; @@ -298,7 +277,7 @@ ifxmips_mii_dev_init(struct net_device *dev) memset(dev->priv, 0, sizeof(struct ifxmips_mii_priv)); priv = dev->priv; priv->dma_device = dma_device_reserve("PPE"); - if (!priv->dma_device){ + if (!priv->dma_device) { BUG(); return -ENODEV; } @@ -307,8 +286,7 @@ ifxmips_mii_dev_init(struct net_device *dev) priv->dma_device->intr_handler = &dma_intr_handler; priv->dma_device->max_rx_chan_num = 4; - for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) - { + for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) { priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE; priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON; } @@ -322,16 +300,14 @@ ifxmips_mii_dev_init(struct net_device *dev) dma_device_register(priv->dma_device); printk(KERN_INFO "ifxmips_mii0: using mac="); - for (i = 0; i < 6; i++) - { + for (i = 0; i < 6; i++) { dev->dev_addr[i] = mac_addr[i]; printk("%02X%c", dev->dev_addr[i], (i == 5)?('\n'):(':')); } return 0; } -static void -ifxmips_mii_chip_init(int mode) +static void ifxmips_mii_chip_init(int mode) { ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE); @@ -345,19 +321,17 @@ ifxmips_mii_chip_init(int mode) wmb(); } -static int -ifxmips_mii_probe(struct platform_device *dev) +static int ifxmips_mii_probe(struct platform_device *dev) { int result = 0; - unsigned char *mac = (unsigned char*)dev->dev.platform_data; + unsigned char *mac = (unsigned char *)dev->dev.platform_data; ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv)); ifxmips_mii0_dev->init = ifxmips_mii_dev_init; memcpy(mac_addr, mac, 6); strcpy(ifxmips_mii0_dev->name, "eth%d"); ifxmips_mii_chip_init(REV_MII_MODE); result = register_netdev(ifxmips_mii0_dev); - if (result) - { + if (result) { printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name); goto out; } @@ -368,10 +342,9 @@ out: return result; } -static int -ifxmips_mii_remove(struct platform_device *dev) +static int ifxmips_mii_remove(struct platform_device *dev) { - struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv; + struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)ifxmips_mii0_dev->priv; printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n"); @@ -383,8 +356,7 @@ ifxmips_mii_remove(struct platform_device *dev) return 0; } -static struct -platform_driver ifxmips_mii_driver = { +static struct platform_driver ifxmips_mii_driver = { .probe = ifxmips_mii_probe, .remove = ifxmips_mii_remove, .driver = { @@ -393,8 +365,7 @@ platform_driver ifxmips_mii_driver = { }, }; -int __init -ifxmips_mii_init(void) +int __init ifxmips_mii_init(void) { int ret = platform_driver_register(&ifxmips_mii_driver); if (ret) @@ -402,8 +373,7 @@ ifxmips_mii_init(void) return ret; } -static void __exit -ifxmips_mii_cleanup(void) +static void __exit ifxmips_mii_cleanup(void) { platform_driver_unregister(&ifxmips_mii_driver); } @@ -414,3 +384,4 @@ module_exit(ifxmips_mii_cleanup); MODULE_LICENSE("GPL"); MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards"); + diff --git a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c b/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c index 2dc8917..d6bf180 100644 --- a/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c +++ b/target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c @@ -42,10 +42,12 @@ #include <linux/sysrq.h> #include <linux/irq.h> #include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/uaccess.h> +#include <linux/bitops.h> + #include <asm/system.h> -#include <asm/io.h> -#include <asm/uaccess.h> -#include <asm/bitops.h> + #include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips_irq.h> @@ -56,19 +58,17 @@ #define UART_DUMMY_UER_RX 1 static void ifxmipsasc_tx_chars(struct uart_port *port); -extern void prom_printf(const char * fmt, ...); +extern void prom_printf(const char *fmt, ...); static struct uart_port ifxmipsasc_port[2]; static struct uart_driver ifxmipsasc_reg; extern unsigned int ifxmips_get_fpi_hz(void); -static void -ifxmipsasc_stop_tx(struct uart_port *port) +static void ifxmipsasc_stop_tx(struct uart_port *port) { return; } -static void -ifxmipsasc_start_tx(struct uart_port *port) +static void ifxmipsasc_start_tx(struct uart_port *port) { unsigned long flags; local_irq_save(flags); @@ -77,26 +77,28 @@ ifxmipsasc_start_tx(struct uart_port *port) return; } -static void -ifxmipsasc_stop_rx(struct uart_port *port) +static void ifxmipsasc_stop_rx(struct uart_port *port) { ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE); } -static void -ifxmipsasc_enable_ms(struct uart_port *port) +static void ifxmipsasc_enable_ms(struct uart_port *port) { } -static void -ifxmipsasc_rx_chars(struct uart_port *port) +#include <linux/version.h> + +static void ifxmipsasc_rx_chars(struct uart_port *port) { +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) + struct tty_struct *tty = port->info->port.tty; +#else struct tty_struct *tty = port->info->tty; +#endif unsigned int ch = 0, rsr = 0, fifocnt; fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; - while(fifocnt--) - { + while (fifocnt--) { u8 flag = TTY_NORMAL; ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF); rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; @@ -107,35 +109,31 @@ ifxmipsasc_rx_chars(struct uart_port *port) * Note that the error handling code is * out of the main execution path */ - if(rsr & ASCSTATE_ANY) - { - if(rsr & ASCSTATE_PE) - { + if (rsr & ASCSTATE_ANY) { + if (rsr & ASCSTATE_PE) { port->icount.parity++; ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE); - } else if(rsr & ASCSTATE_FE) - { + } else if (rsr & ASCSTATE_FE) { port->icount.frame++; ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE); } - if(rsr & ASCSTATE_ROE) - { + if (rsr & ASCSTATE_ROE) { port->icount.overrun++; ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); } rsr &= port->read_status_mask; - if(rsr & ASCSTATE_PE) + if (rsr & ASCSTATE_PE) flag = TTY_PARITY; - else if(rsr & ASCSTATE_FE) + else if (rsr & ASCSTATE_FE) flag = TTY_FRAME; } - if((rsr & port->ignore_status_mask) == 0) + if ((rsr & port->ignore_status_mask) == 0) tty_insert_flip_char(tty, ch, flag); - if(rsr & ASCSTATE_ROE) + if (rsr & ASCSTATE_ROE) /* * Overrun is special, since it's reported * immediately, and doesn't affect the current @@ -143,34 +141,30 @@ ifxmipsasc_rx_chars(struct uart_port *port) */ tty_insert_flip_char(tty, 0, TTY_OVERRUN); } - if(ch != 0) + if (ch != 0) tty_flip_buffer_push(tty); return; } -static void -ifxmipsasc_tx_chars(struct uart_port *port) +static void ifxmipsasc_tx_chars(struct uart_port *port) { struct circ_buf *xmit = &port->info->xmit; - if(uart_tx_stopped(port)) - { + if (uart_tx_stopped(port)) { ifxmipsasc_stop_tx(port); return; } - while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) - { - if(port->x_char) - { + while (((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) + >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) { + if (port->x_char) { ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF); port->icount.tx++; port->x_char = 0; continue; } - if(uart_circ_empty(xmit)) + if (uart_circ_empty(xmit)) break; ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF); @@ -178,66 +172,58 @@ ifxmipsasc_tx_chars(struct uart_port *port) port->icount.tx++; } - if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); } -static irqreturn_t -ifxmipsasc_tx_int(int irq, void *_port) +static irqreturn_t ifxmipsasc_tx_int(int irq, void *_port) { - struct uart_port *port = (struct uart_port*) _port; + struct uart_port *port = (struct uart_port *)_port; ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR); ifxmipsasc_start_tx(port); ifxmips_mask_and_ack_irq(irq); return IRQ_HANDLED; } -static irqreturn_t -ifxmipsasc_er_int(int irq, void *_port) +static irqreturn_t ifxmipsasc_er_int(int irq, void *_port) { - struct uart_port *port = (struct uart_port*) _port; + struct uart_port *port = (struct uart_port *)_port; /* clear any pending interrupts */ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); return IRQ_HANDLED; } -static irqreturn_t -ifxmipsasc_rx_int(int irq, void *_port) +static irqreturn_t ifxmipsasc_rx_int(int irq, void *_port) { - struct uart_port *port = (struct uart_port*)_port; + struct uart_port *port = (struct uart_port *)_port; ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR); - ifxmipsasc_rx_chars((struct uart_port*)port); + ifxmipsasc_rx_chars((struct uart_port *)port); ifxmips_mask_and_ack_irq(irq); return IRQ_HANDLED; } -static unsigned int -ifxmipsasc_tx_empty(struct uart_port *port) +static unsigned int ifxmipsasc_tx_empty(struct uart_port *port) { int status; status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; return status ? 0 : TIOCSER_TEMT; } -static unsigned int -ifxmipsasc_get_mctrl(struct uart_port *port) +static unsigned int ifxmipsasc_get_mctrl(struct uart_port *port) { return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; } -static void -ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl) +static void ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl) { } -static void -ifxmipsasc_break_ctl(struct uart_port *port, int break_state) +static void ifxmipsasc_break_ctl(struct uart_port *port, int break_state) { } -static int -ifxmipsasc_startup(struct uart_port *port) +static int ifxmipsasc_startup(struct uart_port *port) { unsigned long flags; int retval; @@ -249,29 +235,26 @@ ifxmipsasc_startup(struct uart_port *port) ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL); ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); - wmb (); + wmb(); ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON); local_irq_save(flags); retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port); - if(retval) - { - printk("failed to request ifxmipsasc_tx_int\n"); + if (retval) { + printk(KERN_ERR "failed to request ifxmipsasc_tx_int\n"); return retval; } retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port); - if(retval) - { - printk("failed to request ifxmipsasc_rx_int\n"); + if (retval) { + printk(KERN_ERR "failed to request ifxmipsasc_rx_int\n"); goto err1; } retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port); - if(retval) - { - printk("failed to request ifxmipsasc_er_int\n"); + if (retval) { + printk(KERN_ERR "failed to request ifxmipsasc_er_int\n"); goto err2; } @@ -288,8 +271,7 @@ err1: return retval; } -static void -ifxmipsasc_shutdown(struct uart_port *port) +static void ifxmipsasc_shutdown(struct uart_port *port) { free_irq(port->irq, port); free_irq(port->irq + 2, port); @@ -314,8 +296,7 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, cflag = new->c_cflag; iflag = new->c_iflag; - switch(cflag & CSIZE) - { + switch (cflag & CSIZE) { case CS7: con = ASCCON_M_7ASYNC; break; @@ -327,36 +308,34 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, break; } - if(cflag & CSTOPB) + if (cflag & CSTOPB) con |= ASCCON_STP; - if(cflag & PARENB) - { - if(!(cflag & PARODD)) + if (cflag & PARENB) { + if (!(cflag & PARODD)) con &= ~ASCCON_ODD; else con |= ASCCON_ODD; } port->read_status_mask = ASCSTATE_ROE; - if(iflag & INPCK) + if (iflag & INPCK) port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; port->ignore_status_mask = 0; - if(iflag & IGNPAR) + if (iflag & IGNPAR) port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; - if(iflag & IGNBRK) - { + if (iflag & IGNBRK) { /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ - if(iflag & IGNPAR) + if (iflag & IGNPAR) port->ignore_status_mask |= ASCSTATE_ROE; } - if((cflag & CREAD) == 0) + if ((cflag & CREAD) == 0) port->ignore_status_mask |= UART_DUMMY_UER_RX; /* set error signals - framing, parity and overrun, enable receiver */ @@ -368,7 +347,7 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON); /* Set baud rate - take a divider of 2 into account */ - baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); quot = uart_get_divisor(port, baud); quot = quot / 2 - 1; @@ -393,12 +372,10 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, local_irq_restore(flags); } -static const char* -ifxmipsasc_type(struct uart_port *port) +static const char *ifxmipsasc_type(struct uart_port *port) { - if(port->type == PORT_IFXMIPSASC) - { - if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR) + if (port->type == PORT_IFXMIPSASC) { + if (port->membase == (void *)IFXMIPS_ASC_BASE_ADDR) return "asc0"; else return "asc1"; @@ -407,120 +384,109 @@ ifxmipsasc_type(struct uart_port *port) } } -static void -ifxmipsasc_release_port(struct uart_port *port) +static void ifxmipsasc_release_port(struct uart_port *port) { } -static int -ifxmipsasc_request_port(struct uart_port *port) +static int ifxmipsasc_request_port(struct uart_port *port) { return 0; } -static void -ifxmipsasc_config_port(struct uart_port *port, int flags) +static void ifxmipsasc_config_port(struct uart_port *port, int flags) { - if(flags & UART_CONFIG_TYPE) - { + if (flags & UART_CONFIG_TYPE) { port->type = PORT_IFXMIPSASC; ifxmipsasc_request_port(port); } } -static int -ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser) +static int ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser) { int ret = 0; - if(ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC) + if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC) ret = -EINVAL; - if(ser->irq < 0 || ser->irq >= NR_IRQS) + if (ser->irq < 0 || ser->irq >= NR_IRQS) ret = -EINVAL; - if(ser->baud_base < 9600) + if (ser->baud_base < 9600) ret = -EINVAL; return ret; } -static struct uart_ops ifxmipsasc_pops = -{ - .tx_empty = ifxmipsasc_tx_empty, +static struct uart_ops ifxmipsasc_pops = { + .tx_empty = ifxmipsasc_tx_empty, .set_mctrl = ifxmipsasc_set_mctrl, .get_mctrl = ifxmipsasc_get_mctrl, - .stop_tx = ifxmipsasc_stop_tx, - .start_tx = ifxmipsasc_start_tx, - .stop_rx = ifxmipsasc_stop_rx, + .stop_tx = ifxmipsasc_stop_tx, + .start_tx = ifxmipsasc_start_tx, + .stop_rx = ifxmipsasc_stop_rx, .enable_ms = ifxmipsasc_enable_ms, .break_ctl = ifxmipsasc_break_ctl, - .startup = ifxmipsasc_startup, - .shutdown = ifxmipsasc_shutdown, + .startup = ifxmipsasc_startup, + .shutdown = ifxmipsasc_shutdown, .set_termios = ifxmipsasc_set_termios, - .type = ifxmipsasc_type, + .type = ifxmipsasc_type, .release_port = ifxmipsasc_release_port, .request_port = ifxmipsasc_request_port, .config_port = ifxmipsasc_config_port, .verify_port = ifxmipsasc_verify_port, }; -static struct uart_port ifxmipsasc_port[2] = -{ +static struct uart_port ifxmipsasc_port[2] = { { - membase: (void *)IFXMIPS_ASC_BASE_ADDR, - mapbase: IFXMIPS_ASC_BASE_ADDR, - iotype: SERIAL_IO_MEM, - irq: IFXMIPSASC_TIR(0), - uartclk: 0, - fifosize: 16, - type: PORT_IFXMIPSASC, - ops: &ifxmipsasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - line: 0 + .membase = (void *)IFXMIPS_ASC_BASE_ADDR, + .mapbase = IFXMIPS_ASC_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = IFXMIPSASC_TIR(0), + .uartclk = 0, + .fifosize = 16, + .type = PORT_IFXMIPSASC, + .ops = &ifxmipsasc_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0 }, { - membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF), - mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF, - iotype: SERIAL_IO_MEM, - irq: IFXMIPSASC_TIR(1), - uartclk: 0, - fifosize: 16, - type: PORT_IFXMIPSASC, - ops: &ifxmipsasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - line: 1 + .membase = (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF), + .mapbase = IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF, + .iotype = SERIAL_IO_MEM, + .irq = IFXMIPSASC_TIR(1), + .uartclk = 0, + .fifosize = 16, + .type = PORT_IFXMIPSASC, + .ops = &ifxmipsasc_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1 } }; -static void -ifxmipsasc_console_write(struct console *co, const char *s, u_int count) +static void ifxmipsasc_console_write(struct console *co, const char *s, u_int count) { int port = co->index; int i, fifocnt; unsigned long flags; local_irq_save(flags); - for(i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { do { - fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF; - } while(fifocnt == TXFIFO_FULL); + fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) + >> ASCFSTAT_TXFFLOFF; + } while (fifocnt == TXFIFO_FULL); - if(s[i] == '\0') + if (s[i] == '\0') break; - if(s[i] == '\n') - { - ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); + if (s[i] == '\n') { + ifxmips_w32('\r', (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); do { - fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) + fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF; - } while(fifocnt == TXFIFO_FULL); + } while (fifocnt == TXFIFO_FULL); } - ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); + ifxmips_w32(s[i], (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); } local_irq_restore(flags); } -static int __init -ifxmipsasc_console_setup(struct console *co, char *options) +static int __init ifxmipsasc_console_setup(struct console *co, char *options) { int port = co->index; int baud = 115200; @@ -529,7 +495,7 @@ ifxmipsasc_console_setup(struct console *co, char *options) int flow = 'n'; ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz(); ifxmipsasc_port[port].type = PORT_IFXMIPSASC; - if(options) + if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow); } @@ -537,26 +503,25 @@ ifxmipsasc_console_setup(struct console *co, char *options) static struct console ifxmipsasc_console[2] = { { - name: "ttyS", - write: ifxmipsasc_console_write, - device: uart_console_device, - setup: ifxmipsasc_console_setup, - flags: CON_PRINTBUFFER, - index: 0, - data: &ifxmipsasc_reg, + .name = "ttyS", + .write = ifxmipsasc_console_write, + .device = uart_console_device, + .setup = ifxmipsasc_console_setup, + .flags = CON_PRINTBUFFER, + .index = 0, + .data = &ifxmipsasc_reg, }, { - name: "ttyS", - write: ifxmipsasc_console_write, - device: uart_console_device, - setup: ifxmipsasc_console_setup, - flags: CON_PRINTBUFFER, - index: 1, - data: &ifxmipsasc_reg, + .name = "ttyS", + .write = ifxmipsasc_console_write, + .device = uart_console_device, + .setup = ifxmipsasc_console_setup, + .flags = CON_PRINTBUFFER, + .index = 1, + .data = &ifxmipsasc_reg, } }; -static int __init -ifxmipsasc_console_init(void) +static int __init ifxmipsasc_console_init(void) { register_console(&ifxmipsasc_console[0]); register_console(&ifxmipsasc_console[1]); @@ -564,19 +529,17 @@ ifxmipsasc_console_init(void) } console_initcall(ifxmipsasc_console_init); -static struct uart_driver ifxmipsasc_reg = -{ - .owner = THIS_MODULE, - .driver_name = "serial", - .dev_name = "ttyS", - .major = TTY_MAJOR, - .minor = 64, - .nr = 2, - .cons = &ifxmipsasc_console[1], +static struct uart_driver ifxmipsasc_reg = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .nr = 2, + .cons = &ifxmipsasc_console[1], }; -int __init -ifxmipsasc_init(void) +int __init ifxmipsasc_init(void) { int ret; uart_register_driver(&ifxmipsasc_reg); @@ -585,8 +548,7 @@ ifxmipsasc_init(void) return 0; } -void __exit -ifxmipsasc_exit(void) +void __exit ifxmipsasc_exit(void) { uart_unregister_driver(&ifxmipsasc_reg); } diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h index 2180f44..6dc184a 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h @@ -14,36 +14,35 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #ifndef _IFXMIPS_H__ #define _IFXMIPS_H__ -#define ifxmips_r32(reg) __raw_readl(reg) -#define ifxmips_w32(val,reg) __raw_writel(val,reg) +#define ifxmips_r32(reg) __raw_readl(reg) +#define ifxmips_w32(val,reg) __raw_writel(val,reg) #define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) /*------------ GENERAL */ #define BOARD_SYSTEM_TYPE "IFXMIPS" -#define IOPORT_RESOURCE_START 0x10000000 +#define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff -#define IFXMIPS_FLASH_START 0x10000000 -#define IFXMIPS_FLASH_MAX 0x2000000 +#define IFXMIPS_FLASH_START 0x10000000 +#define IFXMIPS_FLASH_MAX 0x02000000 +/*------------ ASC0/1 */ -/*------------ ASC1 */ - -#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400) -#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400) +#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400) +#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400) #define IFXMIPS_ASC_FSTAT 0x0048 #define IFXMIPS_ASC_TBUF 0x0020 -#define IFXMIPS_ASC_WHBSTATE 0x0018 +#define IFXMIPS_ASC_WHBSTATE 0x0018 #define IFXMIPS_ASC_RBUF 0x0024 #define IFXMIPS_ASC_STATE 0x0014 #define IFXMIPS_ASC_IRNCR 0x00F8 @@ -55,7 +54,7 @@ #define IFXMIPS_ASC_BG 0x0050 #define IFXMIPS_ASC_IRNREN 0x00F4 -#define IFXMIPS_ASC_CLC_DISS 0x2 +#define IFXMIPS_ASC_CLC_DISS 0x2 #define ASC_IRNREN_RX_BUF 0x8 #define ASC_IRNREN_TX_BUF 0x4 #define ASC_IRNREN_ERR 0x2 @@ -64,29 +63,29 @@ #define ASC_IRNCR_RIR 0x2 #define ASC_IRNCR_EIR 0x4 #define ASCOPT_CSIZE 0x3 -#define ASCOPT_CS7 0x1 -#define ASCOPT_CS8 0x2 +#define ASCOPT_CS7 0x1 +#define ASCOPT_CS8 0x2 #define ASCOPT_PARENB 0x4 #define ASCOPT_STOPB 0x8 #define ASCOPT_PARODD 0x0 #define ASCOPT_CREAD 0x20 -#define TXFIFO_FL 1 -#define RXFIFO_FL 1 -#define TXFIFO_FULL 16 +#define TXFIFO_FL 1 +#define RXFIFO_FL 1 +#define TXFIFO_FULL 16 #define ASCCLC_RMCMASK 0x0000FF00 #define ASCCLC_RMCOFFSET 8 #define ASCCON_M_8ASYNC 0x0 #define ASCCON_M_7ASYNC 0x2 -#define ASCCON_ODD 0x00000020 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_R 0x00008000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 +#define ASCCON_ODD 0x00000020 +#define ASCCON_STP 0x00000080 +#define ASCCON_BRS 0x00000100 +#define ASCCON_FDE 0x00000200 +#define ASCCON_R 0x00008000 +#define ASCCON_FEN 0x00020000 +#define ASCCON_ROEN 0x00080000 +#define ASCCON_TOEN 0x00100000 +#define ASCSTATE_PE 0x00010000 +#define ASCSTATE_FE 0x00020000 #define ASCSTATE_ROE 0x00080000 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) #define ASCWHBSTATE_CLRREN 0x00000001 @@ -96,54 +95,54 @@ #define ASCWHBSTATE_CLRROE 0x00000020 #define ASCTXFCON_TXFEN 0x0001 #define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 /*------------ RCU */ -#define IFXMIPS_RCU_BASE_ADDR 0xBF203000 +#define IFXMIPS_RCU_BASE_ADDR 0xBF203000 /* reset request */ #define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) -#define IFXMIPS_RCU_RST_CPU1 (1 << 3) +#define IFXMIPS_RCU_RST_CPU1 (1 << 3) #define IFXMIPS_RCU_RST_ALL 0x40000000 -#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7) -#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11) +#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7) +#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11) #define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20) /*------------ GPTU */ -#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 +#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 /* clock control register */ #define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) /* captur reload register */ -#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) +#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) /* timer 6 control register */ -#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) +#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) /*------------ EBU */ -#define IFXMIPS_EBU_BASE_ADDR 0xBE105300 +#define IFXMIPS_EBU_BASE_ADDR 0xBE105300 /* bus configuration register */ #define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) #define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) #define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) -#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) +#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) /*------------ CGU */ @@ -151,34 +150,34 @@ #define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) #define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) #define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) -#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) -#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) -#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) -#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) -#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) -#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) -#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) -#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) -#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) +#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) +#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) +#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) +#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) +#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) +#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) +#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) +#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) +#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) +#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) +#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) /* clock mux */ #define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) #define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) #define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_333M 333333333 +#define CLOCK_60M 60000000 +#define CLOCK_83M 83333333 +#define CLOCK_111M 111111111 +#define CLOCK_133M 133333333 +#define CLOCK_167M 166666667 +#define CLOCK_333M 333333333 /*------------ CGU */ -#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) +#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) #define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) #define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) @@ -186,17 +185,19 @@ /*------------ ICU */ -#define IFXMIPS_ICU_BASE_ADDR 0xBF880200 +#define IFXMIPS_ICU_BASE_ADDR 0xBF880200 #define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) #define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) -#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) -#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) +#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) +#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) #define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) #define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) #define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) +#define IFXMIPS_ICU_IM3_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0080)) +#define IFXMIPS_ICU_IM4_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00A8)) #define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) #define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) @@ -204,24 +205,24 @@ /*------------ ETOP */ -#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000 +#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000 #define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 -#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) +#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) #define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) -#define MII_MODE 1 -#define REV_MII_MODE 2 +#define MII_MODE 1 +#define REV_MII_MODE 2 /* mdio access */ -#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) -#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) +#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) +#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) #define MDIO_ACC_REQUEST 0x80000000 #define MDIO_ACC_READ 0x40000000 #define MDIO_ACC_ADDR_MASK 0x1f -#define MDIO_ACC_ADDR_OFFSET 0x15 +#define MDIO_ACC_ADDR_OFFSET 0x15 #define MDIO_ACC_REG_MASK 0xff #define MDIO_ACC_REG_OFFSET 0x10 #define MDIO_ACC_VAL_MASK 0xffff @@ -242,7 +243,7 @@ /* enet */ #define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) -#define PPE32_CGEN 0x800 +#define PPE32_CGEN 0x800 /*------------ DMA */ @@ -256,32 +257,32 @@ #define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24)) #define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40)) #define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44)) -#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10)) +#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10)) #define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14)) -#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20)) +#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20)) /*------------ PCI */ #define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) -#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) -#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) -#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) -#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) -#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) -#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) -#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) -#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) +#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) +#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) +#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) +#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) +#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) +#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) +#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) +#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) #define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000)) #define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030)) #define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080)) -#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) +#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) #define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044)) #define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048)) #define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C)) #define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010)) -#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) -#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) +#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) +#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) #define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C)) #define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) @@ -296,7 +297,7 @@ /*------------ WDT */ -#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) +#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) #define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) #define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) @@ -304,25 +305,25 @@ /*------------ LED */ -#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) -#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000)) -#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004)) -#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008)) -#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C)) +#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) +#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000)) +#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004)) +#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008)) +#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C)) #define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010)) #define LED_CON0_SWU (1 << 31) #define LED_CON0_AD1 (1 << 25) #define LED_CON0_AD0 (1 << 24) -#define IFXMIPS_LED_2HZ (0) -#define IFXMIPS_LED_4HZ (1 << 23) -#define IFXMIPS_LED_8HZ (2 << 23) -#define IFXMIPS_LED_10HZ (3 << 23) -#define IFXMIPS_LED_MASK (0xf << 23) +#define IFXMIPS_LED_2HZ (0) +#define IFXMIPS_LED_4HZ (1 << 23) +#define IFXMIPS_LED_8HZ (2 << 23) +#define IFXMIPS_LED_10HZ (3 << 23) +#define IFXMIPS_LED_MASK (0xf << 23) -#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31) -#define IFXMIPS_LED_UPD_MASK (3 << 30) +#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31) +#define IFXMIPS_LED_UPD_MASK (3 << 30) #define IFXMIPS_LED_ADSL_SRC (3 << 24) #define IFXMIPS_LED_GROUP0 (1 << 0) @@ -331,7 +332,7 @@ #define IFXMIPS_LED_RISING 0 #define IFXMIPS_LED_FALLING (1 << 26) -#define IFXMIPS_LED_EDGE_MASK (1 << 26) +#define IFXMIPS_LED_EDGE_MASK (1 << 26) /*------------ GPIO */ @@ -344,31 +345,31 @@ #define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) #define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) #define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) -#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) -#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) -#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) -#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) +#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) +#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) +#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) +#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) #define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) #define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) -#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) -#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) -#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) -#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) -#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) -#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) +#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) +#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) +#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) +#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) +#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) +#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) /*------------ SSC */ -#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) +#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) #define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) #define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) #define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) -#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) +#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) #define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) -#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) +#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) #define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) #define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) #define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) @@ -387,10 +388,10 @@ /*------------ MEI */ -#define IFXMIPS_MEI_BASE_ADDR (0xBE116000) +#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000) #define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) -#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) +#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) #define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) #define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) #define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) @@ -402,7 +403,7 @@ #define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) #define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) #define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) -#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) +#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) #define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) #define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) #define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) @@ -432,7 +433,7 @@ /*------------ DEU */ -#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100) +#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100) #define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000)) #define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008)) @@ -471,12 +472,12 @@ /*------------ FUSE */ -#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354) +#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354) /*------------ MPS */ -#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) +#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000)) #define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) @@ -509,7 +510,7 @@ #define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) +#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) +#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) #endif diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h index 02c7aec..d4933ac 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h @@ -20,12 +20,12 @@ #ifndef _IFXMIPS_DMA_H__ #define _IFXMIPS_DMA_H__ -#define RCV_INT 1 +#define RCV_INT 1 #define TX_BUF_FULL_INT 2 #define TRANSMIT_CPT_INT 4 #define IFXMIPS_DMA_CH_ON 1 #define IFXMIPS_DMA_CH_OFF 0 -#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100 +#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100 enum attr_t{ TX = 0, @@ -34,9 +34,9 @@ enum attr_t{ DEFAULT = 3, }; -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 +#define DMA_OWN 1 +#define CPU_OWN 0 +#define DMA_MAJOR 250 #define DMA_DESC_OWN_CPU 0x0 #define DMA_DESC_OWN_DMA 0x80000000 @@ -44,12 +44,12 @@ enum attr_t{ #define DMA_DESC_SOP_SET 0x20000000 #define DMA_DESC_EOP_SET 0x10000000 -#define MISCFG_MASK 0x40 -#define RDERR_MASK 0x20 -#define CHOFF_MASK 0x10 -#define DESCPT_MASK 0x8 -#define DUR_MASK 0x4 -#define EOP_MASK 0x2 +#define MISCFG_MASK 0x40 +#define RDERR_MASK 0x20 +#define CHOFF_MASK 0x10 +#define DESCPT_MASK 0x8 +#define DUR_MASK 0x4 +#define EOP_MASK 0x2 #define DMA_DROP_MASK (1<<31) @@ -57,7 +57,7 @@ enum attr_t{ #define IFXMIPS_DMA_TX 1 typedef struct dma_chan_map { - char dev_name[15]; + const char *dev_name; enum attr_t dir; int pri; int irq; @@ -75,7 +75,7 @@ typedef struct rx_desc{ volatile u32 C:1; volatile u32 OWN:1; volatile u32 Data_Pointer; - /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ + /* fix me:should be 28 bits here, 32 bits just for host simulation purpose */ }_rx_desc; typedef struct tx_desc{ @@ -86,9 +86,9 @@ typedef struct tx_desc{ volatile u32 SoP:1; volatile u32 C:1; volatile u32 OWN:1; - volatile u32 Data_Pointer;//fix me:should be 28 bits here + volatile u32 Data_Pointer;/* fix me:should be 28 bits here */ }_tx_desc; -#else //BIG +#else /* BIG */ typedef struct rx_desc{ union { @@ -128,64 +128,64 @@ typedef struct tx_desc{ #endif //ENDIAN typedef struct dma_channel_info{ - /*relative channel number*/ - int rel_chan_no; - /*class for this channel for QoS*/ - int pri; - /*specify byte_offset*/ - int byte_offset; - /*direction*/ - int dir; - /*irq number*/ - int irq; - /*descriptor parameter*/ - int desc_base; - int desc_len; - int curr_desc; - int prev_desc;/*only used if it is a tx channel*/ - /*weight setting for WFQ algorithm*/ - int weight; - int default_weight; - int packet_size; - int burst_len; - /*on or off of this channel*/ - int control; - /**optional information for the upper layer devices*/ + /*relative channel number*/ + int rel_chan_no; + /*class for this channel for QoS*/ + int pri; + /*specify byte_offset*/ + int byte_offset; + /*direction*/ + int dir; + /*irq number*/ + int irq; + /*descriptor parameter*/ + int desc_base; + int desc_len; + int curr_desc; + int prev_desc;/*only used if it is a tx channel*/ + /*weight setting for WFQ algorithm*/ + int weight; + int default_weight; + int packet_size; + int burst_len; + /*on or off of this channel*/ + int control; + /**optional information for the upper layer devices*/ #if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA) - void* opt[64]; + void* opt[64]; #else - void* opt[25]; + void* opt[25]; #endif - /*Pointer to the peripheral device who is using this channel*/ - void* dma_dev; - /*channel operations*/ - void (*open)(struct dma_channel_info* pCh); - void (*close)(struct dma_channel_info* pCh); - void (*reset)(struct dma_channel_info* pCh); - void (*enable_irq)(struct dma_channel_info* pCh); - void (*disable_irq)(struct dma_channel_info* pCh); + /*Pointer to the peripheral device who is using this channel*/ + void* dma_dev; + /*channel operations*/ + void (*open)(struct dma_channel_info* pCh); + void (*close)(struct dma_channel_info* pCh); + void (*reset)(struct dma_channel_info* pCh); + void (*enable_irq)(struct dma_channel_info* pCh); + void (*disable_irq)(struct dma_channel_info* pCh); }_dma_channel_info; typedef struct dma_device_info{ - /*device name of this peripheral*/ - char device_name[15]; - int reserved; - int tx_burst_len; - int rx_burst_len; - int default_weight; - int current_tx_chan; + /*device name of this peripheral*/ + char device_name[15]; + int reserved; + int tx_burst_len; + int rx_burst_len; + int default_weight; + int current_tx_chan; int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - int max_rx_chan_num; - int max_tx_chan_num; - _dma_channel_info* tx_chan[20]; - _dma_channel_info* rx_chan[20]; - /*functions, optional*/ - u8* (*buffer_alloc)(int len,int* offset, void** opt); - void (*buffer_free)(u8* dataptr, void* opt); - int (*intr_handler)(struct dma_device_info* info, int status); - void * priv; /* used by peripheral driver only */ + int num_tx_chan; + int num_rx_chan; + int max_rx_chan_num; + int max_tx_chan_num; + _dma_channel_info* tx_chan[20]; + _dma_channel_info* rx_chan[20]; + /*functions, optional*/ + u8* (*buffer_alloc)(int len,int* offset, void** opt); + void (*buffer_free)(u8* dataptr, void* opt); + int (*intr_handler)(struct dma_device_info* info, int status); + void * priv; /* used by peripheral driver only */ }_dma_device_info; _dma_device_info* dma_device_reserve(char* dev_name); @@ -200,3 +200,4 @@ int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); #endif + diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h index 694a646..c7bd373 100644 --- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h +++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h @@ -14,7 +14,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> */ #ifndef _IFXMIPS_IRQ__ #define _IFXMIPS_IRQ__ @@ -63,8 +63,8 @@ #define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) #define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) -#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22) -#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) +#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22) +#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h index 761a31b..8a96510 100644 --- a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h +++ b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h @@ -15,11 +15,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * - * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> * */ - #ifndef _IFXMIPS_GPIO_H_ #define _IFXMIPS_GPIO_H_ diff --git a/target/linux/ifxmips/nfs/base-files/etc/preinit.arch b/target/linux/ifxmips/nfs/base-files/etc/preinit.arch index 61662bc..7ee8e3e 100755 --- a/target/linux/ifxmips/nfs/base-files/etc/preinit.arch +++ b/target/linux/ifxmips/nfs/base-files/etc/preinit.arch @@ -1,3 +1,5 @@ -echo "- init nfs -" -exec /sbin/init +grep "/dev/root" /proc/mounts |grep -q nfs && { + echo "- init nfs -" + exec /sbin/init +} diff --git a/target/linux/ifxmips/nfs/config-2.6.27 b/target/linux/ifxmips/nfs/config-2.6.27 new file mode 100644 index 0000000..137af82 --- /dev/null +++ b/target/linux/ifxmips/nfs/config-2.6.27 @@ -0,0 +1,16 @@ +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MD5=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_LOCKD=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y diff --git a/target/linux/ifxmips/patches-2.6.27/000-mips-bad-intctl.patch b/target/linux/ifxmips/patches-2.6.27/000-mips-bad-intctl.patch new file mode 100644 index 0000000..36f0552 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/000-mips-bad-intctl.patch @@ -0,0 +1,34 @@ +--- a/arch/mips/kernel/traps.c ++++ b/arch/mips/kernel/traps.c +@@ -1484,7 +1484,16 @@ void __cpuinit per_cpu_trap_init(void) + */ + if (cpu_has_mips_r2) { + cp0_compare_irq = (read_c0_intctl() >> 29) & 7; ++ if (!cp0_compare_irq) ++ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; ++ + cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; ++ if (!cp0_perfcount_irq) ++ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; ++ ++ if (arch_fixup_c0_irqs) ++ arch_fixup_c0_irqs(); ++ + if (cp0_perfcount_irq == cp0_compare_irq) + cp0_perfcount_irq = -1; + } else { +--- a/include/asm-mips/irq.h ++++ b/include/asm-mips/irq.h +@@ -156,8 +156,12 @@ extern void free_irqno(unsigned int irq) + * IE7. Since R2 their number has to be read from the c0_intctl register. + */ + #define CP0_LEGACY_COMPARE_IRQ 7 ++#define CP0_LEGACY_PERFCNT_IRQ 7 + + extern int cp0_compare_irq; + extern int cp0_perfcount_irq; + ++extern void __weak arch_fixup_c0_irqs(void); ++ ++ + #endif /* _ASM_IRQ_H */ diff --git a/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000..ac44c30 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -21,6 +21,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } diff --git a/target/linux/ifxmips/patches-2.6.27/100-board.patch b/target/linux/ifxmips/patches-2.6.27/100-board.patch new file mode 100644 index 0000000..b45c1c4 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/100-board.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -78,6 +78,23 @@ config MIPS_COBALT + select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + ++config IFXMIPS ++ bool "Infineon Twinpass, Danube, Amazon-SE" ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select CEVT_R4K ++ select CSRC_R4K ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select HAVE_STD_PC_SERIAL_PORT ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_MULTITHREADING ++ select SYS_HAS_EARLY_PRINTK ++ select HW_HAS_PCI ++ select GENERIC_GPIO ++ select SWAP_IO_SPACE ++ + config MACH_DECSTATION + bool "DECstations" + select BOOT_ELF32 +@@ -607,6 +624,7 @@ source "arch/mips/sgi-ip27/Kconfig" + source "arch/mips/sibyte/Kconfig" + source "arch/mips/txx9/Kconfig" + source "arch/mips/vr41xx/Kconfig" ++source "arch/mips/ifxmips/Kconfig" + + endmenu + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -283,6 +283,13 @@ cflags-$(CONFIG_MIPS_COBALT) += -Iinclud + load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 + + # ++# Infineon IFXMIPS ++# ++core-$(CONFIG_IFXMIPS) += arch/mips/ifxmips/ ++cflags-$(CONFIG_IFXMIPS) += -Iinclude/asm-mips/mach-ifxmips ++load-$(CONFIG_IFXMIPS) += 0xffffffff80002000 ++ ++# + # DECstation family + # + core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/ +--- a/include/asm-mips/bootinfo.h ++++ b/include/asm-mips/bootinfo.h +@@ -57,6 +57,12 @@ + #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ + #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ + ++/* ++ * Valid machtype for group IFXMIPS ++ */ ++#define MACH_GROUP_IFXMIPS 29 ++#define MACH_INFINEON_IFXMIPS 0 ++ + #define CL_SIZE COMMAND_LINE_SIZE + + extern char *system_type; +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -51,3 +51,4 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc + obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o + obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o + obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o ++obj-$(CONFIG_IFXMIPS) += pci-ifxmips.o ops-ifxmips.o diff --git a/target/linux/ifxmips/patches-2.6.27/110-drivers.patch b/target/linux/ifxmips/patches-2.6.27/110-drivers.patch new file mode 100644 index 0000000..9382c8b --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/110-drivers.patch @@ -0,0 +1,152 @@ +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -112,6 +112,10 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o + obj-$(CONFIG_JS_RTC) += js-rtc.o + js-rtc-y = rtc.o + ++obj-$(CONFIG_IFXMIPS_SSC) += ifxmips_ssc.o ++obj-$(CONFIG_IFXMIPS_EEPROM) += ifxmips_eeprom.o ++obj-$(CONFIG_IFXMIPS_MEI) += ifxmips_mei_core.o ++ + # Files generated that shall be removed upon make clean + clean-files := consolemap_deftbl.c defkeymap.c + +--- a/drivers/mtd/maps/Makefile ++++ b/drivers/mtd/maps/Makefile +@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_WALNUT) += walnu + obj-$(CONFIG_MTD_H720X) += h720x-flash.o + obj-$(CONFIG_MTD_SBC8240) += sbc8240.o + obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o ++obj-$(CONFIG_MTD_IFXMIPS) += ifxmips.o + obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o + obj-$(CONFIG_MTD_IXP2000) += ixp2000.o + obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -343,6 +343,12 @@ config MACB + + source "drivers/net/arm/Kconfig" + ++config IFXMIPS_MII0 ++ tristate "Infineon IFXMips eth0 driver" ++ depends on IFXMIPS ++ help ++ Support for the MII0 inside the IFXMips SOC ++ + config AX88796 + tristate "ASIX AX88796 NE2000 clone support" + depends on ARM || MIPS || SUPERH +--- a/drivers/serial/Kconfig ++++ b/drivers/serial/Kconfig +@@ -1353,6 +1353,14 @@ config SERIAL_OF_PLATFORM + Currently, only 8250 compatible ports are supported, but + others can easily be added. + ++config SERIAL_IFXMIPS ++ bool "IFXMips serial driver" ++ depends on IFXMIPS ++ select SERIAL_CORE ++ select SERIAL_CORE_CONSOLE ++ help ++ Driver for the ifxmipss built in ASC hardware ++ + config SERIAL_QE + tristate "Freescale QUICC Engine serial port support" + depends on QUICC_ENGINE +--- a/drivers/serial/Makefile ++++ b/drivers/serial/Makefile +@@ -69,3 +69,4 @@ obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_s + obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o + obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o + obj-$(CONFIG_SERIAL_QE) += ucc_uart.o ++obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -102,6 +102,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o ++obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o + + # PARISC Architecture + +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -256,4 +256,4 @@ obj-$(CONFIG_NETXEN_NIC) += netxen/ + obj-$(CONFIG_NIU) += niu.o + obj-$(CONFIG_VIRTIO_NET) += virtio_net.o + obj-$(CONFIG_SFC) += sfc/ +- ++obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -9,6 +9,9 @@ menuconfig CRYPTO_HW + If you say N, all options in this submenu will be skipped and disabled. + + if CRYPTO_HW ++config CRYPTO_DEV_IFXMIPS ++ tristate "Support for IFXMIPS Data Encryption Unit" ++ depends on IFXMIPS + + config CRYPTO_DEV_PADLOCK + tristate "Support for VIA PadLock ACE" +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -4,3 +4,4 @@ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode- + obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o + obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o + obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o ++obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxdeu-aes.o ifxdeu-des.o ifxdeu-dma.o ifxdeu-generic.o ifxdeu-md5.o ifxdeu-sha1.o +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -305,3 +305,10 @@ config SUPERH_ON_CHIP_R8A66597 + help + This driver enables support for the on-chip R8A66597 in the + SH7366 and SH7723 processors. ++ ++config USB_DWC_HCD ++ tristate "IFXMIPS USB Host Controller Driver" ++ depends on USB && IFXMIPS ++ default y ++ help ++ Danube USB Host Controller +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -169,6 +169,12 @@ config LEDS_PCA955X + LED driver chips accessed via the I2C bus. Supported + devices include PCA9550, PCA9551, PCA9552, and PCA9553. + ++config LEDS_IFXMIPS ++ tristate "LED Support for IFXMIPS LEDs" ++ depends on LEDS_CLASS && IFXMIPS ++ help ++ This option enables support for the CM-X270 LEDs. ++ + comment "LED Triggers" + + config LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-c + obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o + obj-$(CONFIG_LEDS_FSG) += leds-fsg.o + obj-$(CONFIG_LEDS_PCA955X) += leds-pca955x.o ++obj-$(CONFIG_LEDS_IFXMIPS) += leds-ifxmips.o + + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -704,6 +704,12 @@ config TXX9_WDT + help + Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. + ++config IFXMIPS_WDT ++ bool "IFXMips watchdog" ++ depends on IFXMIPS ++ help ++ Hardware driver for the IFXMIPS Watchdog Timer. ++ + # PARISC Architecture + + # POWERPC Architecture diff --git a/target/linux/ifxmips/patches-2.6.27/160-cfi-swap.patch b/target/linux/ifxmips/patches-2.6.27/160-cfi-swap.patch new file mode 100644 index 0000000..9010c4b --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/160-cfi-swap.patch @@ -0,0 +1,13 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1025,7 +1025,9 @@ static int __xipram do_write_oneword(str + int retry_cnt = 0; + + adr += chip->start; +- ++#ifdef CONFIG_IFXMIPS ++ adr ^= 2; ++#endif + spin_lock(chip->mutex); + ret = get_chip(map, chip, adr, FL_WRITING); + if (ret) { diff --git a/target/linux/ifxmips/patches-2.6.27/170-dma_hack.patch b/target/linux/ifxmips/patches-2.6.27/170-dma_hack.patch new file mode 100644 index 0000000..5416b6a --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/170-dma_hack.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -51,6 +51,8 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT */ + diff --git a/target/linux/ifxmips/patches-2.6.27/200-genirq_fix.patch b/target/linux/ifxmips/patches-2.6.27/200-genirq_fix.patch new file mode 100644 index 0000000..ba63723 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/200-genirq_fix.patch @@ -0,0 +1,12 @@ +--- a/kernel/irq/chip.c ++++ b/kernel/irq/chip.c +@@ -526,6 +526,9 @@ handle_percpu_irq(unsigned int irq, stru + + kstat_this_cpu.irqs[irq]++; + ++ if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) ++ return; ++ + if (desc->chip->ack) + desc->chip->ack(irq); + diff --git a/target/linux/ifxmips/patches/000-mips-bad-intctl.patch b/target/linux/ifxmips/patches/000-mips-bad-intctl.patch new file mode 100644 index 0000000..3b1c2dc --- /dev/null +++ b/target/linux/ifxmips/patches/000-mips-bad-intctl.patch @@ -0,0 +1,34 @@ +--- a/arch/mips/kernel/traps.c ++++ b/arch/mips/kernel/traps.c +@@ -1464,7 +1464,16 @@ void __cpuinit per_cpu_trap_init(void) + */ + if (cpu_has_mips_r2) { + cp0_compare_irq = (read_c0_intctl() >> 29) & 7; ++ if (!cp0_compare_irq) ++ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; ++ + cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; ++ if (!cp0_perfcount_irq) ++ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; ++ ++ if (arch_fixup_c0_irqs) ++ arch_fixup_c0_irqs(); ++ + if (cp0_perfcount_irq == cp0_compare_irq) + cp0_perfcount_irq = -1; + } else { +--- a/include/asm-mips/irq.h ++++ b/include/asm-mips/irq.h +@@ -156,8 +156,12 @@ extern void free_irqno(unsigned int irq) + * IE7. Since R2 their number has to be read from the c0_intctl register. + */ + #define CP0_LEGACY_COMPARE_IRQ 7 ++#define CP0_LEGACY_PERFCNT_IRQ 7 + + extern int cp0_compare_irq; + extern int cp0_perfcount_irq; + ++extern void __weak arch_fixup_c0_irqs(void); ++ ++ + #endif /* _ASM_IRQ_H */ diff --git a/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000..61d9610 --- /dev/null +++ b/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch @@ -0,0 +1,65 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -13,6 +13,22 @@ + #include <asm/smtc_ipi.h> + #include <asm/time.h> + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -28,6 +44,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + #ifdef CONFIG_MIPS_MT_SMTC + evpe(vpflags); +@@ -187,7 +204,7 @@ static int c0_compare_int_usable(void) + */ + if (c0_compare_int_pending()) { + write_c0_compare(read_c0_count()); +- irq_disable_hazard(); ++ compare_change_hazard(); + if (c0_compare_int_pending()) + return 0; + } +@@ -196,7 +213,7 @@ static int c0_compare_int_usable(void) + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); +- irq_disable_hazard(); ++ compare_change_hazard(); + if ((int)(read_c0_count() - cnt) < 0) + break; + /* increase delta if the timer was already expired */ +@@ -205,11 +222,12 @@ static int c0_compare_int_usable(void) + while ((int)(read_c0_count() - cnt) <= 0) + ; /* Wait for expiry */ + ++ compare_change_hazard(); + if (!c0_compare_int_pending()) + return 0; + + write_c0_compare(read_c0_count()); +- irq_disable_hazard(); ++ compare_change_hazard(); + if (c0_compare_int_pending()) + return 0; + diff --git a/target/linux/ifxmips/patches/100-board.patch b/target/linux/ifxmips/patches/100-board.patch index e33a470..052a08a 100644 --- a/target/linux/ifxmips/patches/100-board.patch +++ b/target/linux/ifxmips/patches/100-board.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -78,6 +78,21 @@ config MIPS_COBALT +@@ -78,6 +78,23 @@ config MIPS_COBALT select SYS_SUPPORTS_LITTLE_ENDIAN select GENERIC_HARDIRQS_NO__DO_IRQ @@ -11,9 +11,11 @@ + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 + select HAVE_STD_PC_SERIAL_PORT + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_MULTITHREADING + select SYS_HAS_EARLY_PRINTK + select HW_HAS_PCI + select GENERIC_GPIO @@ -22,7 +24,7 @@ config MACH_DECSTATION bool "DECstations" select BOOT_ELF32 -@@ -697,6 +712,7 @@ source "arch/mips/sibyte/Kconfig" +@@ -697,6 +714,7 @@ source "arch/mips/sibyte/Kconfig" source "arch/mips/tx4927/Kconfig" source "arch/mips/tx4938/Kconfig" source "arch/mips/vr41xx/Kconfig" @@ -61,16 +63,6 @@ #define CL_SIZE COMMAND_LINE_SIZE extern char *system_type; ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -1464,6 +1464,7 @@ void __cpuinit per_cpu_trap_init(void) - */ - if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup- diff --git a/target/linux/ifxmips/series b/target/linux/ifxmips/series deleted file mode 100644 index 19bcf21..0000000 --- a/target/linux/ifxmips/series +++ /dev/null @@ -1,88 +0,0 @@ -Makefile -base-files/etc/config/network -config-2.6.23 -files/arch/mips/danube/Kconfig -files/arch/mips/danube/Makefile -files/arch/mips/danube/built-in.o -files/arch/mips/danube/dma-core.c -files/arch/mips/danube/dma-core.h -files/arch/mips/danube/dma-core.o -files/arch/mips/danube/interrupt.c -files/arch/mips/danube/interrupt.o -files/arch/mips/danube/kgdb_serial.c -files/arch/mips/danube/pci.c -files/arch/mips/danube/prom.c -files/arch/mips/danube/prom.o -files/arch/mips/danube/reset.c -files/arch/mips/danube/reset.o -files/arch/mips/danube/setup.c -files/arch/mips/danube/setup.o -files/drivers/mtd/maps/danube.c -files/drivers/serial/danube_asc.c -files/drivers/serial/danube_asc.c~ -files/drivers/serial/danube_asc.o -files/include/asm-mips/danube/adm6996.h -files/include/asm-mips/danube/atm_mib.h -files/include/asm-mips/danube/danube.h -files/include/asm-mips/danube/danube_bcu.h -files/include/asm-mips/danube/danube_cgu.h -files/include/asm-mips/danube/danube_deu.h -files/include/asm-mips/danube/danube_deu_structs.h -files/include/asm-mips/danube/danube_dma.h -files/include/asm-mips/danube/danube_eth2.h -files/include/asm-mips/danube/danube_eth2_fw.h -files/include/asm-mips/danube/danube_eth2_fw_with_dplus.h -files/include/asm-mips/danube/danube_eth2_fw_with_dplus_sb.h -files/include/asm-mips/danube/danube_eth_d2.h -files/include/asm-mips/danube/danube_eth_fw_d2.h -files/include/asm-mips/danube/danube_gpio.h -files/include/asm-mips/danube/danube_gptu.h -files/include/asm-mips/danube/danube_icu.h -files/include/asm-mips/danube/danube_led.h -files/include/asm-mips/danube/danube_mei.h -files/include/asm-mips/danube/danube_mei_app.h -files/include/asm-mips/danube/danube_mei_app_ioctl.h -files/include/asm-mips/danube/danube_mei_bsp.h -files/include/asm-mips/danube/danube_mei_ioctl.h -files/include/asm-mips/danube/danube_mei_linux.h -files/include/asm-mips/danube/danube_misc.h -files/include/asm-mips/danube/danube_pmu.h -files/include/asm-mips/danube/danube_ppa_api.h -files/include/asm-mips/danube/danube_ppa_eth_fw_d2.h -files/include/asm-mips/danube/danube_ppa_eth_fw_d3.h -files/include/asm-mips/danube/danube_ppa_hook.h -files/include/asm-mips/danube/danube_ppa_ppe_d3_hal.h -files/include/asm-mips/danube/danube_ppa_ppe_hal.h -files/include/asm-mips/danube/danube_ppa_stack_al.h -files/include/asm-mips/danube/danube_ppe.h -files/include/asm-mips/danube/danube_ppe_fw.h -files/include/asm-mips/danube/danube_ppe_fw_fix_for_pci.h -files/include/asm-mips/danube/danube_rcu.h -files/include/asm-mips/danube/danube_sdio_controller.h -files/include/asm-mips/danube/danube_sdio_controller_registers.h -files/include/asm-mips/danube/danube_ssc.h -files/include/asm-mips/danube/danube_sw.h -files/include/asm-mips/danube/danube_wdt.h -files/include/asm-mips/danube/danube_ws.h -files/include/asm-mips/danube/emulation.h -files/include/asm-mips/danube/ifx_mps.h -files/include/asm-mips/danube/ifx_peripheral_definitions.h -files/include/asm-mips/danube/ifx_sd_card.h -files/include/asm-mips/danube/ifx_serial.h -files/include/asm-mips/danube/ifx_ssc.h -files/include/asm-mips/danube/ifx_ssc_defines.h -files/include/asm-mips/danube/ifx_types.h -files/include/asm-mips/danube/infineon_sdio.h -files/include/asm-mips/danube/infineon_sdio_card.h -files/include/asm-mips/danube/infineon_sdio_cmds.h -files/include/asm-mips/danube/infineon_sdio_controller.h -files/include/asm-mips/danube/irq.h -files/include/asm-mips/danube/memcopy.h -files/include/asm-mips/danube/mps.h -files/include/asm-mips/danube/port.h -files/include/asm-mips/danube/ppe.h -files/include/asm-mips/danube/serial.h -files/include/asm-mips/mach-danube/irq.h -image/Makefile -patches/100-board.patch -patches/110-drivers.patch |