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| author | John Crispin <john@openwrt.org> | 2014-11-14 16:52:30 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2014-11-14 16:52:30 +0000 |
| commit | 062828aee0c343ae13009b2108659c6c742eedff (patch) | |
| tree | c60321e6be9b79aa2625f44a87a62fffa1ff3b05 | |
| parent | 938e1e03fb3853e330dfc712c72ec326ca5790db (diff) | |
| download | mtk-20170518-062828aee0c343ae13009b2108659c6c742eedff.zip mtk-20170518-062828aee0c343ae13009b2108659c6c742eedff.tar.gz mtk-20170518-062828aee0c343ae13009b2108659c6c742eedff.tar.bz2 | |
ralink: mt7621 has a different base addr for PVID
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 43243
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c index 2f3018d..1a40aff 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c @@ -27,6 +27,7 @@ #define MT7620A_CDMA_CSG_CFG 0x400 #define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30) +#define MT7621_DMA_VID 0xa8 #define MT7620A_DMA_2B_OFFSET BIT(31) #define MT7620A_RESET_FE BIT(21) #define MT7621_RESET_FE BIT(6) @@ -76,6 +77,23 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = { [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL, }; +static const u32 mt7621_reg_table[FE_REG_COUNT] = { + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, + [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID, + [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT, + [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL, +}; + static void mt7620_fe_reset(void) { u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); @@ -213,7 +231,7 @@ static struct fe_soc_data mt7621_data = { .rx_dma = mt7620_rx_dma, .switch_init = mt7620_gsw_probe, .switch_config = mt7621_gsw_config, - .reg_table = mt7620_reg_table, + .reg_table = mt7621_reg_table, .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET, .rx_dly_int = RT5350_RX_DLY_INT, .tx_dly_int = RT5350_TX_DLY_INT, |