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| author | Gabor Juhos <juhosg@openwrt.org> | 2009-02-25 16:48:56 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2009-02-25 16:48:56 +0000 |
| commit | 8e0e4cb3d8c6a06815404d25625488d2bc019d96 (patch) | |
| tree | 08f45287fbe292fe1be3d18c9eed349430bb01e9 | |
| parent | 0e8a23d053a4cf9f5d452e9decf2bf1dbf891dc2 (diff) | |
| download | mtk-20170518-8e0e4cb3d8c6a06815404d25625488d2bc019d96.zip mtk-20170518-8e0e4cb3d8c6a06815404d25625488d2bc019d96.tar.gz mtk-20170518-8e0e4cb3d8c6a06815404d25625488d2bc019d96.tar.bz2 | |
mzk-w04nu: enable the ar8216 chip workaround, and add a default network configuration file
SVN-Revision: 14656
| -rw-r--r-- | target/linux/ar71xx/base-files/etc/config/defaults/mzk-w04nu/network | 16 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/target/linux/ar71xx/base-files/etc/config/defaults/mzk-w04nu/network b/target/linux/ar71xx/base-files/etc/config/defaults/mzk-w04nu/network new file mode 100644 index 0000000..2d4d8e0 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/config/defaults/mzk-w04nu/network @@ -0,0 +1,16 @@ +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option ifname eth0 + option type bridge + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + +config interface wan + option ifname eth1 + option proto dhcp diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c index acce733..3a14902 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c @@ -148,6 +148,7 @@ static void __init mzk_w04nu_setup(void) ar71xx_eth0_data.phy_mask = 0xf; ar71xx_eth0_data.speed = SPEED_100; ar71xx_eth0_data.duplex = DUPLEX_FULL; + ar71xx_eth0_data.has_ar8216 = 1; ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ar71xx_eth1_data.phy_mask = 0x10; |