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authorImre Kaloz <kaloz@openwrt.org>2011-06-01 07:24:41 +0000
committerImre Kaloz <kaloz@openwrt.org>2011-06-01 07:24:41 +0000
commit24401759784b8aa4b35f99a9e5fc17225efb8565 (patch)
treeb7fef8689031dbd5005840badcc99075460d06d2
parentaafa838d77e6dad83b09737680018ef1feb4cbf8 (diff)
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refresh patches
SVN-Revision: 27078
-rw-r--r--target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch2
-rw-r--r--target/linux/cns3xxx/patches/100-laguna_support.patch4
2 files changed, 3 insertions, 3 deletions
diff --git a/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch b/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
index 0c6c525..e7180b0 100644
--- a/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
+++ b/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
@@ -1,6 +1,6 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -378,8 +378,6 @@ static int __init cns3xxx_pcie_init(void
+@@ -375,8 +375,6 @@ static int __init cns3xxx_pcie_init(void
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
iotable_init(cns3xxx_pcie[i].cfg_bases,
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
diff --git a/target/linux/cns3xxx/patches/100-laguna_support.patch b/target/linux/cns3xxx/patches/100-laguna_support.patch
index 32becc3..574b8b3 100644
--- a/target/linux/cns3xxx/patches/100-laguna_support.patch
+++ b/target/linux/cns3xxx/patches/100-laguna_support.patch
@@ -874,8 +874,8 @@
+
iotable_init(cns3xxx_pcie[i].cfg_bases,
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
-@@ -386,4 +389,3 @@ static int __init cns3xxx_pcie_init(void
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+@@ -384,4 +387,3 @@ static int __init cns3xxx_pcie_init(void
return 0;
}