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authorYutang Jiang <yutang.jiang@nxp.com>2016-10-29 00:18:23 +0800
committerJohn Crispin <john@phrozen.org>2016-10-31 17:00:10 +0100
commit15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch)
treebd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch
parentc6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff)
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layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch')
-rw-r--r--package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch33
1 files changed, 33 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch b/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch
new file mode 100644
index 0000000..76fb0b0
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch
@@ -0,0 +1,33 @@
+From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Mon, 13 Jun 2016 17:29:59 +0530
+Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
+
+DDR timigs displayed for LS1012A were half of true value.
+Updated DDR value to 1000 MT/s.
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+index 63e5bed..a4dde5b 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+@@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
+- if (ver == SVR_LS1012)
++ if (ver == SVR_LS1012){
+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+-
++ sys_info->freq_ddrbus *=2;
++ }
+ #define HWA_CGA_M1_CLK_SEL 0xe0000000
+ #define HWA_CGA_M1_CLK_SHIFT 29
+ #ifdef CONFIG_SYS_DPAA_FMAN
+--
+1.7.9.5
+