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| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
| tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch | |
| parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
| download | mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 | |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch b/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch new file mode 100644 index 0000000..a99b846 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch @@ -0,0 +1,28 @@ +From 3c41e8827ddcff313a518de19d630a42bbdca3b1 Mon Sep 17 00:00:00 2001 +From: Anji J <anji.jagarlmudi@freescale.com> +Date: Fri, 8 Jul 2016 20:05:37 +0530 +Subject: [PATCH 73/93] armv8:pfe Change MDIO HOLDTIME value to 5 + +Per design/validation team suggestion use HOLDTIME value as 5. + +Signed-off-by: Anji J <anji.jagarlmudi@freescale.com> +--- + drivers/net/pfe_eth/pfe_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c +index 528ede9..9a90b38 100644 +--- a/drivers/net/pfe_eth/pfe_eth.c ++++ b/drivers/net/pfe_eth/pfe_eth.c +@@ -329,7 +329,7 @@ struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info) + + /*configure mdio speed */ + mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT); +- mdio_speed |= EMAC_HOLDTIME(0x4); ++ mdio_speed |= EMAC_HOLDTIME(0x5); + writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG); + + ret = mdio_register(bus); +-- +1.7.9.5 + |