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authorJohn Crispin <john@openwrt.org>2012-10-16 13:44:25 +0000
committerJohn Crispin <john@openwrt.org>2012-10-16 13:44:25 +0000
commite75106aa0d82a64122954b5990b50ec80d8e4040 (patch)
treebcc8ab60e849b3a0debb601b13c7f5356d9683e8 /package/boot/uboot-xburst/files/include/configs/avt2.h
parent254d851d8a9434e9c8a12a6ec96538ba13101600 (diff)
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move boot related packages to their own folder
SVN-Revision: 33781
Diffstat (limited to 'package/boot/uboot-xburst/files/include/configs/avt2.h')
-rw-r--r--package/boot/uboot-xburst/files/include/configs/avt2.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/package/boot/uboot-xburst/files/include/configs/avt2.h b/package/boot/uboot-xburst/files/include/configs/avt2.h
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+++ b/package/boot/uboot-xburst/files/include/configs/avt2.h
@@ -0,0 +1,26 @@
+#ifndef __CONFIG_AVT2_H
+#define __CONFIG_AVT2_H
+
+#include <configs/nanonote.h>
+
+#define CONFIG_AVT2 1
+
+#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1"
+#define CONFIG_BOOTARGSFROMSD "mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1"
+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
+
+/* SDRAM paramters */
+#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
+#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
+#define SDRAM_ROW 13 /* Row address: 11 to 13 */
+#define SDRAM_COL 10 /* Column address: 8 to 12 */
+#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
+
+/* SDRAM Timings, unit: ns */
+#define SDRAM_TRAS 45 /* RAS# Active Time */
+#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
+#define SDRAM_TPC 20 /* RAS# Precharge Time */
+#define SDRAM_TRWL 7 /* Write Latency Time */
+#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
+
+#endif /* __CONFIG_AVT_H */