* rename voice package * sync with lantiqs release * make it work on lantiq kernel

SVN-Revision: 25275

1 files changed, 559 insertions, 0 deletions

diff --git a/package/ltq-vmmc/patches/100-ifxmips.patch b/package/ltq-vmmc/patches/100-ifxmips.patch
new file mode 100644
index 0000000..9a237d9
--- /dev/null
+++ b/package/ltq-vmmc/patches/100-ifxmips.patch
@@ -0,0 +1,559 @@
+--- a/src/drv_vmmc_access.h
++++ b/src/drv_vmmc_access.h
+@@ -24,6 +24,10 @@
+ #include "drv_mps_vmmc.h"
+ #endif
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS IFXMIPS_MPS_BASE_ADDR
++#endif
++
+ /* ============================= */
+ /* Global Defines                */
+ /* ============================= */
+--- a/src/drv_vmmc_bbd.c
++++ b/src/drv_vmmc_bbd.c
+@@ -1072,7 +1072,11 @@
+    IFX_uint8_t  padBytes = 0;
+ #endif
+    IFX_uint16_t cram_offset, cram_crc,
+-                pCmd [MAX_CMD_WORD]  = {0};
++                pCmd [MAX_CMD_WORD]
++#if defined (__GNUC__) || defined (__GNUG__)
++                   __attribute__ ((aligned(4)))
++#endif
++                   = {0};
+ 
+    /* read offset */
+    cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
+--- a/src/drv_vmmc_danube.h
++++ b/src/drv_vmmc_danube.h
+@@ -15,56 +15,18 @@
+ */
+ 
+ #if defined SYSTEM_DANUBE
+-#include <asm/ifx/ifx_gpio.h>
++#include <xway/xway.h>
++
+ #else
+ #error no system selected
+ #endif
+ 
+-#define VMMC_TAPI_GPIO_MODULE_ID                        IFX_GPIO_MODULE_TAPI_VMMC
++#define VMMC_TAPI_GPIO_MODULE_ID             IFX_GPIO_MODULE_TAPI_VMMC
+ /**
+ 
+ */
+ #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
+ do { \
+-   ret = VMMC_statusOk; \
+-   /* Reserve P0.0 as TDM/FSC */ \
+-   if (!GPIOreserved) \
+-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
+-   \
+-   /* Reserve P1.9 as TDM/DO */ \
+-   if (!GPIOreserved) \
+-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   \
+-   /* Reserve P1.10 as TDM/DI */ \
+-   if (!GPIOreserved) \
+-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
+-   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
+-   \
+-   /* Reserve P1.11 as TDM/DCL */ \
+-   if (!GPIOreserved) \
+-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   \
+-   if (mode == 2) { \
+-      /* TDM/FSC+DCL Master */ \
+-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   } else { \
+-      /* TDM/FSC+DCL Slave */ \
+-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+-   } \
+ } while(0);
+ 
+ /**
+@@ -72,11 +34,6 @@
+ */
+ #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
+ do { \
+-   ret = VMMC_statusOk; \
+-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
+-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
+ } while (0)
+ 
+ #endif /* _DRV_VMMC_AMAZON_S_H */
+--- a/src/drv_vmmc_init.c
++++ b/src/drv_vmmc_init.c
+@@ -52,6 +52,14 @@
+ #include "ifx_pmu.h"
+ #endif /* PMU_SUPPORTED */
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
++#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
++#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
++#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
++#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
++#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
++#endif
+ 
+ /* ============================= */
+ /* Local Macros & Definitions    */
+--- a/src/drv_vmmc_init_cap.c
++++ b/src/drv_vmmc_init_cap.c
+@@ -22,6 +22,11 @@
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_device.h"
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  define IFX_MPS_CHIPID_VERSION_GET   IFXMIPS_MPS_CHIPID_VERSION_GET
++#  define IFX_MPS_CHIPID               IFXMIPS_MPS_CHIPID
++#endif
++
+ /* ============================= */
+ /* Configuration defintions      */
+ /* ============================= */
+--- a/src/mps/drv_mps_vmmc_common.c
++++ b/src/mps/drv_mps_vmmc_common.c
+@@ -17,6 +17,7 @@
+ /* Includes                      */
+ /* ============================= */
+ #include "drv_config.h"
++#include "drv_vmmc_init.h"
+ 
+ #undef USE_PLAIN_VOICE_FIRMWARE
+ #undef PRINT_ON_ERR_INTERRUPT
+@@ -35,8 +36,35 @@
+ #include "ifxos_interrupt.h"
+ #include "ifxos_time.h"
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/ifx_gptu.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <lantiq.h>
++#  include <irq.h>
++#  include <lantiq_timer.h>
++
++#  define ifx_gptu_timer_request    lq_request_timer
++#  define ifx_gptu_timer_start      lq_start_timer
++#  define ifx_gptu_countvalue_get   lq_get_count_value
++#  define ifx_gptu_timer_free       lq_free_timer
++
++#  define IFX_MPS_SRAM              IFXMIPS_MPS_SRAM
++#  define IFX_MPS_AD0ENR            IFXMIPS_MPS_AD0ENR
++#  define IFX_MPS_AD1ENR            IFXMIPS_MPS_AD1ENR
++#  define IFX_MPS_VC0ENR            IFXMIPS_MPS_VC0ENR
++#  define IFX_MPS_SAD0SR            IFXMIPS_MPS_SAD0SR
++#  define IFX_MPS_RAD0SR            IFXMIPS_MPS_RAD0SR
++#  define IFX_MPS_RAD1SR            IFXMIPS_MPS_RAD1SR
++#  define IFX_MPS_CAD0SR            IFXMIPS_MPS_CAD0SR
++#  define IFX_MPS_CAD1SR            IFXMIPS_MPS_CAD1SR
++#  define IFX_MPS_RVC0SR            IFXMIPS_MPS_RVC0SR
++#  define IFX_MPS_CVC0SR            IFXMIPS_MPS_CVC0SR
++
++#  define INT_NUM_IM4_IRL14         (INT_NUM_IM4_IRL0 + 14)
++
++#  define bsp_mask_and_ack_irq      lq_mask_and_ack_irq
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx/ifx_gptu.h>
++#endif
+ 
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_dbg.h"
+@@ -201,7 +229,8 @@
+  */
+ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
+ {
+-   IFX_uint32_t ptr, flags;
++   unsigned long flags;
++   IFX_uint32_t ptr;
+    IFX_int32_t index = fastbuf_index;
+ 
+    if (fastbuf_initialized == 0)
+@@ -255,7 +284,7 @@
+  */
+ IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t index = fastbuf_index;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -451,7 +480,7 @@
+  */
+ static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
+    {
+@@ -478,7 +507,7 @@
+  */
+ static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    if (mps_buffer.buf_level < value)
+    {
+@@ -946,7 +975,7 @@
+                                  mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
+                                  IFX_boolean_t from_kernel)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+ 
+@@ -1062,7 +1091,7 @@
+ IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
+ {
+    IFX_int32_t count;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+    IFXOS_BlockFree (pFW_img_data);
+@@ -1558,7 +1587,7 @@
+                                       IFX_uint32_t * bytes)
+ {
+    IFX_int32_t i, ret;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+ 
+@@ -1768,7 +1797,7 @@
+ {
+    mps_fifo *mbx;
+    IFX_uint32_t i;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t retval = -EAGAIN;
+    IFX_int32_t retries = 0;
+    IFX_uint32_t word = 0;
+@@ -2163,6 +2192,7 @@
+       TRACE (MPS, DBG_LEVEL_HIGH,
+              ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
+    }
++
+    return retval;
+ }
+ 
+@@ -2186,7 +2216,7 @@
+    mps_mbx_dev *mbx_dev;
+    MbxMsg_s msg;
+    IFX_uint32_t bytes_read = 0;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    IFX_int32_t ret;
+ 
+    /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
+@@ -2277,7 +2307,7 @@
+          {
+             ifx_mps_bufman_dec_level (1);
+             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
+-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
++                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
+             {
+                IFXOS_LockRelease (pMPSDev->provide_buffer);
+             }
+@@ -2320,7 +2350,7 @@
+ #endif /* CONFIG_PROC_FS */
+             ifx_mps_bufman_dec_level (1);
+             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
+-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
++                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
+             {
+                IFXOS_LockRelease (pMPSDev->provide_buffer);
+             }
+@@ -2350,7 +2380,7 @@
+ IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
+ {
+    mps_fifo *mbx;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    /* set pointer to upstream command mailbox */
+    mbx = &(pMPSDev->cmd_upstrm_fifo);
+@@ -2398,7 +2428,7 @@
+    mps_event_msg msg;
+    IFX_int32_t length = 0;
+    IFX_int32_t read_length = 0;
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    /* set pointer to upstream event mailbox */
+    mbx = &(pMPSDev->event_upstrm_fifo);
+@@ -2641,7 +2671,7 @@
+ */
+ IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    MPS_Ad0Reg_u Ad0Reg;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -2667,7 +2697,7 @@
+ */
+ IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+    MPS_Ad0Reg_u Ad0Reg;
+ 
+    IFXOS_LOCKINT (flags);
+@@ -2794,6 +2824,7 @@
+       }
+    }
+ 
++
+    if (MPS_Ad0StatusReg.fld.du_mbx)
+    {
+ #ifdef CONFIG_PROC_FS
+@@ -3087,7 +3118,8 @@
+  */
+ IFX_return_t ifx_mps_init_gpt ()
+ {
+-   IFX_uint32_t flags, timer_flags, timer, loops = 0;
++   unsigned long flags;
++   IFX_uint32_t timer_flags, timer, loops = 0;
+    IFX_ulong_t count;
+ #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
+    timer = TIMER1A;
+--- a/src/mps/drv_mps_vmmc_danube.c
++++ b/src/mps/drv_mps_vmmc_danube.c
+@@ -32,9 +32,21 @@
+ #include "ifxos_select.h"
+ #include "ifxos_interrupt.h"
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/ifx_gpio.h>
+-#include <asm/ifx/common_routines.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <lantiq.h>
++#  include <irq.h>
++#  include <lantiq_timer.h>
++#  include <linux/dma-mapping.h>
++
++
++# define LQ_RCU_RST		((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
++#define IFX_RCU_RST_REQ_CPU1             (1 << 3)
++#  define IFX_RCU_RST_REQ        LQ_RCU_RST
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#  include <asm/ifx/ifx_gpio.h>
++#endif
+ 
+ #include "drv_mps_vmmc.h"
+ #include "drv_mps_vmmc_dbg.h"
+@@ -71,6 +83,20 @@
+ /* Local function definition     */
+ /* ============================= */
+ 
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
++{
++	return 2;
++}
++
++unsigned int *lq_get_cp1_base(void);
++
++IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
++{
++	return lq_get_cp1_base();
++}
++#endif
++
+ /******************************************************************************
+  * DANUBE Specific Routines
+  ******************************************************************************/
+@@ -130,6 +156,15 @@
+    }
+ 
+    /* check if FW image fits in available memory space */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++   if (mem > ifx_get_cp1_size()<<20)
++   {
++      TRACE (MPS, DBG_LEVEL_HIGH,
++      ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
++                 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
++      return IFX_ERROR;
++   }
++#else
+    if (mem > ifx_get_cp1_size())
+    {
+       TRACE (MPS, DBG_LEVEL_HIGH,
+@@ -137,6 +172,7 @@
+                  __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
+       return IFX_ERROR;
+    }
++#endif
+ 
+    /* reset the driver */
+    ifx_mps_reset ();
+@@ -357,7 +393,7 @@
+  */
+ IFX_void_t ifx_mps_wdog_expiry()
+ {
+-   IFX_uint32_t flags;
++   unsigned long flags;
+ 
+    IFXOS_LOCKINT (flags);
+    /* recalculate and compare the firmware checksum */
+--- a/src/mps/drv_mps_vmmc_device.h
++++ b/src/mps/drv_mps_vmmc_device.h
+@@ -16,8 +16,15 @@
+                  declarations.
+ *******************************************************************************/
+ 
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx_vpe.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#  include <lantiq.h>
++#  include <irq.h>
++#  include <xway/xway.h>
++#  include <gpio.h>
++#else
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#endif
+ 
+ /* ============================= */
+ /* MPS Common defines            */
+--- a/src/mps/drv_mps_vmmc_linux.c
++++ b/src/mps/drv_mps_vmmc_linux.c
+@@ -40,10 +40,28 @@
+ #include <linux/moduleparam.h>
+ #endif /* */
+ 
+-
+-#include <asm/ifx/irq.h>
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx_vpe.h>
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
++#include "drv_vmmc_init.h"
++#  include <lantiq.h>
++#  include <irq.h>
++
++#  define IFX_MPS_AD0ENR      IFXMIPS_MPS_AD0ENR
++#  define IFX_MPS_AD1ENR      IFXMIPS_MPS_AD1ENR
++#  define IFX_MPS_RAD0SR      IFXMIPS_MPS_RAD0SR
++#  define IFX_MPS_RAD1SR      IFXMIPS_MPS_RAD1SR
++#  define IFX_MPS_VC0ENR      IFXMIPS_MPS_VC0ENR
++#  define IFX_MPS_RVC0SR      IFXMIPS_MPS_RVC0SR
++
++#  define INT_NUM_IM4_IRL14   (INT_NUM_IM4_IRL0 + 14)
++#  define INT_NUM_IM4_IRL18   (INT_NUM_IM4_IRL0 + 18)
++#  define INT_NUM_IM4_IRL19   (INT_NUM_IM4_IRL0 + 19)
++#define LQ_ICU_BASE_ADDR      (KSEG1 | 0x1F880200)
++#  define IFX_ICU_IM4_IER     (LQ_ICU_BASE_ADDR + 0x00A8)
++#else
++#  include <asm/ifx/irq.h>
++#  include <asm/ifx/ifx_regs.h>
++#  include <asm/ifx_vpe.h>
++#endif
+ 
+ /* lib_ifxos headers */
+ #include "ifx_types.h"
+@@ -915,7 +933,7 @@
+ #endif /* MPS_FIFO_BLOCKING_WRITE */
+       case FIO_MPS_GET_STATUS:
+          {
+-            IFX_uint32_t flags;
++            unsigned long flags;
+ 
+             /* get the status of the channel */
+             if (!from_kernel)
+@@ -949,7 +967,7 @@
+ #if CONFIG_MPS_HISTORY_SIZE > 0
+       case FIO_MPS_GET_CMD_HISTORY:
+          {
+-            IFX_uint32_t flags;
++            unsigned long flags;
+ 
+             if (from_kernel)
+             {
+@@ -1641,6 +1659,7 @@
+          sprintf (buf + len, "   minLv: \t  %8d\n",
+                   ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
+    }
++
+    return len;
+ }
+ 
+--- a/src/drv_vmmc_init.h
++++ b/src/drv_vmmc_init.h
+@@ -53,4 +53,41 @@
+ extern IFX_int32_t   VMMC_DeviceDriverStart(IFX_void_t);
+ extern IFX_void_t    VMMC_DeviceDriverStop(IFX_void_t);
+ 
++
++#define IFXMIPS_MPS_BASE_ADDR           (KSEG1 + 0x1F107000)
++#define IFXMIPS_MPS_SRAM                ((u32 *)(KSEG1 + 0x1F200000))
++
++#define IFXMIPS_MPS_CHIPID              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
++#define IFXMIPS_MPS_VC0ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
++#define IFXMIPS_MPS_VC1ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
++#define IFXMIPS_MPS_VC2ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
++#define IFXMIPS_MPS_VC3ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
++#define IFXMIPS_MPS_RVC0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
++#define IFXMIPS_MPS_RVC1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
++#define IFXMIPS_MPS_RVC2SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
++#define IFXMIPS_MPS_RVC3SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
++#define IFXMIPS_MPS_SVC0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
++#define IFXMIPS_MPS_SVC1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
++#define IFXMIPS_MPS_SVC2SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
++#define IFXMIPS_MPS_SVC3SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
++#define IFXMIPS_MPS_CVC0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
++#define IFXMIPS_MPS_CVC1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
++#define IFXMIPS_MPS_CVC2SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
++#define IFXMIPS_MPS_CVC3SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
++#define IFXMIPS_MPS_RAD0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
++#define IFXMIPS_MPS_RAD1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
++#define IFXMIPS_MPS_SAD0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
++#define IFXMIPS_MPS_SAD1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
++#define IFXMIPS_MPS_CAD0SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
++#define IFXMIPS_MPS_CAD1SR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
++#define IFXMIPS_MPS_AD0ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
++#define IFXMIPS_MPS_AD1ENR              ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
++
++#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)   (((value) >> 28) & ((1 << 4) - 1))
++#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)   ((((1 << 4) - 1) & (value)) << 28)
++#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)   (((value) >> 12) & ((1 << 16) - 1))
++#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)   ((((1 << 16) - 1) & (value)) << 12)
++#define IFXMIPS_MPS_CHIPID_MANID_GET(value)     (((value) >> 1) & ((1 << 10) - 1))
++#define IFXMIPS_MPS_CHIPID_MANID_SET(value)     ((((1 << 10) - 1) & (value)) << 1)
++
+ #endif /* _DRV_VMMC_INIT_H */
+--- a/src/drv_vmmc_ioctl.c
++++ b/src/drv_vmmc_ioctl.c
+@@ -18,6 +18,7 @@
+ /* Includes                      */
+ /* ============================= */
+ #include "drv_api.h"
++#include "drv_vmmc_init.h"
+ #include "drv_vmmc_api.h"
+ #include "drv_vmmc_bbd.h"
+