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| author | Felix Fietkau <nbd@openwrt.org> | 2012-03-10 12:59:36 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2012-03-10 12:59:36 +0000 |
| commit | 7dff84b6703a69fb6585052ee0e27cf794d3d8b5 (patch) | |
| tree | d94c676a0f89e03d761705bb03435d6eaed0438a /package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch | |
| parent | 1812fe63b223bfcc286778ceb51d0af615df4858 (diff) | |
| download | mtk-20170518-7dff84b6703a69fb6585052ee0e27cf794d3d8b5.zip mtk-20170518-7dff84b6703a69fb6585052ee0e27cf794d3d8b5.tar.gz mtk-20170518-7dff84b6703a69fb6585052ee0e27cf794d3d8b5.tar.bz2 | |
mac80211: more patch reorganization, merge an upstream performance optimization patch
SVN-Revision: 30865
Diffstat (limited to 'package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch')
| -rw-r--r-- | package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch b/package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch new file mode 100644 index 0000000..6bde765 --- /dev/null +++ b/package/mac80211/patches/542-ath9k_fix_half_quarter_sifs.patch @@ -0,0 +1,44 @@ +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -1007,31 +1007,35 @@ void ath9k_hw_init_global_settings(struc + if (IS_CHAN_HALF_RATE(chan)) { + eifs = 175; + +- if (!AR_SREV_9300_20_OR_LATER(ah)) ++ if (!AR_SREV_9300_20_OR_LATER(ah)) { + rx_lat = 10; +- else ++ sifstime = 8; ++ } else { + rx_lat *= 2; ++ sifstime = 32; ++ } + + tx_lat *= 2; + if (IS_CHAN_A_FAST_CLOCK(ah, chan)) + tx_lat += 11; + + slottime = 13; +- sifstime = 32; + } else if (IS_CHAN_QUARTER_RATE(chan)) { + eifs = 340; + +- if (!AR_SREV_9300_20_OR_LATER(ah)) ++ if (!AR_SREV_9300_20_OR_LATER(ah)) { + rx_lat = 20; +- else ++ sifstime = 8; ++ } else { + rx_lat = (rx_lat * 4) - 1; ++ sifstime = 64; ++ } + + tx_lat *= 4; + if (IS_CHAN_A_FAST_CLOCK(ah, chan)) + tx_lat += 22; + + slottime = 21; +- sifstime = 64; + } else { + if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { + eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; |