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authorFelix Fietkau <nbd@openwrt.org>2011-07-08 17:19:21 +0000
committerFelix Fietkau <nbd@openwrt.org>2011-07-08 17:19:21 +0000
commit2d0ecd63f5981cc55f0278022ce59d8e9791bcd1 (patch)
treebad7367e1041e53e957a885469f1ecc6830beb3b /package/mac80211/patches/549-ath9k_shift_reg_delay.patch
parent887b29bfbde85f52c5b2434ebaba964c1d70af17 (diff)
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ath9k: add more fixes for half/quarter rate support
SVN-Revision: 27562
Diffstat (limited to 'package/mac80211/patches/549-ath9k_shift_reg_delay.patch')
-rw-r--r--package/mac80211/patches/549-ath9k_shift_reg_delay.patch14
1 files changed, 14 insertions, 0 deletions
diff --git a/package/mac80211/patches/549-ath9k_shift_reg_delay.patch b/package/mac80211/patches/549-ath9k_shift_reg_delay.patch
new file mode 100644
index 0000000..3676ae4
--- /dev/null
+++ b/package/mac80211/patches/549-ath9k_shift_reg_delay.patch
@@ -0,0 +1,14 @@
+--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+@@ -131,8 +131,9 @@ static int ar9002_hw_set_channel(struct
+ channelSel = CHANSEL_5G(freq);
+
+ /* RefDivA setting */
+- REG_RMW_FIELD(ah, AR_AN_SYNTH9,
+- AR_AN_SYNTH9_REFDIVA, refDivA);
++ ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9,
++ AR_AN_SYNTH9_REFDIVA,
++ AR_AN_SYNTH9_REFDIVA_S, refDivA);
+
+ }
+