mac80211: backport ath9k uninline patch

SVN-Revision: 15490

1 files changed, 104 insertions, 0 deletions

diff --git a/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch b/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch
new file mode 100644
index 0000000..d461cb1
--- /dev/null
+++ b/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch
@@ -0,0 +1,104 @@
+From dd51972ba5d11df434faf9171fe02c0cc48d35c1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 29 Apr 2009 08:52:16 +0200
+Subject: [PATCH] ath9k: uninline ath9k_io{read,write}32 routines
+
+The spin_lock handling uses lots of instructions on some archs.
+With this patch the size of the ath9k module will be significantly
+smaller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+Example results on different platforms:
+
+xscale:     468344 -> 293022 (62.6%)
+mips32:     549847 -> 389421 (70.8%)
+mips32r2:   510520 -> 394020 (77.2%)
+ppc40x:     365153 -> 296928 (81.3%)
+
+ drivers/net/wireless/ath9k/ath9k.h |   33 +------------------------------
+ drivers/net/wireless/ath9k/hw.c    |   32 +++++++++++++++++++++++++++++++
+ 2 files changed, 34 insertions(+), 31 deletions(-)
+
+--- a/drivers/net/wireless/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath9k/ath9k.h
+@@ -721,36 +721,7 @@ void ath9k_wiphy_pause_all_forced(struct
+ bool ath9k_wiphy_scanning(struct ath_softc *sc);
+ void ath9k_wiphy_work(struct work_struct *work);
+ 
+-/*
+- * Read and write, they both share the same lock. We do this to serialize
+- * reads and writes on Atheros 802.11n PCI devices only. This is required
+- * as the FIFO on these devices can only accept sanely 2 requests. After
+- * that the device goes bananas. Serializing the reads/writes prevents this
+- * from happening.
+- */
+-
+-static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
+-{
+-	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
+-		unsigned long flags;
+-		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
+-		iowrite32(val, ah->ah_sc->mem + reg_offset);
+-		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
+-	} else
+-		iowrite32(val, ah->ah_sc->mem + reg_offset);
+-}
+-
+-static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
+-{
+-	u32 val;
+-	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
+-		unsigned long flags;
+-		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
+-		val = ioread32(ah->ah_sc->mem + reg_offset);
+-		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
+-	} else
+-		val = ioread32(ah->ah_sc->mem + reg_offset);
+-	return val;
+-}
++void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
++unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
+ 
+ #endif /* ATH9K_H */
+--- a/drivers/net/wireless/ath9k/hw.c
++++ b/drivers/net/wireless/ath9k/hw.c
+@@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct a
+ 		return ath9k_hw_mac_clks(ah, usecs);
+ }
+ 
++/*
++ * Read and write, they both share the same lock. We do this to serialize
++ * reads and writes on Atheros 802.11n PCI devices only. This is required
++ * as the FIFO on these devices can only accept sanely 2 requests. After
++ * that the device goes bananas. Serializing the reads/writes prevents this
++ * from happening.
++ */
++
++void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
++{
++	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
++		unsigned long flags;
++		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
++		iowrite32(val, ah->ah_sc->mem + reg_offset);
++		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
++	} else
++		iowrite32(val, ah->ah_sc->mem + reg_offset);
++}
++
++unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
++{
++	u32 val;
++	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
++		unsigned long flags;
++		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
++		val = ioread32(ah->ah_sc->mem + reg_offset);
++		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
++	} else
++		val = ioread32(ah->ah_sc->mem + reg_offset);
++	return val;
++}
++
+ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
+ {
+ 	int i;