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author | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 22:40:32 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 22:40:32 +0000 |
commit | 60c60c05163b1d4d44fefef49caaac9dbc9f8a8f (patch) | |
tree | c3a7fa927f23cbbbf01129aec8cc729b731849bc /package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h | |
parent | 6e5419b7acc217c83d410775ae3d71d37efdaa91 (diff) | |
download | mtk-20170518-60c60c05163b1d4d44fefef49caaac9dbc9f8a8f.zip mtk-20170518-60c60c05163b1d4d44fefef49caaac9dbc9f8a8f.tar.gz mtk-20170518-60c60c05163b1d4d44fefef49caaac9dbc9f8a8f.tar.bz2 |
add uboot-lantiq (based on a patch contributed by Lantiq)
SVN-Revision: 20561
Diffstat (limited to 'package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h')
-rw-r--r-- | package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h new file mode 100644 index 0000000..445b7da --- /dev/null +++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h @@ -0,0 +1,51 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x301 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1700 +#define MC_DC22_VALUE 0x1717 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x4e20 +#define MC_DC30_VALUE 0x8235 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 |