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author | Lars-Peter Clausen <lars@metafoo.de> | 2010-04-12 18:17:26 +0000 |
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committer | Lars-Peter Clausen <lars@metafoo.de> | 2010-04-12 18:17:26 +0000 |
commit | 393541dce8995dbe0fc3d4691b382c06e5824b14 (patch) | |
tree | 2f074389e55b47cbf3dad05b898076c171bd54c5 /package/uboot-xburst/files/include/configs/qi_lb60.h | |
parent | 0946764732b8d2059621bff372150ca074e972c4 (diff) | |
download | mtk-20170518-393541dce8995dbe0fc3d4691b382c06e5824b14.zip mtk-20170518-393541dce8995dbe0fc3d4691b382c06e5824b14.tar.gz mtk-20170518-393541dce8995dbe0fc3d4691b382c06e5824b14.tar.bz2 |
Add uboot for xburst package
SVN-Revision: 20832
Diffstat (limited to 'package/uboot-xburst/files/include/configs/qi_lb60.h')
-rw-r--r-- | package/uboot-xburst/files/include/configs/qi_lb60.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/package/uboot-xburst/files/include/configs/qi_lb60.h b/package/uboot-xburst/files/include/configs/qi_lb60.h new file mode 100644 index 0000000..1542c3d --- /dev/null +++ b/package/uboot-xburst/files/include/configs/qi_lb60.h @@ -0,0 +1,27 @@ +#ifndef __CONFIG_QI_LB60_H +#define __CONFIG_QI_LB60_H + +#include <configs/nanonote.h> + +#define CONFIG_QI_LB60 1 + +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" +#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" +#define CONFIG_BOOTCOMMANDFROMSD "mmc init; fatload mmc 0 0x80600000 uImage; bootm" + +/* SDRAM paramters */ +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ + +/* SDRAM Timings, unit: ns */ +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ + +#endif |