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| author | John Crispin <john@openwrt.org> | 2012-10-16 13:44:25 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2012-10-16 13:44:25 +0000 |
| commit | e75106aa0d82a64122954b5990b50ec80d8e4040 (patch) | |
| tree | bcc8ab60e849b3a0debb601b13c7f5356d9683e8 /package/uboot-xburst/files/include/configs/qi_lb60.h | |
| parent | 254d851d8a9434e9c8a12a6ec96538ba13101600 (diff) | |
| download | mtk-20170518-e75106aa0d82a64122954b5990b50ec80d8e4040.zip mtk-20170518-e75106aa0d82a64122954b5990b50ec80d8e4040.tar.gz mtk-20170518-e75106aa0d82a64122954b5990b50ec80d8e4040.tar.bz2 | |
move boot related packages to their own folder
SVN-Revision: 33781
Diffstat (limited to 'package/uboot-xburst/files/include/configs/qi_lb60.h')
| -rw-r--r-- | package/uboot-xburst/files/include/configs/qi_lb60.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/package/uboot-xburst/files/include/configs/qi_lb60.h b/package/uboot-xburst/files/include/configs/qi_lb60.h deleted file mode 100644 index 1542c3d..0000000 --- a/package/uboot-xburst/files/include/configs/qi_lb60.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __CONFIG_QI_LB60_H -#define __CONFIG_QI_LB60_H - -#include <configs/nanonote.h> - -#define CONFIG_QI_LB60 1 - -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" -#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait" -#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" -#define CONFIG_BOOTCOMMANDFROMSD "mmc init; fatload mmc 0 0x80600000 uImage; bootm" - -/* SDRAM paramters */ -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define SDRAM_COL 9 /* Column address: 8 to 12 */ -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ - -/* SDRAM Timings, unit: ns */ -#define SDRAM_TRAS 45 /* RAS# Active Time */ -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define SDRAM_TPC 20 /* RAS# Precharge Time */ -#define SDRAM_TRWL 7 /* Write Latency Time */ -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ - -#endif |