uboot-sunxi: bump to 2014.04

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

SVN-Revision: 42422

4 files changed, 3439 insertions, 4357 deletions

diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile
index 392c740..67c935d 100644
--- a/package/boot/uboot-sunxi/Makefile
+++ b/package/boot/uboot-sunxi/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=u-boot
-PKG_VERSION:=2014.01-rc1
+PKG_VERSION:=2014.04
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
 	http://mirror2.openwrt.org/sources \
 	ftp://ftp.denx.de/pub/u-boot
-PKG_SOURCE_VERSION:=1552fe43c3e827d56c9cd212fba3dcba
+PKG_SOURCE_VERSION:=6d2116d1385a66e9a59742caa9d62a54
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
 
 include $(INCLUDE_DIR)/package.mk
@@ -25,46 +25,46 @@ define uboot/Default
 endef
 
 define uboot/A10-OLinuXino-Lime
-  TITLE:=U-Boot 2014.01-rc1 for the A10 OLinuXino LIME
+  TITLE:=U-Boot 2014.04 for the A10 OLinuXino LIME
 endef
 
 define uboot/A13-OLinuXino
-  TITLE:=U-Boot 2014.01-rc1 for the A13 OlinuXino
+  TITLE:=U-Boot 2014.04 for the A13 OlinuXino
 endef
 
 define uboot/A20-OLinuXino_MICRO
-  TITLE:=U-Boot 2014.01-rc1 for A20 OLinuXino MICRO
+  TITLE:=U-Boot 2014.04 for A20 OLinuXino MICRO
 endef
 
-define uboot/bananapi
-  TITLE:=U-Boot 2014.01-rc1 for BananaPi
+define uboot/Bananapi
+  TITLE:=U-Boot 2014.04 for Bananapi
 endef
 
 define uboot/Cubieboard
-  TITLE:=U-Boot 2014.01-rc1 for Cubieboard
+  TITLE:=U-Boot 2014.04 for Cubieboard
 endef
 
 define uboot/Cubieboard2
-  TITLE:=U-Boot 2014.01-rc1 for Cubieboard2
+  TITLE:=U-Boot 2014.04 for Cubieboard2
 endef
 
 define uboot/Cubietruck
-  TITLE:=U-Boot 2014.01-rc1 for Cubietruck
+  TITLE:=U-Boot 2014.04 for Cubietruck
 endef
 
 define uboot/Hackberry
-  TITLE:=U-Boot 2014.01-rc1 for the Hackbeery
+  TITLE:=U-Boot 2014.04 for the Hackbeery
 endef
 
 define uboot/pcDuino
-  TITLE:=U-Boot 2014.01-rc1 for pcDuino
+  TITLE:=U-Boot 2014.04 for pcDuino
 endef  
 
-define uboot/pcDuino3
-  TITLE:=U-Boot 2014.01-rc1 for pcDuino3
+define uboot/Linksprite_pcDuino3
+  TITLE:=U-Boot 2014.04 for Linksprite pcDuino3
 endef  
 
-UBOOTS:=A10-OLinuXino-Lime A13-OLinuXino A20-OLinuXino_MICRO bananapi Cubieboard Cubieboard2 Cubietruck Hackberry pcDuino pcDuino3
+UBOOTS:=A10-OLinuXino-Lime A13-OLinuXino A20-OLinuXino_MICRO Bananapi Cubieboard Cubieboard2 Cubietruck Hackberry pcDuino Linksprite_pcDuino3
 
 define Package/uboot/template
 define Package/uboot-sunxi-$(1)
diff --git a/package/boot/uboot-sunxi/patches/001-zuperman-d57e8f49a52e59486f49346975c826cf4c298d7e.patch b/package/boot/uboot-sunxi/patches/001-uboot-sunxi-509d96d4f1f602d62d36db660973249e16f9d088.patch
index c3aed21..15aac6b 100644
--- a/package/boot/uboot-sunxi/patches/001-zuperman-d57e8f49a52e59486f49346975c826cf4c298d7e.patch
+++ b/package/boot/uboot-sunxi/patches/001-uboot-sunxi-509d96d4f1f602d62d36db660973249e16f9d088.patch
@@ -1,27 +1,11 @@
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/cmd_boot.c u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/cmd_boot.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c	2014-03-05 23:14:47.108100778 +0100
-@@ -0,0 +1,36 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/cmd_boot.c u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/cmd_boot.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c	2014-09-06 16:58:35.193953144 +0200
+@@ -0,0 +1,20 @@
 +/*
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +/*
@@ -38,415 +22,24 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/cmd_boot.c u-boot-sunxi/arch/arm
 +	return entry(argc, argv);
 +}
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/Makefile u-boot-sunxi/arch/arm/cpu/armv7/Makefile
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/Makefile	2014-03-05 23:14:47.108100778 +0100
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/Makefile u-boot-sunxi/arch/arm/cpu/armv7/Makefile
+--- u-boot-2014.04/arch/arm/cpu/armv7/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/arch/arm/cpu/armv7/Makefile	2014-09-06 16:58:35.185953145 +0200
 @@ -11,8 +11,9 @@
  
  obj-y	+= cpu.o
  obj-y	+= syslib.o
 +obj-y	+= cmd_boot.o
  
--ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
-+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_SUNXI),)
+-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
++ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
  ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
  obj-y	+= lowlevel_init.o
  endif
-@@ -21,6 +22,11 @@
- ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
- obj-y	+= nonsec_virt.o
- obj-y	+= virt-v7.o
-+obj-y	+= virt-dt.o
-+endif
-+
-+ifneq ($(CONFIG_ARMV7_PSCI),)
-+obj-y	+= psci.o
- endif
- 
- obj-$(CONFIG_OMAP_COMMON) += omap-common/
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/nonsec_virt.S u-boot-sunxi/arch/arm/cpu/armv7/nonsec_virt.S
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/nonsec_virt.S	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/nonsec_virt.S	2014-03-05 23:14:47.116100672 +0100
-@@ -10,10 +10,15 @@
- #include <linux/linkage.h>
- #include <asm/gic.h>
- #include <asm/armv7.h>
-+#include <asm/proc-armv/ptrace.h>
- 
- .arch_extension sec
- .arch_extension virt
- 
-+	.pushsection ._secure.text, "ax"
-+
-+	.align	5				@ Minimal alignment for vectors
-+
- /* the vector table for secure state and HYP mode */
- _monitor_vectors:
- 	.word 0	/* reset */
-@@ -21,44 +26,92 @@
- 	adr pc, _secure_monitor
- 	.word 0
- 	.word 0
--	adr pc, _hyp_trap
- 	.word 0
- 	.word 0
-+	.word 0
-+
-+.macro is_cpu_virt_capable	tmp
-+	mrc	p15, 0, \tmp, c0, c1, 1		@ read ID_PFR1
-+	and	\tmp, \tmp, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
-+	cmp	\tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
-+.endm
- 
- /*
-  * secure monitor handler
-  * U-boot calls this "software interrupt" in start.S
-  * This is executed on a "smc" instruction, we use a "smc #0" to switch
-  * to non-secure state.
-- * We use only r0 and r1 here, due to constraints in the caller.
-+ * r0, r1, r2: passed to the callee
-+ * ip: target PC
-  */
--	.align	5
- _secure_monitor:
--	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
--	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
--	orr	r1, r1, #0x31			@ enable NS, AW, FW bits
--
--#ifdef CONFIG_ARMV7_VIRT
--	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
--	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
--	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
--	orreq	r1, r1, #0x100			@ allow HVC instruction
-+#ifdef CONFIG_ARMV7_PSCI
-+	ldr	r5, =_psci_vectors		@ Switch to the next monitor
-+	mcr	p15, 0, r5, c12, c0, 1
-+	isb
- #endif
- 
--	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
-+	mrc	p15, 0, r5, c1, c1, 0		@ read SCR
-+	bic	r5, r5, #0x4e			@ clear IRQ, FIQ, EA, nET bits
-+	orr	r5, r5, #0x31			@ enable NS, AW, FW bits
- 
-+	mov	r6, #SVC_MODE			@ default mode is SVC
-+	is_cpu_virt_capable r4
- #ifdef CONFIG_ARMV7_VIRT
--	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value
--	mcreq	p15, 4, r0, c12, c0, 0		@ write HVBAR
-+	orreq	r5, r5, #0x100			@ allow HVC instruction
-+	moveq	r6, #HYP_MODE			@ Enter the kernel as HYP
- #endif
- 
--	movs	pc, lr				@ return to non-secure SVC
-+	mcr	p15, 0, r5, c1, c1, 0		@ write SCR (with NS bit set)
-+	isb
-+
-+	bne	1f
-+
-+	@ Reset CNTVOFF to 0 before leaving monitor mode
-+	mrc	p15, 0, r4, c0, c1, 1		@ read ID_PFR1
-+	ands	r4, r4, #CPUID_ARM_GENTIMER_MASK	@ test arch timer bits
-+	movne	r4, #0
-+	mcrrne	p15, 4, r4, r4, c14		@ Reset CNTVOFF to zero
-+1:
-+	mov	lr, ip
-+	mov	ip, #(F_BIT | I_BIT | A_BIT)	@ Set A, I and F
-+	tst	lr, #1				@ Check for Thumb PC
-+	orrne	ip, ip, #T_BIT			@ Set T if Thumb
-+	orr	ip, ip, r6			@ Slot target mode in
-+	msr	spsr_cxfs, ip			@ Set full SPSR
-+	movs	pc, lr				@ ERET to non-secure
-+
-+ENTRY(_do_nonsec_entry)
-+	mov	ip, r0
-+	mov	r0, r1
-+	mov	r1, r2
-+	mov	r2, r3
-+	smc	#0
-+ENDPROC(_do_nonsec_entry)
-+
-+.macro get_cbar_addr	addr
-+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-+	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
-+#else
-+	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
-+	bfc	\addr, #0, #15			@ clear reserved bits
-+#endif
-+.endm
- 
--_hyp_trap:
--	mrs	lr, elr_hyp	@ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
--	mov pc, lr				@ do no switch modes, but
--						@ return to caller
-+.macro get_gicd_addr	addr
-+	get_cbar_addr	\addr
-+	add	\addr, \addr, #GIC_DIST_OFFSET	@ GIC dist i/f offset
-+.endm
-+
-+.macro get_gicc_addr	addr, tmp
-+	get_cbar_addr	\addr
-+	is_cpu_virt_capable \tmp
-+	movne	\tmp, #GIC_CPU_OFFSET_A9	@ GIC CPU offset for A9
-+	moveq	\tmp, #GIC_CPU_OFFSET_A15	@ GIC CPU offset for A15/A7
-+	add	\addr, \addr, \tmp
-+.endm
- 
-+#ifndef CONFIG_ARMV7_PSCI
- /*
-  * Secondary CPUs start here and call the code for the core specific parts
-  * of the non-secure and HYP mode transition. The GIC distributor specific
-@@ -66,31 +119,21 @@
-  * Then they go back to wfi and wait to be woken up by the kernel again.
-  */
- ENTRY(_smp_pen)
--	mrs	r0, cpsr
--	orr	r0, r0, #0xc0
--	msr	cpsr, r0			@ disable interrupts
--	ldr	r1, =_start
--	mcr	p15, 0, r1, c12, c0, 0		@ set VBAR
-+	cpsid	i
-+	cpsid	f
- 
- 	bl	_nonsec_init
--	mov	r12, r0				@ save GICC address
--#ifdef CONFIG_ARMV7_VIRT
--	bl	_switch_to_hyp
--#endif
--
--	ldr	r1, [r12, #GICC_IAR]		@ acknowledge IPI
--	str	r1, [r12, #GICC_EOIR]		@ signal end of interrupt
- 
- 	adr	r0, _smp_pen			@ do not use this address again
- 	b	smp_waitloop			@ wait for IPIs, board specific
- ENDPROC(_smp_pen)
-+#endif
- 
- /*
-  * Switch a core to non-secure state.
-  *
-  *  1. initialize the GIC per-core interface
-  *  2. allow coprocessor access in non-secure modes
-- *  3. switch the cpu mode (by calling "smc #0")
-  *
-  * Called from smp_pen by secondary cores and directly by the BSP.
-  * Do not assume that the stack is available and only use registers
-@@ -100,38 +143,23 @@
-  * though, but we check this in C before calling this function.
-  */
- ENTRY(_nonsec_init)
--#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
--	ldr	r2, =CONFIG_ARM_GIC_BASE_ADDRESS
--#else
--	mrc	p15, 4, r2, c15, c0, 0		@ read CBAR
--	bfc	r2, #0, #15			@ clear reserved bits
--#endif
--	add	r3, r2, #GIC_DIST_OFFSET	@ GIC dist i/f offset
-+	get_gicd_addr	r3
-+
- 	mvn	r1, #0				@ all bits to 1
- 	str	r1, [r3, #GICD_IGROUPRn]	@ allow private interrupts
- 
--	mrc	p15, 0, r0, c0, c0, 0		@ read MIDR
--	ldr	r1, =MIDR_PRIMARY_PART_MASK
--	and	r0, r0, r1			@ mask out variant and revision
--
--	ldr	r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
--	cmp	r0, r1				@ check for Cortex-A7
--
--	ldr	r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
--	cmpne	r0, r1				@ check for Cortex-A15
--
--	movne	r1, #GIC_CPU_OFFSET_A9		@ GIC CPU offset for A9
--	moveq	r1, #GIC_CPU_OFFSET_A15		@ GIC CPU offset for A15/A7
--	add	r3, r2, r1			@ r3 = GIC CPU i/f addr
-+	get_gicc_addr	r3, r1
- 
- 	mov	r1, #1				@ set GICC_CTLR[enable]
- 	str	r1, [r3, #GICC_CTLR]		@ and clear all other bits
- 	mov	r1, #0xff
- 	str	r1, [r3, #GICC_PMR]		@ set priority mask register
- 
-+	mrc	p15, 0, r0, c1, c1, 2
- 	movw	r1, #0x3fff
--	movt	r1, #0x0006
--	mcr	p15, 0, r1, c1, c1, 2		@ NSACR = all copros to non-sec
-+	movt	r1, #0x0004
-+	orr	r0, r0, r1
-+	mcr	p15, 0, r0, c1, c1, 2		@ NSACR = all copros to non-sec
- 
- /* The CNTFRQ register of the generic timer needs to be
-  * programmed in secure state. Some primary bootloaders / firmware
-@@ -149,44 +177,24 @@
- 
- 	adr	r1, _monitor_vectors
- 	mcr	p15, 0, r1, c12, c0, 1		@ set MVBAR to secure vectors
--
--	mrc	p15, 0, ip, c12, c0, 0		@ save secure copy of VBAR
--
- 	isb
--	smc	#0				@ call into MONITOR mode
--
--	mcr	p15, 0, ip, c12, c0, 0		@ write non-secure copy of VBAR
--
--	mov	r1, #1
--	str	r1, [r3, #GICC_CTLR]		@ enable non-secure CPU i/f
--	add	r2, r2, #GIC_DIST_OFFSET
--	str	r1, [r2, #GICD_CTLR]		@ allow private interrupts
- 
- 	mov	r0, r3				@ return GICC address
--
- 	bx	lr
- ENDPROC(_nonsec_init)
- 
- #ifdef CONFIG_SMP_PEN_ADDR
- /* void __weak smp_waitloop(unsigned previous_address); */
- ENTRY(smp_waitloop)
--	wfi
-+	wfe
- 	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
- 	ldr	r1, [r1]
- 	cmp	r0, r1			@ make sure we dont execute this code
- 	beq	smp_waitloop		@ again (due to a spurious wakeup)
--	mov	pc, r1
-+	mov	r0, r1
-+	b	_do_nonsec_entry
- ENDPROC(smp_waitloop)
- .weak smp_waitloop
- #endif
- 
--ENTRY(_switch_to_hyp)
--	mov	r0, lr
--	mov	r1, sp				@ save SVC copy of LR and SP
--	isb
--	hvc #0			 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
--	mov	sp, r1
--	mov	lr, r0				@ restore SVC copy of LR and SP
--
--	bx	lr
--ENDPROC(_switch_to_hyp)
-+	.popsection
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/psci.S u-boot-sunxi/arch/arm/cpu/armv7/psci.S
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/psci.S	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/psci.S	2014-03-05 23:14:47.124100564 +0100
-@@ -0,0 +1,113 @@
-+/*
-+ * Copyright (C) 2013 - ARM Ltd
-+ * Author: Marc Zyngier <marc.zyngier@arm.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <config.h>
-+#include <linux/linkage.h>
-+#include <asm/psci.h>
-+
-+	.pushsection ._secure.text, "ax"
-+
-+	.arch_extension	sec
-+
-+	.align	5
-+	.globl _psci_vectors
-+_psci_vectors:
-+	adr	pc, .		@ reset
-+	adr	pc, .		@ undef
-+	adr	pc, _smc_psci	@ smc
-+	adr	pc, .		@ pabort
-+	adr	pc, .		@ dabort
-+	adr	pc, .		@ hyp
-+	adr	pc, .		@ irq
-+	adr	pc, .		@ fiq
-+
-+ENTRY(psci_cpu_suspend)
-+ENTRY(psci_cpu_off)
-+ENTRY(psci_cpu_on)
-+ENTRY(psci_migrate)
-+	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
-+	mov	pc, lr
-+ENDPROC(psci_migrate)
-+ENDPROC(psci_cpu_on)
-+ENDPROC(psci_cpu_off)
-+ENDPROC(psci_cpu_suspend)
-+.weak psci_cpu_suspend
-+.weak psci_cpu_off
-+.weak psci_cpu_on
-+.weak psci_migrate
-+
-+_psci_table:
-+	.word	ARM_PSCI_FN_CPU_SUSPEND
-+	.word	psci_cpu_suspend
-+	.word	ARM_PSCI_FN_CPU_OFF
-+	.word	psci_cpu_off
-+	.word	ARM_PSCI_FN_CPU_ON
-+	.word	psci_cpu_on
-+	.word	ARM_PSCI_FN_MIGRATE
-+	.word	psci_migrate
-+	.word	0
-+	.word	0
-+
-+_secure_stacks:			@ Enough to save 16 registers per CPU
-+	.skip	16*4*CONFIG_ARMV7_PSCI_NR_CPUS
-+_secure_stack_base:
-+
-+_smc_psci:
-+	@ Switch to secure mode
-+	mrc	p15, 0, sp, c1, c1, 0
-+	bic	sp, sp, #1
-+	mcr	p15, 0, sp, c1, c1, 0
-+
-+	adr	sp, _secure_stack_base
-+	mcr	p15, 0, r0, c13, c0, 4	@ use TPIDRPRW as a tmp reg
-+	mcr	p15, 0, r1, c13, c0, 3	@ use TPIDRURO as a tmp reg
-+	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR
-+	and	r1, r0, #3		@ cpu number in cluster
-+	lsr	r0, r0, #8
-+	and	r0, r0, #3		@ cluster number
-+	mul	r1, r1, r0		@ absolute cpu nr
-+	sbc	sp, sp, r1, lsl #6	@ sp = sp_base - 64*cpunr
-+
-+	mrc	p15, 0, r0, c13, c0, 4	@ restore r0
-+	mrc	p15, 0, r1, c13, c0, 3	@ restore r1
-+
-+	push	{r4-r12,lr}
-+
-+	adr	r4, _psci_table
-+1:	ldr	r5, [r4]	@ Load PSCI function ID
-+	ldr	r6, [r4, #4]	@ Load target PC
-+	cmp	r5, #0		@ If reach the end, bail out
-+	mvneq	r0, #0		@ Return -1 (Not Implemented)
-+	beq	2f
-+	cmp	r0, r5		@ If not matching, try next entry
-+	addne	r4, r4, #8
-+	bne	1b
-+	cmp	r6, #0		@ Not implemented
-+	moveq	r0, #ARM_PSCI_RET_NI
-+	beq	2f
-+
-+	blx	r6		@ Execute PSCI function
-+
-+2:	pop	{r4-r12, lr}
-+
-+	@ Back to non-secure
-+	mrc	p15, 0, sp, c1, c1, 0
-+	orr	sp, sp, #1
-+	mcr	p15, 0, sp, c1, c1, 0
-+	movs	pc, lr		@ Return to the kernel
-+
-+	.popsection
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,158 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/board.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,166 @@
 +/*
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
@@ -456,23 +49,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 + *
 + * Some init for sunxi platform.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -496,7 +73,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +/* The sunxi internal brom will try to loader external bootloader
-+ * from mmc0, nannd flash, mmc2.
++ * from mmc0, nand flash, mmc2.
 + * Unfortunately we can't check how SPL was loaded so assume
 + * it's always the first SD/MMC controller
 + */
@@ -536,9 +113,13 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
 +	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
 +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
-+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART0_TX);
-+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART0_RX);
++	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
++	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
 +	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
++#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
++	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
++	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
++	sunxi_gpio_set_pull(SUNXI_GPL(3), 1);
 +#else
 +#error Unsupported console port number. Please fix pin mux settings in board.c
 +#endif
@@ -559,7 +140,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 +	asm volatile(
 +		"mrc p15, 0, r0, c1, c0, 1\n"
-+		"orr r0, r0, #0x40\n"
++		"orr r0, r0, #1 << 6\n"
 +		"mcr p15, 0, r0, c1, c0, 1\n");
 +#endif
 +
@@ -567,6 +148,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +	clock_init();
 +	timer_init();
 +	gpio_init();
++	i2c_init_board();
 +
 +#ifdef CONFIG_SPL_BUILD
 +	gd = &gdata;
@@ -576,7 +158,9 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +	/* Needed early by sunxi_board_init if PMU is enabled */
 +	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 +#endif
-+
++#endif
++/* No SPL on sun6i, so we do sunxi_board_init() from non spl there */
++#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 +	sunxi_board_init();
 +#endif
 +}
@@ -589,26 +173,43 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/
 +}
 +#endif
 +
-+#if defined(CONFIG_SUNXI_EMAC) || defined(CONFIG_SUNXI_GMAC)
++#ifdef CONFIG_CMD_NET
 +/*
 + * Initializes on-chip ethernet controllers.
 + * to override, implement board_eth_init()
 + */
 +int cpu_eth_init(bd_t *bis)
 +{
++	__maybe_unused int rc;
++
++#ifdef CONFIG_MACPWR
++	gpio_direction_output(CONFIG_MACPWR, 1);
++	mdelay(200);
++#endif
++
 +#ifdef CONFIG_SUNXI_EMAC
-+	sunxi_emac_initialize(bis);
-+#else
-+	sunxi_gmac_initialize(bis);
++	rc = sunxi_emac_initialize(bis);
++	if (rc < 0) {
++		printf("sunxi: failed to initialize emac\n");
++		return rc;
++	}
++#endif
++
++#ifdef CONFIG_SUNXI_GMAC
++	rc = sunxi_gmac_initialize(bis);
++	if (rc < 0) {
++		printf("sunxi: failed to initialize gmac\n");
++		return rc;
++	}
 +#endif
 +
 +	return 0;
 +}
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,204 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,25 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -616,23 +217,38 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 + *
 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/sys_proto.h>
++
++int clock_init(void)
++{
++#ifdef CONFIG_SPL_BUILD
++	clock_init_safe();
++#endif
++	clock_init_uart();
++
++	return 0;
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun4i.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun4i.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun4i.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,188 @@
++/*
++ * sun4i, sun5i and sun7i specific clock code
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
++ * (C) Copyright 2007-2012
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -642,82 +258,46 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +#include <asm/arch/sys_proto.h>
 +
 +#ifdef CONFIG_SPL_BUILD
-+static void clock_init_safe(void)
++void clock_init_safe(void)
 +{
 +	struct sunxi_ccm_reg * const ccm =
 +		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 +
 +	/* Set safe defaults until PMU is configured */
-+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
-+	       CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
-+	writel(0xa1005000, &ccm->pll1_cfg);
++	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
++	       AHB_DIV_2 << AHB_DIV_SHIFT |
++	       APB0_DIV_1 << APB0_DIV_SHIFT |
++	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
++	       &ccm->cpu_ahb_apb0_cfg);
++	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
 +	sdelay(200);
-+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
-+	       CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
-+#ifdef CONFIG_SUN5I
-+	/* Power on reset default for PLL6 is 2400 MHz, which is faster then
-+	 * it can reliable do :|  Set it to a 600 MHz instead. */
-+	writel(0x21009911, &ccm->pll6_cfg);
-+#endif
++	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
++	       AHB_DIV_2 << AHB_DIV_SHIFT |
++	       APB0_DIV_1 << APB0_DIV_SHIFT |
++	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
++	       &ccm->cpu_ahb_apb0_cfg);
 +#ifdef CONFIG_SUN7I
-+	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
-+	writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
++	writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
++	       &ccm->ahb_gate0);
 +#endif
++	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 +}
 +#endif
 +
-+int clock_init(void)
++void clock_init_uart(void)
 +{
 +	struct sunxi_ccm_reg *const ccm =
 +		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 +
-+#ifdef CONFIG_SPL_BUILD
-+	clock_init_safe();
-+#endif
-+
-+#if defined(CONFIG_SUN6I)
-+	/* uart clock source is apb2 */
-+	sr32(&ccm->apb2_div, 24, 2, APB2_CLK_SRC_OSC24M);
-+	sr32(&ccm->apb2_div, 16, 2, APB2_FACTOR_N);
-+	sr32(&ccm->apb2_div, 0, 5, APB2_FACTOR_M);
-+
-+	/* open the clock for uart */
-+	sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
-+#else
 +	/* uart clock source is apb1 */
-+	sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
-+	sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
-+	sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
++	writel(APB1_CLK_SRC_OSC24M|
++	       APB1_CLK_RATE_N_1|
++	       APB1_CLK_RATE_M(1),
++	       &ccm->apb1_clk_div_cfg);
 +
 +	/* open the clock for uart */
-+	sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
-+#endif
-+
-+#ifdef CONFIG_NAND_SUNXI
-+	/* nand clock source is osc24m */
-+	sr32(&ccm->nand_sclk_cfg, 24, 2, NAND_CLK_SRC_OSC24);
-+	sr32(&ccm->nand_sclk_cfg, 16, 2, NAND_CLK_DIV_N);
-+	sr32(&ccm->nand_sclk_cfg, 0, 4, NAND_CLK_DIV_M);
-+	sr32(&ccm->nand_sclk_cfg, 31, 1, CLK_GATE_OPEN);
-+	/* open clock for nand */
-+	sr32(&ccm->ahb_gate0, AHB_GATE_OFFSET_NAND, 1, CLK_GATE_OPEN);
-+#endif
-+
-+	return 0;
-+}
-+
-+/* Return PLL5 frequency in Hz
-+ * Note: Assumes PLL5 reference is 24MHz clock
-+ */
-+unsigned int clock_get_pll5(void)
-+{
-+	struct sunxi_ccm_reg *const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+	uint32_t rval = readl(&ccm->pll5_cfg);
-+	int n = (rval >> 8) & 0x1f;
-+	int k = ((rval >> 4) & 3) + 1;
-+	int p = 1 << ((rval >> 16) & 3);
-+	return 24000000 * n * k / p;
++	setbits_le32(&ccm->apb1_gate,
++		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
 +}
 +
 +int clock_twi_onoff(int port, int state)
@@ -728,22 +308,36 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +	if (port > 2)
 +		return -1;
 +
-+	/* set the apb1 clock gate for twi */
-+	sr32(&ccm->apb1_gate, 0 + port, 1, state);
++	/* set the apb clock gate for twi */
++	if (state)
++		setbits_le32(&ccm->apb1_gate,
++			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
++	else
++		clrbits_le32(&ccm->apb1_gate,
++			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
 +
 +	return 0;
 +}
 +
 +#ifdef CONFIG_SPL_BUILD
-+#define PLL1_CFG(N, K, M, P)	(1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \
-+				 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
-+				 (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
-+#define RDIV(a, b)		((a + (b) - 1) / (b))
-+
-+struct {
++#define PLL1_CFG(N, K, M, P)	( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
++				  0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
++				  8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
++				  0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
++				 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
++				 (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
++				  2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
++				 (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
++				 (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
++				  0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
++				  0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
++				 (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
++
++static struct {
 +	u32 pll1_cfg;
 +	unsigned int freq;
 +} pll1_para[] = {
++	/* This array must be ordered by frequency. */
 +	{ PLL1_CFG(16, 0, 0, 0), 384000000 },
 +	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
 +	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
@@ -758,10 +352,11 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +	{ PLL1_CFG(29, 1, 0, 0), 1392000000},
 +	{ PLL1_CFG(30, 1, 0, 0), 1440000000},
 +	{ PLL1_CFG(31, 1, 0, 0), 1488000000},
++	/* Final catchall entry */
 +	{ PLL1_CFG(31, 1, 0, 0), ~0},
 +};
 +
-+void clock_set_pll1(int hz)
++void clock_set_pll1(unsigned int hz)
 +{
 +	int i = 0;
 +	int axi, ahb, apb0;
@@ -775,11 +370,11 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +	hz = pll1_para[i].freq;
 +
 +	/* Calculate system clock divisors */
-+	axi = RDIV(hz, 432000000);		/* Max 450MHz */
-+	ahb = RDIV(hz/axi, 204000000);		/* Max 250MHz */
++	axi = DIV_ROUND_UP(hz, 432000000);	/* Max 450MHz */
++	ahb = DIV_ROUND_UP(hz/axi, 204000000);	/* Max 250MHz */
 +	apb0 = 2;				/* Max 150MHz */
 +
-+	printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
++	printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
 +
 +	/* Map divisors to register values */
 +	axi = axi - 1;
@@ -795,12 +390,18 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +	apb0 = apb0 - 1;
 +
 +	/* Switch to 24MHz clock while changing PLL1 */
-+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
-+	       CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
++	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
++	       AHB_DIV_2 << AHB_DIV_SHIFT |
++	       APB0_DIV_1 << APB0_DIV_SHIFT |
++	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
++	       &ccm->cpu_ahb_apb0_cfg);
 +	sdelay(20);
 +
 +	/* Configure sys clock divisors */
-+	writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_OSC24M << 16,
++	writel(axi << AXI_DIV_SHIFT |
++	       ahb << AHB_DIV_SHIFT |
++	       apb0 << APB0_DIV_SHIFT |
++	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 +	       &ccm->cpu_ahb_apb0_cfg);
 +
 +	/* Configure PLL1 at the desired frequency */
@@ -808,32 +409,146 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/
 +	sdelay(200);
 +
 +	/* Switch CPU to PLL1 */
-+	writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_PLL1 << 16,
++	writel(axi << AXI_DIV_SHIFT |
++	       ahb << AHB_DIV_SHIFT |
++	       apb0 << APB0_DIV_SHIFT |
++	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 +	       &ccm->cpu_ahb_apb0_cfg);
 +	sdelay(20);
 +}
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,42 @@
++
++unsigned int clock_get_pll6(void)
++{
++	struct sunxi_ccm_reg *const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++	uint32_t rval = readl(&ccm->pll6_cfg);
++	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
++	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
++	return 24000000 * n * k / 2;
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun6i.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun6i.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun6i.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,110 @@
 +/*
-+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
++ * sun6i specific clock code
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
++ * (C) Copyright 2007-2012
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/prcm.h>
++#include <asm/arch/sys_proto.h>
++
++#ifdef CONFIG_SPL_BUILD
++void clock_init_safe(void)
++{
++	struct sunxi_ccm_reg * const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++	struct sunxi_prcm_reg * const prcm =
++		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
++
++	/* Set PLL ldo voltage without this PLL6 does not work properly */
++	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
++		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
++		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
++	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
++		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
++		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
++	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
++		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
++		&prcm->pll_ctrl1);
++
++	/* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
++	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
++	       ATB_DIV_2 << ATB_DIV_SHIFT |
++	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
++	       &ccm->cpu_axi_cfg);
++	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
++	sdelay(200);
++	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
++	       ATB_DIV_2 << ATB_DIV_SHIFT |
++	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
++	       &ccm->cpu_axi_cfg);
++
++	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
++}
++#endif
++
++void clock_init_uart(void)
++{
++	struct sunxi_ccm_reg *const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++#if CONFIG_CONS_INDEX < 5
++	/* uart clock source is apb2 */
++	writel(APB2_CLK_SRC_OSC24M|
++	       APB2_CLK_RATE_N_1|
++	       APB2_CLK_RATE_M(1),
++	       &ccm->apb2_div);
++
++	/* open the clock for uart */
++	setbits_le32(&ccm->apb2_gate,
++		CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
++
++	/* deassert uart reset */
++	setbits_le32(&ccm->apb2_reset_cfg,
++		1 << (APB2_RESET_UART_SHIFT+CONFIG_CONS_INDEX-1));
++#else
++	/* enable R_PIO and R_UART clocks, and de-assert resets */
++	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
++#endif
++
++	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
++	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
++}
++
++int clock_twi_onoff(int port, int state)
++{
++	struct sunxi_ccm_reg *const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++	if (port > 3)
++		return -1;
++
++	/* set the apb clock gate for twi */
++	if (state)
++		setbits_le32(&ccm->apb2_gate,
++			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
++	else
++		clrbits_le32(&ccm->apb2_gate,
++			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
++
++	return 0;
++}
++
++unsigned int clock_get_pll6(void)
++{
++	struct sunxi_ccm_reg *const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++	uint32_t rval = readl(&ccm->pll6_cfg);
++	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
++	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
++	return 24000000 * n * k / 2;
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,29 @@
++/*
++ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -859,44 +574,28 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c u-boot-sunx
 +	"Set watchdog [0 - 16]. [17+} disables",
 +	""
 +);
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/config.mk u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/config.mk	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk	2014-03-05 23:14:47.128100511 +0100
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/config.mk u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/config.mk	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk	2014-09-06 16:58:35.317953141 +0200
 @@ -0,0 +1,8 @@
 +# Build a combined spl + u-boot image
 +ifdef CONFIG_SPL
 +ifndef CONFIG_SPL_BUILD
 +ifndef CONFIG_SPL_FEL
-+ALL-y = $(obj)u-boot-sunxi-with-spl.bin
++ALL-y += u-boot-sunxi-with-spl.bin
 +endif
 +endif
 +endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,47 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cpu_info.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,38 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -909,12 +608,19 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/ar
 +#ifdef CONFIG_SUN4I
 +	puts("CPU:   Allwinner A10 (SUN4I)\n");
 +#elif defined CONFIG_SUN5I
-+	/* TODO: Distinguish A13/A10s */
-+	puts("CPU:   Allwinner A13/A10s (SUN5I)\n");
++	u32 val = readl(SUNXI_SID_BASE + 0x08);
++	switch ((val >> 12) & 0xf) {
++	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
++	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
++	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
++	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
++	}
 +#elif defined CONFIG_SUN6I
 +	puts("CPU:   Allwinner A31 (SUN6I)\n");
 +#elif defined CONFIG_SUN7I
 +	puts("CPU:   Allwinner A20 (SUN7I)\n");
++#elif defined CONFIG_SUN8I
++	puts("CPU:   Allwinner A23 (SUN8I)\n");
 +#else
 +#warning Please update cpu_info.c with correct CPU information
 +	puts("CPU:   SUNXI Family\n");
@@ -922,10 +628,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/ar
 +	return 0;
 +}
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,679 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/dram.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,693 @@
 +/*
 + * sunxi DRAM controller initialization
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
@@ -939,23 +645,14 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 + * Berg Xing <bergxing@allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++/*
++ * Unfortunately the only documentation we have on the sun7i DRAM
++ * controller is Allwinner boot0 + boot1 code, and that code uses
++ * magic numbers & shifts with no explanations. Hence this code is
++ * rather undocumented and full of magic.
 + */
 +
 +#include <common.h>
@@ -972,6 +669,19 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +#define CPU_CFG_CHIP_REV_C2 0x2
 +#define CPU_CFG_CHIP_REV_B 0x3
 +
++/*
++ * Wait up to 1s for mask to be clear in given reg.
++ */
++static void await_completion(u32 *reg, u32 mask)
++{
++	unsigned long tmo = timer_get_us() + 1000000;
++
++	while (readl(reg) & mask) {
++		if (timer_get_us() > tmo)
++			panic("Timeout initialising DRAM\n");
++	}
++}
++
 +static void mctl_ddr3_reset(void)
 +{
 +	struct sunxi_dram_reg *dram =
@@ -1059,11 +769,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +		n = DRAM_DCR_NR_DLLCR_16BIT;
 +
 +	for (i = 1; i < n; i++) {
-+#ifdef CONFIG_SUN7I
 +		clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
-+#else
-+		clrsetbits_le32(&dram->dllcr[i], 0x4 << 14,
-+#endif
 +				(phase & 0xf) << 14);
 +		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
 +				DRAM_DLLCR_DISABLE);
@@ -1098,7 +804,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	0x0301, 0x0301, 0, 0,
 +	0, 0, 0, 0,
 +	0, 0, 0, 0,
-+	0x1031, 0x1031, 0x0735, 0x1035,
++	0x1031, 0x1031, 0x0735, 0x5031,
 +	0x1035, 0x0731, 0x1031, 0x0735,
 +	0x1035, 0x1031, 0x0731, 0x1035,
 +	0x1031, 0x0301, 0x0301, 0x0731
@@ -1116,7 +822,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	 * 0x1031, 0x0301, 0x0301, 0x0731
 +	 * but boot0 code skips #28 and #30, and sets #29 and #31 to the
 +	 * value from #28 entry (0x1031)
-+         */
++	 */
 +#endif
 +};
 +
@@ -1137,13 +843,46 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	/* setup DRAM PLL */
 +	reg_val = readl(&ccm->pll5_cfg);
 +	reg_val &= ~CCM_PLL5_CTRL_M_MASK;		/* set M to 0 (x1) */
-+	reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 +	reg_val &= ~CCM_PLL5_CTRL_K_MASK;		/* set K to 0 (x1) */
-+	reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
 +	reg_val &= ~CCM_PLL5_CTRL_N_MASK;		/* set N to 0 (x0) */
-+	reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
 +	reg_val &= ~CCM_PLL5_CTRL_P_MASK;		/* set P to 0 (x1) */
-+	reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
++	if (clk >= 540 && clk < 552) {
++		/* dram = 540MHz, pll5p = 540MHz */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
++		reg_val |= CCM_PLL5_CTRL_P(1);
++	} else if (clk >= 512 && clk < 528) {
++		/* dram = 512MHz, pll5p = 384MHz */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
++		reg_val |= CCM_PLL5_CTRL_P(2);
++	} else if (clk >= 496 && clk < 504) {
++		/* dram = 496MHz, pll5p = 372MHz */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
++		reg_val |= CCM_PLL5_CTRL_P(2);
++	} else if (clk >= 468 && clk < 480) {
++		/* dram = 468MHz, pll5p = 468MHz */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
++		reg_val |= CCM_PLL5_CTRL_P(1);
++	} else if (clk >= 396 && clk < 408) {
++		/* dram = 396MHz, pll5p = 396MHz */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
++		reg_val |= CCM_PLL5_CTRL_P(1);
++	} else 	{
++		/* any other frequency that is a multiple of 24 */
++		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
++		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
++		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
++		reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
++	}
 +	reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;		/* PLL VCO Gain off */
 +	reg_val |= CCM_PLL5_CTRL_EN;			/* PLL On */
 +	writel(reg_val, &ccm->pll5_cfg);
@@ -1159,6 +898,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 +#endif
 +
++#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 +	/* setup MBUS clock */
 +	reg_val = CCM_MBUS_CTRL_GATE |
 +#if defined(CONFIG_SUN7I) && defined(CONFIG_FAST_MBUS)
@@ -1175,6 +915,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
 +#endif
 +	writel(reg_val, &ccm->mbus_clk_cfg);
++#endif
 +
 +	/*
 +	 * open DRAMC AHB & DLL register clock
@@ -1208,7 +949,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 +
 +	/* check whether data training process has completed */
-+	while (readl(&dram->ccr) & DRAM_CCR_DATA_TRAINING);
++	await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 +
 +	/* check data training result */
 +	reg_val = readl(&dram->csr);
@@ -1348,53 +1089,30 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +#endif
 +}
 +
-+#ifdef CONFIG_SUN4I
-+static void dramc_set_autorefresh_cycle(u32 clk)
-+{
-+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-+	u32 reg_val;
-+	u32 tmp_val;
-+	u32 reg_dcr;
-+
-+	if (clk < 600) {
-+		reg_dcr = readl(&dram->dcr);
-+		if ((reg_dcr & DRAM_DCR_CHIP_DENSITY_MASK) <=
-+		    DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M))
-+			reg_val = (131 * clk) >> 10;
-+		else
-+			reg_val = (336 * clk) >> 10;
-+
-+		tmp_val = (7987 * clk) >> 10;
-+		tmp_val = tmp_val * 9 - 200;
-+		reg_val |= tmp_val << 8;
-+		reg_val |= 0x8 << 24;
-+		writel(reg_val, &dram->drr);
-+	} else {
-+		writel(0x0, &dram->drr);
-+	}
-+}
-+#endif /* SUN4I */
++static const u16 tRFC_table[2][6] = {
++	/*       256Mb    512Mb    1Gb      2Gb      4Gb      8Gb      */
++	/* DDR2  75ns     105ns    127.5ns  195ns    327.5ns  invalid  */
++	{        77,      108,     131,     200,     336,     336 },
++	/* DDR3  invalid  90ns     110ns    160ns    300ns    350ns    */
++	{        93,      93,      113,     164,     308,     359 }
++};
 +
-+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
-+static void dramc_set_autorefresh_cycle(u32 clk)
++static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
 +{
 +	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-+	u32 reg_val;
-+	u32 tmp_val;
-+	reg_val = 0x83;
++	u32 tRFC, tREFI;
 +
-+	tmp_val = (7987 * clk) >> 10;
-+	tmp_val = tmp_val * 9 - 200;
-+	reg_val |= tmp_val << 8;
-+	reg_val |= 0x8 << 24;
-+	writel(reg_val, &dram->drr);
++	tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
++	tREFI = (7987 * clk) >> 10;	/* <= 7.8us */
++
++	writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
 +}
-+#endif /* SUN5I */
 +
 +unsigned long dramc_init(struct dram_para *para)
 +{
 +	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 +	u32 reg_val;
++	u32 density;
 +	int ret_val;
 +
 +	/* check input dram parameter structure */
@@ -1433,20 +1151,21 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
 +
 +	if (para->density == 256)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
++		density = DRAM_DCR_CHIP_DENSITY_256M;
 +	else if (para->density == 512)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M);
++		density = DRAM_DCR_CHIP_DENSITY_512M;
 +	else if (para->density == 1024)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M);
++		density = DRAM_DCR_CHIP_DENSITY_1024M;
 +	else if (para->density == 2048)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M);
++		density = DRAM_DCR_CHIP_DENSITY_2048M;
 +	else if (para->density == 4096)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M);
++		density = DRAM_DCR_CHIP_DENSITY_4096M;
 +	else if (para->density == 8192)
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M);
++		density = DRAM_DCR_CHIP_DENSITY_8192M;
 +	else
-+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
++		density = DRAM_DCR_CHIP_DENSITY_256M;
 +
++	reg_val |= DRAM_DCR_CHIP_DENSITY(density);
 +	reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
 +	reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
 +	reg_val |= DRAM_DCR_CMD_RANK_ALL;
@@ -1485,12 +1204,12 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +
 +	udelay(1);
 +
-+	while (readl(&dram->ccr) & DRAM_CCR_INIT);
++	await_completion(&dram->ccr, DRAM_CCR_INIT);
 +
 +	mctl_enable_dllx(para->tpr3);
 +
 +#ifdef CONFIG_SUN4I
-+	/* set odt impendance divide ratio */
++	/* set odt impedance divide ratio */
 +	reg_val = ((para->zq) >> 8) & 0xfffff;
 +	reg_val |= ((para->zq) & 0xff) << 20;
 +	reg_val |= (para->zq) & 0xf0000000;
@@ -1506,7 +1225,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +#endif
 +
 +	/* set refresh period */
-+	dramc_set_autorefresh_cycle(para->clock);
++	dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
 +
 +	/* set timing parameters */
 +	writel(para->tpr0, &dram->tpr0);
@@ -1541,7 +1260,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +#endif
 +	/* reset external DRAM */
 +	setbits_le32(&dram->ccr, DRAM_CCR_INIT);
-+	while (readl(&dram->ccr) & DRAM_CCR_INIT);
++	await_completion(&dram->ccr, DRAM_CCR_INIT);
 +
 +#ifdef CONFIG_SUN7I
 +	/* setup zq calibration manual */
@@ -1557,25 +1276,26 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +		/* exit self-refresh state */
 +		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
 +		/* check whether command has been executed */
-+		while (readl(&dram->dcr) & (0x1 << 31));
++		await_completion(&dram->dcr, 0x1 << 31);
 +
 +		udelay(2);
 +
 +		/* dram pad hold off */
 +		setbits_le32(&dram->ppwrsctl, 0x16510000);
 +
-+		while (readl(&dram->ppwrsctl) & 0x1);
++		await_completion(&dram->ppwrsctl, 0x1);
 +
 +		/* exit self-refresh state */
 +		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
 +
 +		/* check whether command has been executed */
-+		while (readl(&dram->dcr) & (0x1 << 31));
-+		udelay(2);;
++		await_completion(&dram->dcr, 0x1 << 31);
++
++		udelay(2);
 +
 +		/* issue a refresh command */
 +		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
-+		while (readl(&dram->dcr) & (0x1 << 31));
++		await_completion(&dram->dcr, 0x1 << 31);
 +
 +		udelay(2);
 +	}
@@ -1603,12 +1323,12 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/a
 +	/* configure all host port */
 +	mctl_configure_hostport();
 +
-+	return get_ram_size((unsigned long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
++	return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,65 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/early_print.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,55 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -1616,23 +1336,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi
 + *
 + * Early uart print for debugging.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -1644,7 +1348,13 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi
 +
 +static int uart_initialized = 0;
 +
++#if CONFIG_CONS_INDEX < 5
 +#define UART	CONFIG_CONS_INDEX-1
++#else
++/* SUNXI_R_UART_BASE */
++#define UART	2922
++#endif
++
 +void uart_init(void) {
 +
 +	/* select dll dlh */
@@ -1674,84 +1384,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi
 +}
 +
 +
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/key.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/key.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/key.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/key.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,70 @@
-+/*
-+ * (C) Copyright 2007-2011
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ * Tom Cubie <tangliang@allwinnertech.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <asm/arch/cpu.h>
-+#include <asm/arch/key.h>
-+#include <asm/arch/sys_proto.h>
-+
-+int sunxi_key_init(void)
-+{
-+	struct sunxi_lradc *sunxi_key_base =
-+		(struct sunxi_lradc *)SUNXI_LRADC_BASE;
-+
-+	sr32(&sunxi_key_base->ctrl, 0, 1, LRADC_EN);
-+	sr32(&sunxi_key_base->ctrl, 2, 2, LRADC_SAMPLE_RATE);
-+	sr32(&sunxi_key_base->ctrl, 4, 2, LEVELB_VOL);
-+	sr32(&sunxi_key_base->ctrl, 6, 1, LRADC_HOLD_EN);
-+	sr32(&sunxi_key_base->ctrl, 12, 2, KEY_MODE_SELECT);
-+
-+	/* disable all key irq */
-+	writel(0x0, &sunxi_key_base->intc);
-+	/* clear all key pending */
-+	writel(0xffffffff, &sunxi_key_base->ints);
-+
-+	return 0;
-+}
-+
-+u32 sunxi_read_key(void)
-+{
-+	u32 ints;
-+	u32 key = 0;
-+	struct sunxi_lradc *sunxi_key_base =
-+		(struct sunxi_lradc *)SUNXI_LRADC_BASE;
-+
-+	ints = readl(&sunxi_key_base->ints);
-+
-+	/* if there is already data pending,
-+	 read it */
-+	if (ints & ADC0_DATA_PENDING) {
-+		key = readl(&sunxi_key_base->data0);
-+#ifdef DEBUG
-+		printf("key pressed, value=0x%x\n", key);
-+#endif
-+	}
-+	/* clear the pending data */
-+	writel(ints, &sunxi_key_base->ints);
-+	return key;
-+}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,56 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,44 @@
 +#
 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 +#
@@ -1759,30 +1395,21 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch
 +# (C) Copyright 2000-2003
 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 +#
-+# See file CREDITS for list of people who contributed to this
-+# project.
++# SPDX-License-Identifier:	GPL-2.0+
 +#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
 +obj-y	+= timer.o
 +obj-y	+= board.o
 +obj-y	+= clock.o
 +obj-y	+= pinmux.o
 +obj-y	+= watchdog.o
++obj-$(CONFIG_SUN6I)	+= prcm.o
++obj-$(CONFIG_SUN8I)	+= prcm.o
++obj-$(CONFIG_SUN6I)	+= p2wi.o
++obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
++obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
++obj-$(CONFIG_SUN6I)	+= clock_sun6i.o
++obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
++obj-$(CONFIG_SUN8I)	+= clock_sun6i.o
 +ifdef DEBUG
 +obj-y	+= early_print.o
 +endif
@@ -1791,49 +1418,154 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch
 +obj-$(CONFIG_SYS_SECONDARY_ON)	+= smp.o
 +
 +ifndef CONFIG_SPL_BUILD
-+obj-y	+= key.o
 +obj-y	+= cpu_info.o
 +ifdef CONFIG_CMD_WATCHDOG
 +obj-$(CONFIG_CMD_WATCHDOG)	+= cmd_watchdog.o
 +endif
-+ifdef CONFIG_ARMV7_PSCI
-+obj-y	+= psci.o
-+endif
 +endif
 +
 +ifdef CONFIG_SPL_BUILD
-+obj-y	+= dram.o
++obj-$(CONFIG_SUN4I)	+= dram.o
++obj-$(CONFIG_SUN5I)	+= dram.o
++obj-$(CONFIG_SUN7I)	+= dram.o
 +ifdef CONFIG_SPL_FEL
 +obj-y	+= start.o
 +endif
 +endif
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/p2wi.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/p2wi.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/p2wi.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/p2wi.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Sunxi A31 Power Management Unit
++ *
++ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ * http://linux-sunxi.org
++ *
++ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
++ *
++ * (C) Copyright 2006-2013
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Berg Xing <bergxing@allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <errno.h>
++#include <asm/io.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/p2wi.h>
++#include <asm/arch/prcm.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/sys_proto.h>
++
++void p2wi_init(void)
++{
++	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
++
++	/* Enable p2wi and PIO clk, and de-assert their resets */
++	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
++
++	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
++	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
++
++	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
++	writel(P2WI_CTRL_RESET, &p2wi->ctrl);
++	sdelay(0x100);
++	writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
++	       &p2wi->cc);
++}
++
++int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data)
++{
++	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
++	int i;
 +
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,96 @@
++	writel(P2WI_PM_DEV_ADDR(slave_addr) |
++	       P2WI_PM_CTRL_ADDR(ctrl_reg) |
++	       P2WI_PM_INIT_DATA(init_data) |
++	       P2WI_PM_INIT_SEND,
++	       &p2wi->pm);
++	for (i = 0xffffff; i != 0; i--)
++		if (!(readl(&p2wi->pm) & P2WI_PM_INIT_SEND))
++			break;
++	if (readl(&p2wi->pm) & P2WI_PM_INIT_SEND)
++		return -EFAULT;
++
++	return 0;
++}
++
++int p2wi_read(const u8 addr, u8 *data)
++{
++	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
++	int i, ret = 0;
++	u8 reg;
++
++	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
++	writel(P2WI_DATA_NUM_BYTES(1) |
++	       P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
++	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
++	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
++
++	for (i = 0xffffff; i != 0; i--) {
++	        reg = readl(&p2wi->status);
++	        if (reg & P2WI_STAT_TRANS_ERR) {
++	                ret = -EIO;
++	                break;
++                }
++		if (reg & P2WI_STAT_TRANS_DONE)
++			break;
++        }
++
++	if (i == 0)
++		ret = -ETIME;
++
++	*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
++	writel(reg, &p2wi->status); /* Clear status bits */
++	return ret;
++}
++
++int p2wi_write(const u8 addr, u8 data)
++{
++	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
++	int i, ret = 0;
++	u8 reg;
++
++	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
++	writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
++	writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
++	writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
++	writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
++
++	for (i = 0xffffff; i != 0; i--) {
++	        reg = readl(&p2wi->status);
++	        if (reg & P2WI_STAT_TRANS_ERR) {
++	                ret = -EIO;
++	                break;
++                }
++		if (reg & P2WI_STAT_TRANS_DONE)
++			break;
++        }
++
++	if (i == 0)
++		ret = -ETIME;
++
++	writel(reg, &p2wi->status); /* Clear status bits */
++	return ret;
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/pinmux.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,61 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -1842,18 +1574,12 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch
 +
 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 +{
-+	u32 cfg;
 +	u32 bank = GPIO_BANK(pin);
 +	u32 index = GPIO_CFG_INDEX(pin);
 +	u32 offset = GPIO_CFG_OFFSET(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
-+	cfg = readl(&pio->cfg[0] + index);
-+	cfg &= ~(0xf << offset);
-+	cfg |= val << offset;
-+
-+	writel(cfg, &pio->cfg[0] + index);
++	clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
 +
 +	return 0;
 +}
@@ -1864,8 +1590,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch
 +	u32 bank = GPIO_BANK(pin);
 +	u32 index = GPIO_CFG_INDEX(pin);
 +	u32 offset = GPIO_CFG_OFFSET(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
 +	cfg = readl(&pio->cfg[0] + index);
 +	cfg >>= offset;
@@ -1875,64 +1600,36 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch
 +
 +int sunxi_gpio_set_drv(u32 pin, u32 val)
 +{
-+	u32 drv;
 +	u32 bank = GPIO_BANK(pin);
 +	u32 index = GPIO_DRV_INDEX(pin);
 +	u32 offset = GPIO_DRV_OFFSET(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
-+
-+	drv = readl(&pio->drv[0] + index);
-+	drv &= ~(0x3 << offset);
-+	drv |= val << offset;
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
-+	writel(drv, &pio->drv[0] + index);
++	clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
 +
 +	return 0;
 +}
 +
 +int sunxi_gpio_set_pull(u32 pin, u32 val)
 +{
-+	u32 pull;
 +	u32 bank = GPIO_BANK(pin);
 +	u32 index = GPIO_PULL_INDEX(pin);
 +	u32 offset = GPIO_PULL_OFFSET(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
-+	pull = readl(&pio->pull[0] + index);
-+	pull &= ~(0x3 << offset);
-+	pull |= val << offset;
-+
-+	writel(pull, &pio->pull[0] + index);
++	clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
 +
 +	return 0;
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/postclk_init.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/postclk_init.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,36 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/postclk_init.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/postclk_init.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,20 @@
 +/*
 + * (C) Copyright 2013
 + * Carl van Schaik <carl@ok-labs.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -1948,138 +1645,49 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/postclk_init.c u-boot-sunx
 +#endif
 +	return 0;
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/psci.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/psci.S
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/psci.S	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/psci.S	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,124 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/prcm.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/prcm.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/prcm.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/prcm.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,35 @@
 +/*
-+ * Copyright (C) 2013 - ARM Ltd
-+ * Author: Marc Zyngier <marc.zyngier@arm.com>
++ * Sunxi A31 Power Management Unit
 + *
-+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
++ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ * http://linux-sunxi.org
 + *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
++ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
 + *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * (C) Copyright 2006-2013
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Berg Xing <bergxing@allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
-+#include <config.h>
-+#include <asm/psci.h>
++#include <common.h>
++#include <errno.h>
++#include <asm/io.h>
 +#include <asm/arch/cpu.h>
++#include <asm/arch/prcm.h>
++#include <asm/arch/sys_proto.h>
++
++/* APB0 clock gate and reset bit offsets are the same. */
++void prcm_apb0_enable(u32 flags)
++{
++	struct sunxi_prcm_reg *prcm =
++		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
++
++	/* open the clock for module */
++	setbits_le32(&prcm->apb0_gate, flags);
 +
-+	.pushsection ._secure.text, "ax"
-+
-+	.arch_extension sec
-+
-+#define	TEN_MS			(10 * CONFIG_SYS_CLK_FREQ / 1000)
-+
-+	@ r1 = target CPU
-+	@ r2 = target PC
-+.globl	psci_cpu_on
-+psci_cpu_on:
-+	adr	r0, _target_pc
-+	str	r2, [r0]
-+	dsb
-+
-+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-+
-+	@ CPU mask
-+	and	r1, r1, #3	@ only care about first cluster
-+	mov	r4, #1
-+	lsl	r4, r4, r1
-+
-+	adr	r6, _sunxi_cpu_entry
-+	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
-+
-+	@ Assert reset on target CPU
-+	mov	r6, #0
-+	lsl	r5, r1, #6	@ 64 bytes per CPU
-+	add	r5, r5, #0x40	@ Offset from base
-+	add	r5, r5, r0	@ CPU control block
-+	str	r6, [r5]	@ Reset CPU
-+
-+	@ l1 invalidate
-+	ldr	r6, [r0, #0x184]
-+	bic	r6, r6, r4
-+	str	r6, [r0, #0x184]
-+
-+	@ Lock CPU
-+	ldr	r6, [r0, #0x1e4]
-+	bic	r6, r6, r4
-+	str	r6, [r0, #0x1e4]
-+
-+	@ Release power clamp
-+	movw	r6, #0x1ff
-+	movt	r6, #0
-+1:	lsrs	r6, r6, #1
-+	str	r6, [r0, #0x1b0]
-+	bne	1b
-+
-+	@ Write CNTP_TVAL : 10ms @ 24MHz (240000 cycles)
-+	movw	r1, #(TEN_MS & 0xffff)
-+	movt	r1, #(TEN_MS >> 16)
-+	mcr	p15, 0, r1, c14, c2, 0
-+	isb
-+	@ Enable physical timer, mask interrupt
-+	mov	r1, #3
-+	mcr	p15, 0, r1, c14, c2, 1
-+	@ Poll physical timer until ISTATUS is on
-+1:	isb
-+	mrc	p15, 0, r1, c14, c2, 1
-+	ands	r1, r1, #4
-+	bne	1b
-+	@ Disable timer
-+	mov	r1, #0
-+	mcr	p15, 0, r1, c14, c2, 1
-+	isb
-+
-+	@ Clear power gating
-+	ldr	r6, [r0, #0x1b4]
-+	bic	r6, r6, #1
-+	str	r6, [r0, #0x1b4]
-+
-+	@ Deassert reset on target CPU
-+	mov	r6, #3
-+	str	r6, [r5]
-+
-+	@ Unlock CPU
-+	ldr	r6, [r0, #0x1e4]
-+	orr	r6, r6, r4
-+	str	r6, [r0, #0x1e4]
-+
-+	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-+	mov	pc, lr
-+
-+_target_pc:
-+	.word	0
-+
-+_sunxi_cpu_entry:
-+	@ Set SMP bit
-+	mrc	p15, 0, r0, c1, c0, 1
-+	orr	r0, r0, #0x40
-+	mcr	p15, 0, r0, c1, c0, 1
-+	isb
-+
-+	bl	_nonsec_init
-+
-+	adr	r0, _target_pc
-+	ldr	r0, [r0]
-+	b	_do_nonsec_entry
-+
-+	.popsection
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,48 @@
++	/* deassert reset for module */
++	setbits_le32(&prcm->apb0_reset, flags);
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/secondary_init.S	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,31 @@
 +/*
 + * A lowlevel_init function that sets up the stack to call a C function to
 + * perform further init.
@@ -2087,25 +1695,8 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-su
 + * (C) Copyright 2013
 + * Carl van Schaik <carl@ok-labs.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +#include <asm-offsets.h>
 +#include <config.h>
 +#include <linux/linkage.h>
@@ -2128,31 +1719,15 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-su
 +	bl	secondary_start
 +ENDPROC(secondary_init)
 +
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/smp.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/smp.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c	2014-03-05 23:14:47.128100511 +0100
-@@ -0,0 +1,96 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/smp.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/smp.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,80 @@
 +/*
 + * (C) Copyright 2013
 + * Carl van Schaik <carl@ok-labs.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -2228,37 +1803,21 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/smp.c u-boot-sunxi/arch/ar
 +		printf("Secondary CPU%d power-on\n", i);
 +	}
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/start.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/start.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c	2014-03-05 23:14:47.128100511 +0100
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/start.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/start.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c	2014-09-06 16:58:35.317953141 +0200
 @@ -0,0 +1 @@
 +/* Intentionally empty. Only needed to get FEL SPL link line right */
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,120 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/timer.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,113 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -2283,18 +1842,29 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/
 +
 +#define TIMER_NUM		0	/* we use timer 0 */
 +
-+static struct sunxi_timer *timer_base =
-+	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
++/* read the 32-bit timer */
++static ulong read_timer(void)
++{
++	struct sunxi_timer_reg *timers =
++		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
++	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
 +
-+/* macro to read the 32 bit timer: since it decrements, we invert read value */
-+#define READ_TIMER() (~readl(&timer_base->val))
++	/*
++	 * The hardware timer counts down, therefore we invert to
++	 * produce an incrementing timer.
++	 */
++	return ~readl(&timer->val);
++}
 +
 +/* init timer register */
 +int timer_init(void)
 +{
-+	writel(TIMER_LOAD_VAL, &timer_base->inter);
++	struct sunxi_timer_reg *timers =
++		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
++	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
++	writel(TIMER_LOAD_VAL, &timer->inter);
 +	writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
-+	       &timer_base->ctl);
++	       &timer->ctl);
 +
 +	return 0;
 +}
@@ -2308,7 +1878,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/
 +ulong get_timer_masked(void)
 +{
 +	/* current tick value */
-+	ulong now = TICKS_TO_HZ(READ_TIMER());
++	ulong now = TICKS_TO_HZ(read_timer());
 +
 +	if (now >= gd->arch.lastinc)	/* normal (non rollover) */
 +		gd->arch.tbl += (now - gd->arch.lastinc);
@@ -2326,10 +1896,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/
 +void __udelay(unsigned long usec)
 +{
 +	long tmo = USEC_TO_COUNT(usec);
-+	ulong now, last = READ_TIMER();
++	ulong now, last = read_timer();
 +
 +	while (tmo > 0) {
-+		now = READ_TIMER();
++		now = read_timer();
 +		if (now > last)	/* normal (non rollover) */
 +			tmo -= now - last;
 +		else		/* rollover */
@@ -2353,144 +1923,93 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/
 + */
 +ulong get_tbclk(void)
 +{
-+	ulong tbclk;
-+	tbclk = CONFIG_SYS_HZ;
-+	return tbclk;
++	return CONFIG_SYS_HZ;
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,63 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,77 @@
 +/*
-+ * (C) Copyright 2013 ARM Ltd
-+ * Marc Zyngier <marc.zyngier@arm.com>
-+ *
-+ * Based on sunxi/u-boot-spl.lds:
-+ *
-+ * (C) Copyright 2012
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ * Tom Cubie <tangliang@allwinnertech.com>
-+ *
-+ * Based on omap-common/u-boot-spl.lds:
-+ *
-+ * (C) Copyright 2002
-+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-+ *
-+ * (C) Copyright 2010
-+ * Texas Instruments, <www.ti.com>
-+ *	Aneesh V <aneesh@ti.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * (C) Copyright 2013
++ * Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
-+MEMORY { sram : ORIGIN = CONFIG_ARMV7_PSCI_BASE, LENGTH = 0x1000 }
 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 +OUTPUT_ARCH(arm)
-+ENTRY(_start)
++ENTRY(s_init)
 +SECTIONS
 +{
-+	.text      :
++	. = 0x00002000;
++
++	. = ALIGN(4);
++	.text :
 +	{
-+		_start = .;
++		*(.text.s_init)
 +		*(.text*)
-+	} > sram
++	}
++
++	. = ALIGN(4);
++	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
++
++	. = ALIGN(4);
++	.data : {
++		*(.data*)
++	}
 +
 +	. = ALIGN(4);
-+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > sram
++	. = .;
 +
 +	. = ALIGN(4);
-+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } > sram
++	.rel.dyn : {
++		__rel_dyn_start = .;
++		*(.rel*)
++		__rel_dyn_end = .;
++	}
++
++	.dynsym : {
++		__dynsym_start = .;
++		*(.dynsym)
++	}
 +
 +	. = ALIGN(4);
++	.note.gnu.build-id :
++	{
++		*(.note.gnu.build-id)
++	}
 +	_end = .;
 +
-+	/DISCARD/ : {
++	. = ALIGN(4096);
++	.mmutable : {
++		*(.mmutable)
++	}
++
++	.bss_start __rel_dyn_start (OVERLAY) : {
++		KEEP(*(.__bss_start));
++		__bss_base = .;
++	}
++
++	.bss __bss_base (OVERLAY) : {
 +		*(.bss*)
++		. = ALIGN(4);
++		__bss_limit = .;
 +	}
-+}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,59 @@
-+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-+OUTPUT_ARCH(arm)
-+ENTRY(s_init)
-+SECTIONS
-+{
-+ . = 0x00002000;
-+ . = ALIGN(4);
-+ .text :
-+ {
-+  *(.text.s_init)
-+  *(.text*)
-+ }
-+ . = ALIGN(4);
-+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-+ . = ALIGN(4);
-+ .data : {
-+  *(.data*)
-+ }
-+ . = ALIGN(4);
-+ . = .;
-+ . = ALIGN(4);
-+ .rel.dyn : {
-+  __rel_dyn_start = .;
-+  *(.rel*)
-+  __rel_dyn_end = .;
-+ }
-+ .dynsym : {
-+  __dynsym_start = .;
-+  *(.dynsym)
-+ }
-+ . = ALIGN(4);
-+ .note.gnu.build-id :
-+ {
-+	*(.note.gnu.build-id)
-+ }
-+ _end = .;
-+ . = ALIGN(4096);
-+ .mmutable : {
-+  *(.mmutable)
-+ }
-+ .bss_start __rel_dyn_start (OVERLAY) : {
-+  KEEP(*(.__bss_start));
-+  __bss_base = .;
-+ }
-+ .bss __bss_base (OVERLAY) : {
-+  *(.bss*)
-+   . = ALIGN(4);
-+   __bss_limit = .;
-+ }
-+ .bss_end __bss_limit (OVERLAY) : {
-+  KEEP(*(.__bss_end));
-+ }
-+ /DISCARD/ : { *(.dynstr*) }
-+ /DISCARD/ : { *(.dynamic*) }
-+ /DISCARD/ : { *(.plt*) }
-+ /DISCARD/ : { *(.interp*) }
-+ /DISCARD/ : { *(.gnu*) }
-+ /DISCARD/ : { *(.note*) }
-+}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,69 @@
++
++	.bss_end __bss_limit (OVERLAY) : {
++		KEEP(*(.__bss_end));
++	}
++
++	/DISCARD/ : { *(.dynstr*) }
++	/DISCARD/ : { *(.dynamic*) }
++	/DISCARD/ : { *(.plt*) }
++	/DISCARD/ : { *(.interp*) }
++	/DISCARD/ : { *(.gnu*) }
++	/DISCARD/ : { *(.note*) }
++}
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,52 @@
 +/*
 + * (C) Copyright 2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -2505,25 +2024,8 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunx
 + * Texas Instruments, <www.ti.com>
 + *	Aneesh V <aneesh@ti.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
 +		LENGTH = CONFIG_SPL_MAX_SIZE }
 +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
@@ -2560,29 +2062,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunx
 +		__bss_end = .;
 +	} > .sdram
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/watchdog.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,96 @@
+diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c
+--- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/watchdog.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c	2014-09-06 16:58:35.317953141 +0200
+@@ -0,0 +1,83 @@
 +/*
 + * Watchdog driver for the Allwinner sunxi platform.
 + * Copyright (C) 2013  Oliver Schinagl <oliver@schinagl.nl>
 + * http://www.linux-sunxi.org/
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-+ * MA  02110-1301, USA.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <asm/io.h>
@@ -2660,278 +2149,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/watchdog.c u-boot-sunxi/ar
 +	watchdog_set(WDT_OFF); /* no timeout */
 +#endif
 +}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-dt.c u-boot-sunxi/arch/arm/cpu/armv7/virt-dt.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-dt.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/virt-dt.c	2014-03-05 23:14:47.132100458 +0100
-@@ -0,0 +1,100 @@
-+/*
-+ * Copyright (C) 2013 - ARM Ltd
-+ * Author: Marc Zyngier <marc.zyngier@arm.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <common.h>
-+#include <stdio_dev.h>
-+#include <linux/ctype.h>
-+#include <linux/types.h>
-+#include <asm/global_data.h>
-+#include <libfdt.h>
-+#include <fdt_support.h>
-+#include <asm/armv7.h>
-+#include <asm/psci.h>
-+
-+static int fdt_psci(void *fdt)
-+{
-+#ifdef CONFIG_ARMV7_PSCI
-+	int nodeoff;
-+	int tmp;
-+
-+	nodeoff = fdt_path_offset(fdt, "/cpus");
-+	if (nodeoff < 0) {
-+		printf("couldn't find /cpus\n");
-+		return nodeoff;
-+	}
-+
-+	/* add 'enable-method = "psci"' to each cpu node */
-+	for (tmp = fdt_first_subnode(fdt, nodeoff);
-+	     tmp >= 0;
-+	     tmp = fdt_next_subnode(fdt, tmp)) {
-+		const struct fdt_property *prop;
-+		int len;
-+
-+		prop = fdt_get_property(fdt, tmp, "device_type", &len);
-+		if (!prop)
-+			continue;
-+		if (len < 4)
-+			continue;
-+		if (strcmp(prop->data, "cpu"))
-+			continue;
-+
-+		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
-+	}
-+
-+	nodeoff = fdt_path_offset(fdt, "/psci");
-+	if (nodeoff < 0) {
-+		nodeoff = fdt_path_offset(fdt, "/");
-+		if (nodeoff < 0)
-+			return nodeoff;
-+
-+		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
-+		if (nodeoff < 0)
-+			return nodeoff;
-+	}
-+
-+	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
-+	if (tmp)
-+		return tmp;
-+	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
-+	if (tmp)
-+		return tmp;
-+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
-+	if (tmp)
-+		return tmp;
-+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
-+	if (tmp)
-+		return tmp;
-+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
-+	if (tmp)
-+		return tmp;
-+	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
-+	if (tmp)
-+		return tmp;
-+#endif
-+	return 0;
-+}
-+
-+int armv7_update_dt(void *fdt)
-+{
-+#ifndef CONFIG_ARMV7_SECURE_BASE
-+	/* secure code lives in RAM, keep it alive */
-+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
-+			__secure_end - __secure_start);
-+#endif
-+
-+	return fdt_psci(fdt);
-+}
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-v7.c u-boot-sunxi/arch/arm/cpu/armv7/virt-v7.c
---- u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-v7.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/armv7/virt-v7.c	2014-03-05 23:14:47.132100458 +0100
-@@ -13,17 +13,10 @@
- #include <asm/armv7.h>
- #include <asm/gic.h>
- #include <asm/io.h>
-+#include <asm/secure.h>
- 
- unsigned long gic_dist_addr;
- 
--static unsigned int read_cpsr(void)
--{
--	unsigned int reg;
--
--	asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
--	return reg;
--}
--
- static unsigned int read_id_pfr1(void)
- {
- 	unsigned int reg;
-@@ -72,6 +65,18 @@
- #endif
- }
- 
-+static void relocate_secure_section(void)
-+{
-+#ifdef CONFIG_ARMV7_SECURE_BASE
-+	size_t sz = __secure_end - __secure_start;
-+
-+	memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
-+	flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
-+			   CONFIG_ARMV7_SECURE_BASE + sz + 1);
-+	invalidate_icache_all();
-+#endif
-+}
-+
- static void kick_secondary_cpus_gic(unsigned long gicdaddr)
- {
- 	/* kick all CPUs (except this one) by writing to GICD_SGIR */
-@@ -83,35 +88,7 @@
- 	kick_secondary_cpus_gic(gic_dist_addr);
- }
- 
--int armv7_switch_hyp(void)
--{
--	unsigned int reg;
--
--	/* check whether we are in HYP mode already */
--	if ((read_cpsr() & 0x1f) == 0x1a) {
--		debug("CPU already in HYP mode\n");
--		return 0;
--	}
--
--	/* check whether the CPU supports the virtualization extensions */
--	reg = read_id_pfr1();
--	if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
--		printf("HYP mode: Virtualization extensions not implemented.\n");
--		return -1;
--	}
--
--	/* call the HYP switching code on this CPU also */
--	_switch_to_hyp();
--
--	if ((read_cpsr() & 0x1F) != 0x1a) {
--		printf("HYP mode: switch not successful.\n");
--		return -1;
--	}
--
--	return 0;
--}
--
--int armv7_switch_nonsec(void)
-+int armv7_init_nonsec(void)
- {
- 	unsigned int reg;
- 	unsigned itlinesnr, i;
-@@ -147,11 +124,13 @@
- 	for (i = 1; i <= itlinesnr; i++)
- 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
- 
--	smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
-+#ifndef CONFIG_ARMV7_PSCI
-+	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
- 	smp_kick_all_cpus();
-+#endif
- 
- 	/* call the non-sec switching code on this CPU also */
--	_nonsec_init();
--
-+	relocate_secure_section();
-+	secure_ram_addr(_nonsec_init)();
- 	return 0;
- }
-diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/u-boot.lds u-boot-sunxi/arch/arm/cpu/u-boot.lds
---- u-boot-2014.01-rc1/arch/arm/cpu/u-boot.lds	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/cpu/u-boot.lds	2014-03-05 23:14:47.136100405 +0100
-@@ -7,6 +7,8 @@
-  * SPDX-License-Identifier:	GPL-2.0+
-  */
- 
-+#include <config.h>
-+
- OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
- OUTPUT_ARCH(arm)
- ENTRY(_start)
-@@ -22,6 +24,34 @@
- 		*(.text*)
- 	}
- 
-+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
-+
-+#ifndef CONFIG_ARMV7_SECURE_BASE
-+#define CONFIG_ARMV7_SECURE_BASE
-+#endif
-+
-+	.__secure_start : {
-+		. = ALIGN(0x1000);
-+		*(.__secure_start)
-+	}
-+
-+	.secure_text CONFIG_ARMV7_SECURE_BASE :
-+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
-+	{
-+		*(._secure.text)
-+	}
-+
-+	. = LOADADDR(.__secure_start) +
-+		SIZEOF(.__secure_start) +
-+		SIZEOF(.secure_text);
-+
-+	__secure_end_lma = .;
-+	.__secure_end : AT(__secure_end_lma) {
-+		*(.__secure_end)
-+		LONG(0x1d1071c);	/* Must output something to reset LMA */
-+	}
-+#endif
-+
- 	. = ALIGN(4);
- 	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
- 
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,375 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,33 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_CLOCK_H
@@ -2943,138 +2170,38 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunx
 +#define CLK_GATE_CLOSE			0x0
 +
 +/* clock control module regs definition */
-+#if defined(CONFIG_SUN6I)
-+struct sunxi_ccm_reg {
-+	u32 pll1_cfg;		/* 0x00 pll1 control */
-+	u32 reserved0;
-+	u32 pll2_cfg;		/* 0x08 pll2 control */
-+	u32 reserved1;
-+	u32 pll3_cfg;		/* 0x10 pll3 control */
-+	u32 reserved2;
-+	u32 pll4_cfg;		/* 0x18 pll4 control */
-+	u32 reserved3;
-+	u32 pll5_cfg;		/* 0x20 pll5 control */
-+	u32 reserved4;
-+	u32 pll6_cfg;		/* 0x28 pll6 control */
-+	u32 reserved5;
-+	u32 pll7_cfg;		/* 0x30 pll7 control */
-+	u32 reserved6;
-+	u32 pll8_cfg;		/* 0x38 pll8 control */
-+	u32 reserved7;
-+	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
-+	u32 pll9_cfg;		/* 0x44 pll9 control */
-+	u32 pll10_cfg;		/* 0x48 pll10 control */
-+	u32 reserved8;
-+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
-+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
-+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
-+	u32 axi_gate;		/* 0x5c axi module clock gating */
-+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
-+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
-+	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
-+	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
-+	u32 reserved9[4];
-+	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
-+	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
-+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
-+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
-+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
-+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
-+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
-+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
-+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
-+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
-+	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
-+	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
-+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
-+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
-+	u32 reserved10[2];
-+	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
-+	u32 reserved11[2];
-+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
-+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
-+	u32 reserved12[7];
-+	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
-+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
-+	u32 reserved13[2];
-+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
-+	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
-+	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
-+	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
-+	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
-+	u32 mp_clk_cfg;		/* 0x114 MP module clock */
-+	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
-+	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
-+	u32 reserved14[3];
-+	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
-+	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
-+	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
-+	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
-+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
-+	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
-+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
-+	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
-+	u32 reserved15;
-+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
-+	u32 ps_clk_cfg;		/* 0x154 PS module clock */
-+	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
-+	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
-+	u32 mbus1_clk_cfg;	/* 0x160 MBUS0 module clock */
-+	u32 reserved16;
-+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
-+	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
-+	u32 reserved17[4];
-+	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
-+	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
-+	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
-+	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
-+	u32 reserved18[4];
-+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
-+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
-+	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
-+	u32 reserved19[21];
-+	u32 pll_lock;		/* 0x200 PLL Lock Time */
-+	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
-+	u32 reserved20[6];
-+	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
-+	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
-+	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
-+	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
-+	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
-+	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
-+	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
-+	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
-+	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
-+	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
-+	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
-+	u32 reserved21[13];
-+	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
-+	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
-+	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
-+	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
-+	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
-+	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
-+	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
-+	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
-+	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
-+	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
-+	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
-+	u32 reserved22[5];
-+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
-+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
-+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
-+	u32 reserved23;
-+	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
-+	u32 reserved24;
-+	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
-+};
++#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
++#include <asm/arch/clock_sun6i.h>
++#else
++#include <asm/arch/clock_sun4i.h>
++#endif
 +
-+/* apb2 bit field */
-+#define APB2_CLK_SRC_OSC24M		1
-+#define APB2_FACTOR_M			0
-+#define APB2_FACTOR_N			0
++#ifndef __ASSEMBLY__
++int clock_init(void);
++int clock_twi_onoff(int port, int state);
++void clock_set_pll1(unsigned int hz);
++unsigned int clock_get_pll6(void);
++void clock_init_safe(void);
++void clock_init_uart(void);
++#endif
 +
-+#else
++#endif /* _SUNXI_CLOCK_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun4i.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun4i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun4i.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,256 @@
++/*
++ * sun4i, sun5i and sun7i clock register definitions
++ *
++ * (C) Copyright 2007-2011
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef _SUNXI_CLOCK_SUN4I_H
++#define _SUNXI_CLOCK_SUN4I_H
 +
 +struct sunxi_ccm_reg {
 +	u32 pll1_cfg;		/* 0x00 pll1 control */
@@ -3156,29 +2283,60 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunx
 +};
 +
 +/* apb1 bit field */
-+#define APB1_CLK_SRC_OSC24M		0
-+#define APB1_FACTOR_M			0
-+#define APB1_FACTOR_N			0
++#define APB1_CLK_SRC_OSC24M		(0x0 << 24)
++#define APB1_CLK_SRC_PLL6		(0x1 << 24)
++#define APB1_CLK_SRC_LOSC		(0x2 << 24)
++#define APB1_CLK_SRC_MASK		(0x3 << 24)
++#define APB1_CLK_RATE_N_1		(0x0 << 16)
++#define APB1_CLK_RATE_N_2		(0x1 << 16)
++#define APB1_CLK_RATE_N_4		(0x2 << 16)
++#define APB1_CLK_RATE_N_8		(0x3 << 16)
++#define APB1_CLK_RATE_N_MASK		(3 << 16)
++#define APB1_CLK_RATE_M(m)		(((m)-1) << 0)
++#define APB1_CLK_RATE_M_MASK            (0x1f << 0)
++
++/* apb1 gate field */
++#define APB1_GATE_UART_SHIFT	(16)
++#define APB1_GATE_UART_MASK		(0xff << APB1_GATE_UART_SHIFT)
++#define APB1_GATE_TWI_SHIFT	(0)
++#define APB1_GATE_TWI_MASK		(0xf << APB1_GATE_TWI_SHIFT)
 +
 +/* clock divide */
-+#define CPU_CLK_SRC_OSC24M		1
-+#define CPU_CLK_SRC_PLL1		2
++#define AXI_DIV_SHIFT		(0)
 +#define AXI_DIV_1			0
 +#define AXI_DIV_2			1
 +#define AXI_DIV_3			2
 +#define AXI_DIV_4			3
++#define AHB_DIV_SHIFT		(4)
 +#define AHB_DIV_1			0
 +#define AHB_DIV_2			1
 +#define AHB_DIV_4			2
 +#define AHB_DIV_8			3
++#define APB0_DIV_SHIFT		(8)
 +#define APB0_DIV_1			0
 +#define APB0_DIV_2			1
 +#define APB0_DIV_4			2
 +#define APB0_DIV_8			3
++#define CPU_CLK_SRC_SHIFT	(16)
++#define CPU_CLK_SRC_OSC24M		1
++#define CPU_CLK_SRC_PLL1		2
 +
-+#ifdef CONFIG_SUN5I
-+#define AHB_CLK_SRC_AXI			0
-+#endif
++#define CCM_PLL1_CFG_ENABLE_SHIFT		31
++#define CCM_PLL1_CFG_VCO_RST_SHIFT		30
++#define CCM_PLL1_CFG_VCO_BIAS_SHIFT		26
++#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT		25
++#define CCM_PLL1_CFG_BIAS_CUR_SHIFT		20
++#define CCM_PLL1_CFG_DIVP_SHIFT			16
++#define CCM_PLL1_CFG_LCK_TMR_SHIFT		13
++#define CCM_PLL1_CFG_FACTOR_N_SHIFT		8
++#define CCM_PLL1_CFG_FACTOR_K_SHIFT		4
++#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT	3
++#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT	2
++#define CCM_PLL1_CFG_FACTOR_M_SHIFT		0
++
++#define PLL1_CFG_DEFAULT	0xa1005000
++
++#define PLL6_CFG_DEFAULT	0xa1009911
 +
 +/* nand clock */
 +#define NAND_CLK_SRC_OSC24		0
@@ -3208,6 +2366,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunx
 +#define AHB_GATE_OFFSET_MMC2		10
 +#define AHB_GATE_OFFSET_MMC1		9
 +#define AHB_GATE_OFFSET_MMC0		8
++#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
 +#define AHB_GATE_OFFSET_BIST		7
 +#define AHB_GATE_OFFSET_DMA		6
 +#define AHB_GATE_OFFSET_SS		5
@@ -3251,6 +2410,11 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunx
 +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
 +#define CCM_PLL5_CTRL_EN (0x1 << 31)
 +
++#define CCM_PLL6_CTRL_N_SHIFT	8
++#define CCM_PLL6_CTRL_N_MASK	(0x1f << CCM_PLL6_CTRL_N_SHIFT)
++#define CCM_PLL6_CTRL_K_SHIFT	4
++#define CCM_PLL6_CTRL_K_MASK	(0x3 << CCM_PLL6_CTRL_K_SHIFT)
++
 +#define CCM_GPS_CTRL_RESET (0x1 << 0)
 +#define CCM_GPS_CTRL_GATE (0x1 << 1)
 +
@@ -3269,49 +2433,239 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunx
 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 +#define CCM_MBUS_CTRL_GATE (0x1 << 31)
 +
++#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
++#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
++#define CCM_MMC_CTRL_PLL5   (0x2 << 24)
++
++#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
++
 +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
 +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
 +
-+#endif /* CONFIG_SUN6I */
++#endif /* _SUNXI_CLOCK_SUN4I_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun6i.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun6i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun6i.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,205 @@
++/*
++ * sun6i clock register definitions
++ *
++ * (C) Copyright 2007-2011
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
 +
-+#ifndef __ASSEMBLY__
-+int clock_init(void);
-+int clock_twi_onoff(int port, int state);
-+void clock_set_pll1(int mhz);
-+unsigned int clock_get_pll5(void);
-+#endif
++#ifndef _SUNXI_CLOCK_SUN6I_H
++#define _SUNXI_CLOCK_SUN6I_H
 +
-+#endif /* _SUNXI_CLOCK_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpucfg.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpucfg.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,71 @@
++struct sunxi_ccm_reg {
++	u32 pll1_cfg;		/* 0x00 pll1 control */
++	u32 reserved0;
++	u32 pll2_cfg;		/* 0x08 pll2 control */
++	u32 reserved1;
++	u32 pll3_cfg;		/* 0x10 pll3 control */
++	u32 reserved2;
++	u32 pll4_cfg;		/* 0x18 pll4 control */
++	u32 reserved3;
++	u32 pll5_cfg;		/* 0x20 pll5 control */
++	u32 reserved4;
++	u32 pll6_cfg;		/* 0x28 pll6 control */
++	u32 reserved5;
++	u32 pll7_cfg;		/* 0x30 pll7 control */
++	u32 reserved6;
++	u32 pll8_cfg;		/* 0x38 pll8 control */
++	u32 reserved7;
++	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
++	u32 pll9_cfg;		/* 0x44 pll9 control */
++	u32 pll10_cfg;		/* 0x48 pll10 control */
++	u32 reserved8;
++	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
++	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
++	u32 apb2_div;		/* 0x58 APB2 divide ratio */
++	u32 axi_gate;		/* 0x5c axi module clock gating */
++	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
++	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
++	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
++	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
++	u32 reserved9[4];
++	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
++	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
++	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
++	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
++	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
++	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
++	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
++	u32 ss_clk_cfg;		/* 0x9c security system clock control */
++	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
++	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
++	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
++	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
++	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
++	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
++	u32 reserved10[2];
++	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
++	u32 reserved11[2];
++	u32 usb_clk_cfg;	/* 0xcc USB clock control */
++	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
++	u32 reserved12[7];
++	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
++	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
++	u32 reserved13[2];
++	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
++	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
++	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
++	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
++	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
++	u32 mp_clk_cfg;		/* 0x114 MP module clock */
++	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
++	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
++	u32 reserved14[3];
++	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
++	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
++	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
++	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
++	u32 ve_clk_cfg;		/* 0x13c VE module clock */
++	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
++	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
++	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
++	u32 reserved15;
++	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
++	u32 ps_clk_cfg;		/* 0x154 PS module clock */
++	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
++	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
++	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
++	u32 reserved16;
++	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
++	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
++	u32 reserved17[4];
++	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
++	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
++	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
++	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
++	u32 reserved18[4];
++	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
++	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
++	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
++	u32 reserved19[21];
++	u32 pll_lock;		/* 0x200 PLL Lock Time */
++	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
++	u32 reserved20[6];
++	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
++	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
++	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
++	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
++	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
++	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
++	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
++	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
++	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
++	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
++	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
++	u32 reserved21[13];
++	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
++	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
++	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
++	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
++	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
++	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
++	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
++	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
++	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
++	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
++	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
++	u32 reserved22[5];
++	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
++	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
++	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
++	u32 reserved23;
++	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
++	u32 reserved24;
++	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
++};
++
++/* apb2 bit field */
++#define APB2_CLK_SRC_LOSC		(0x0 << 24)
++#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
++#define APB2_CLK_SRC_PLL6		(0x2 << 24)
++#define APB2_CLK_SRC_MASK		(0x3 << 24)
++#define APB2_CLK_RATE_N_1		(0x0 << 16)
++#define APB2_CLK_RATE_N_2		(0x1 << 16)
++#define APB2_CLK_RATE_N_4		(0x2 << 16)
++#define APB2_CLK_RATE_N_8		(0x3 << 16)
++#define APB2_CLK_RATE_N_MASK		(3 << 16)
++#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
++#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
++
++/* apb2 gate field */
++#define APB2_GATE_UART_SHIFT	(16)
++#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
++#define APB2_GATE_TWI_SHIFT	(0)
++#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
++
++/* cpu_axi_cfg bits */
++#define AXI_DIV_SHIFT			0
++#define ATB_DIV_SHIFT			8
++#define CPU_CLK_SRC_SHIFT		16
++
++#define AXI_DIV_1			0
++#define AXI_DIV_2			1
++#define AXI_DIV_3			2
++#define AXI_DIV_4			3
++#define ATB_DIV_1			0
++#define ATB_DIV_2			1
++#define ATB_DIV_4			2
++#define CPU_CLK_SRC_OSC24M		1
++#define CPU_CLK_SRC_PLL1		2
++
++#define PLL1_CFG_DEFAULT		0x90011b21
++
++#define PLL6_CFG_DEFAULT		0x90041811
++
++#define CCM_PLL6_CTRL_N_SHIFT		8
++#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
++#define CCM_PLL6_CTRL_K_SHIFT		4
++#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
++
++#define AHB_GATE_OFFSET_MMC3		11
++#define AHB_GATE_OFFSET_MMC2		10
++#define AHB_GATE_OFFSET_MMC1		9
++#define AHB_GATE_OFFSET_MMC0		8
++#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
++
++#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
++#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
++
++#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
++
++#define AHB_RESET_OFFSET_MMC3		11
++#define AHB_RESET_OFFSET_MMC2		10
++#define AHB_RESET_OFFSET_MMC1		9
++#define AHB_RESET_OFFSET_MMC0		8
++#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
++
++/* apb2 reset */
++#define APB2_RESET_UART_SHIFT		(16)
++#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
++#define APB2_RESET_TWI_SHIFT		(0)
++#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
++
++#endif /* _SUNXI_CLOCK_SUN6I_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpucfg.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpucfg.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,55 @@
 +/*
 + * (C) Copyright 2013
 + * Carl van Schaik <carl@ok-labs.com>
 + *
 + * CPU configuration registers for the sun7i (A20).
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_CPUCFG_H_
@@ -3360,32 +2714,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpucfg.h u-boot-sun
 +#endif /* __ASSEMBLY__ */
 +
 +#endif /* _SUNXI_CPUCFG_H_ */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,147 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpu.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,141 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_CPU_H
@@ -3477,6 +2815,11 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/
 +#define SUNXI_MALI400_BASE		0x01c40000
 +#define SUNXI_GMAC_BASE			0x01c50000
 +
++#define SUNXI_DRAM_COM_BASE		0x01c62000
++#define SUNXI_DRAM_CTL_BASE		0x01c63000
++#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
++#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
++
 +/* module sram */
 +#define SUNXI_SRAM_C_BASE		0x01d00000
 +
@@ -3487,6 +2830,11 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/
 +#define SUNXI_MP_BASE			0x01e80000
 +#define SUNXI_AVG_BASE			0x01ea0000
 +
++#define SUNXI_PRCM_BASE			0x01f01400
++#define SUNXI_R_UART_BASE		0x01f02800
++#define SUNXI_R_PIO_BASE		0x01f02c00
++#define SUNXI_P2WI_BASE			0x01f03400
++
 +/* CoreSight Debug Module */
 +#define SUNXI_CSDM_BASE			0x3f500000
 +
@@ -3507,14 +2855,14 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/
 +};
 +
 +void sunxi_board_init(void);
-+extern void sunxi_reset(void);
++void sunxi_reset(void);
 +#endif /* __ASSEMBLY__ */
 +
 +#endif /* _CPU_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,191 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/dram.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,179 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -3523,23 +2871,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi
 + *
 + * Sunxi platform dram register definition.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_DRAM_H
@@ -3667,6 +2999,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi
 +
 +#define DRAM_CSR_FAILED (0x1 << 20)
 +
++#define DRAM_DRR_TRFC(n) ((n) & 0xff)
++#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
++#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
++
 +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
 +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
 +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
@@ -3706,10 +3042,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi
 +unsigned long dramc_init(struct dram_para *para);
 +
 +#endif /* _SUNXI_DRAM_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,74 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/early_print.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/early_print.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,58 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -3717,23 +3053,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h u-boo
 + *
 + * Early uart print for debugging.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_EARLY_PRINT_H
@@ -3784,38 +3104,23 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h u-boo
 +#endif /* __ASSEMBLY__ */
 +
 +#endif /* _SUNXI_EARLY_PRINT_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,179 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/gpio.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,174 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_GPIO_H
 +#define _SUNXI_GPIO_H
 +
 +#include <linux/types.h>
++#include <asm/arch/cpu.h>
 +
 +/*
 + * sunxi has 9 banks of gpio, they are:
@@ -3833,6 +3138,15 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +#define SUNXI_GPIO_G	6
 +#define SUNXI_GPIO_H	7
 +#define SUNXI_GPIO_I	8
++#define SUNXI_GPIO_BANKS 9
++
++/*
++ * sun6i has atleast 1 additional bank, note banks J K don't exist!
++ * PL0 - PL1 at the very least is known.
++ *
++ * Note this bank is at a different register offset!
++ */
++#define SUNXI_GPIO_L	9
 +
 +struct sunxi_gpio {
 +	u32 cfg[4];
@@ -3850,11 +3164,15 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +};
 +
 +struct sunxi_gpio_reg {
-+	struct sunxi_gpio gpio_bank[9];
++	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
 +	u8 res[0xbc];
 +	struct sunxi_gpio_int gpio_int;
 +};
 +
++#define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_BANKS) ? \
++	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
++	(struct sunxi_gpio *)SUNXI_R_PIO_BASE)
++
 +#define GPIO_BANK(pin)		((pin) >> 5)
 +#define GPIO_NUM(pin)		((pin) & 0x1f)
 +
@@ -3877,6 +3195,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +#define SUNXI_GPIO_G_NR		32
 +#define SUNXI_GPIO_H_NR		32
 +#define SUNXI_GPIO_I_NR		32
++#define SUNXI_GPIO_L_NR		32
 +
 +#define SUNXI_GPIO_NEXT(__gpio) \
 +	((__gpio##_START) + (__gpio##_NR) + 0)
@@ -3891,6 +3210,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
 +	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
 +	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
++	SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),
 +};
 +
 +/* SUNXI GPIO number definitions */
@@ -3903,25 +3223,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +#define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
 +#define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
 +#define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
++#define SUNXI_GPL(_nr)	(SUNXI_GPIO_L_START + (_nr))
 +
 +/* GPIO pin function config */
 +#define SUNXI_GPIO_INPUT	0
 +#define SUNXI_GPIO_OUTPUT	1
 +
-+#define SUNXI_GPA0_ERXD3	2
-+#define SUNXI_GPA0_SPI1_CS0	3
-+#define SUNXI_GPA0_UART2_RTS	4
-+
-+#define SUNXI_GPA1_ERXD2	2
-+#define SUNXI_GPA1_SPI1_CLK	3
-+#define SUNXI_GPA1_UART2_CTS	4
++#define SUNXI_GPA0_EMAC		2
++#define SUN7I_GPA0_GMAC		5
 +
-+#define SUNXI_GPA2_ERXD1	2
-+#define SUNXI_GPA2_SPI1_MOSI	3
-+#define SUNXI_GPA2_UART2_TX	4
-+
-+#define SUNXI_GPA10_UART1_TX	4
-+#define SUNXI_GPA11_UART1_RX	4
++#define SUNXI_GPB0_TWI0		2
 +
 +#define SUN4I_GPB22_UART0_TX	2
 +#define SUN4I_GPB23_UART0_RX	2
@@ -3929,387 +3240,592 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi
 +#define SUN5I_GPB19_UART0_TX	2
 +#define SUN5I_GPB20_UART0_RX	2
 +
-+#define SUN5I_GPG3_UART0_TX	4
-+#define SUN5I_GPG4_UART0_RX	4
++#define SUN5I_GPG3_UART1_TX	4
++#define SUN5I_GPG4_UART1_RX	4
 +
-+#define SUNXI_GPC2_NCLE		2
-+#define SUNXI_GPC2_SPI0_CLK	3
++#define SUNXI_GPC6_SDC2		3
 +
-+#define SUNXI_GPC6_NRB0		2
-+#define SUNXI_GPC6_SDC2_CMD	3
++#define SUNXI_GPF0_SDC0		2
 +
-+#define SUNXI_GPC7_NRB1		2
-+#define SUNXI_GPC7_SDC2_CLK	3
++#define SUNXI_GPF2_SDC0		2
 +
-+#define SUNXI_GPC8_NDQ0		2
-+#define SUNXI_GPC8_SDC2_D0	3
++#ifdef CONFIG_SUN8I
++#define SUNXI_GPF2_UART0_TX	3
++#define SUNXI_GPF4_UART0_RX	3
++#else
++#define SUNXI_GPF2_UART0_TX	4
++#define SUNXI_GPF4_UART0_RX	4
++#endif
 +
-+#define SUNXI_GPC9_NDQ1		2
-+#define SUNXI_GPC9_SDC2_D1	3
++#define SUN4I_GPG0_SDC1		4
 +
-+#define SUNXI_GPC10_NDQ2	2
-+#define SUNXI_GPC10_SDC2_D2	3
++#define SUN4I_GPH22_SDC1	5
 +
-+#define SUNXI_GPC11_NDQ3	2
-+#define SUNXI_GPC11_SDC2_D3	3
++#define SUN4I_GPI4_SDC3		2
 +
-+#define SUNXI_GPF2_SDC0_CLK	2
-+#define SUNXI_GPF2_UART0_TX	4
++/* GPIO pin pull-up/down config */
++#define SUNXI_GPIO_PULL_DISABLE	0
++#define SUNXI_GPIO_PULL_UP	1
++#define SUNXI_GPIO_PULL_DOWN	2
 +
-+#define SUNXI_GPF4_SDC0_D3	2
-+#define SUNXI_GPF4_UART0_RX	4
++#define SUNXI_GPL0_R_P2WI_SCK	3
++#define SUNXI_GPL1_R_P2WI_SDA	3
++
++#define SUN8I_GPL2_R_UART_TX	2
++#define SUN8I_GPL3_R_UART_RX	2
 +
 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 +int sunxi_gpio_get_cfgpin(u32 pin);
 +int sunxi_gpio_set_drv(u32 pin, u32 val);
 +int sunxi_gpio_set_pull(u32 pin, u32 val);
-+int name_to_gpio(const char *name);
-+#define name_to_gpio	name_to_gpio
++int sunxi_name_to_gpio(const char *name);
++#define name_to_gpio(name) sunxi_name_to_gpio(name)
 +
 +#endif /* _SUNXI_GPIO_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/i2c.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/i2c.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,185 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/i2c.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/i2c.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,15 @@
 +/*
-+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
-+ *
-+ * Based on sun4i linux kernle i2c.h
-+ * (C) Copyright 2007-2012
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ * Tom Cubie <tanglaing@allwinnertech.com>
-+ * Victor Wei <weiziheng@allwinnertech.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +#ifndef _SUNXI_I2C_H_
 +#define _SUNXI_I2C_H_
 +
-+struct i2c {
-+	u32 saddr;	/*  31:8bit res,7-1bit for slave addr,0 bit for GCE */
-+	u32 xsaddr;	/*  31:8bit res,7-0bit for second addr in 10bit addr */
-+	u32 data;	/*  31:8bit res, 7-0bit send or receive data byte */
-+	u32 ctl;	/*  INT_EN,BUS_EN,M_STA,INT_FLAG,A_ACK */
-+	u32 status;	/*  28 interrupt types + 0xf8 normal type = 29  */
-+	u32 clkr;	/*  31:7bit res,6-3bit,CLK_M,2-0bit CLK_N */
-+	u32 reset;	/*  31:1bit res;0bit,write 1 to clear 0. */
-+	u32 efr;	/*  31:2bit res,1:0 bit data byte follow read comand */
-+	u32 lctl;	/*  31:6bits res 5:0bit for sda&scl control */
-+};
-+
-+/* TWI address register */
-+#define TWI_GCE_EN	(0x1 << 0)	/* gen call addr enable slave mode */
-+#define TWI_ADDR_MASK	(0x7f << 1)	/* 7:1bits */
-+#define TWI_XADDR_MASK	0xff		/* 7:0bits for extend slave address */
-+
-+#define TWI_DATA_MASK	0xff		/* 7:0bits for send or received */
-+
-+/* TWI Control Register Bit Fields */
-+/* 1:0 bits reserved */
-+/* set 1 to send A_ACK,then low level on SDA */
-+#define TWI_CTL_ACK	(0x1 << 2)
-+/* INT_FLAG,interrupt status flag: set '1' when interrupt coming */
-+#define TWI_CTL_INTFLG	(0x1 << 3)
-+#define TWI_CTL_STP	(0x1 << 4)	/* M_STP,Automatic clear 0 */
-+#define TWI_CTL_STA	(0x1 << 5)	/* M_STA,atutomatic clear 0 */
-+#define TWI_CTL_BUSEN	(0x1 << 6)	/* BUS_EN, mastr mode should be set 1 */
-+#define TWI_CTL_INTEN	(0x1 << 7)	/* INT_EN */
-+/* 31:8 bit reserved */
-+
-+/*
-+ * TWI Clock Register Bit Fields & Masks,default value:0x0000_0000
-+ * Fin is APB CLOCK INPUT;
-+ * Fsample = F0 = Fin/2^CLK_N;
-+ *           F1 = F0/(CLK_M+1);
-+ *
-+ * Foscl = F1/10 = Fin/(2^CLK_N * (CLK_M+1)*10);
-+ * Foscl is clock SCL;standard mode:100KHz or fast mode:400KHz
-+ */
++#include <asm/arch/cpu.h>
 +
-+#define TWI_CLK_DIV_M		(0xf << 3)	/* 6:3bit  */
-+#define TWI_CLK_DIV_N		(0x7 << 0)	/* 2:0bit */
-+#define TWI_CLK_DIV(N, M)	((((N) & 0xf) << 3) | (((M) & 0x7) << 0))
-+
-+/* TWI Soft Reset Register Bit Fields & Masks  */
-+/* write 1 to clear 0, when complete soft reset clear 0 */
-+#define TWI_SRST_SRST		(0x1 << 0)
-+
-+/* TWI Enhance Feature Register Bit Fields & Masks  */
-+/* default -- 0x0 */
-+/* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */
-+#define TWI_EFR_MASK		(0x3 << 0)
-+#define TWI_EFR_WARC_0		(0x0 << 0)
-+#define TWI_EFR_WARC_1		(0x1 << 0)
-+#define TWI_EFR_WARC_2		(0x2 << 0)
-+#define TWI_EFR_WARC_3		(0x3 << 0)
-+
-+/* twi line control register -default value: 0x0000_003a */
-+/* SDA line state control enable ,1:enable;0:disable */
-+#define TWI_LCR_SDA_EN		(0x01 << 0)
-+/* SDA line state control bit, 1:high level;0:low level */
-+#define TWI_LCR_SDA_CTL		(0x01 << 1)
-+/* SCL line state control enable ,1:enable;0:disable */
-+#define TWI_LCR_SCL_EN		(0x01 << 2)
-+/* SCL line state control bit, 1:high level;0:low level */
-+#define TWI_LCR_SCL_CTL		(0x01 << 3)
-+/* current state of SDA,readonly bit */
-+#define TWI_LCR_SDA_STATE_MASK	(0x01 << 4)
-+/* current state of SCL,readonly bit */
-+#define TWI_LCR_SCL_STATE_MASK	(0x01 << 5)
-+/* 31:6bits reserved */
-+#define TWI_LCR_IDLE_STATUS	0x3a
-+
-+/* TWI Status Register Bit Fields & Masks  */
-+#define TWI_STAT_MASK		0xff
-+/* 7:0 bits use only,default is 0xf8 */
-+#define TWI_STAT_BUS_ERR	0x00	/* BUS ERROR */
-+
-+/* Master mode use only */
-+#define TWI_STAT_TX_STA		0x08	/* START condition transmitted */
-+/* Repeated START condition transmitted */
-+#define TWI_STAT_TX_RESTA	0x10
-+/* Address+Write bit transmitted, ACK received */
-+#define TWI_STAT_TX_AW_ACK	0x18
-+/* Address+Write bit transmitted, ACK not received */
-+#define TWI_STAT_TX_AW_NAK	0x20
-+/* data byte transmitted in master mode,ack received */
-+#define TWI_STAT_TXD_ACK	0x28
-+/* data byte transmitted in master mode ,ack not received */
-+#define TWI_STAT_TXD_NAK	0x30
-+/* arbitration lost in address or data byte */
-+#define TWI_STAT_ARBLOST	0x38
-+/* Address+Read bit transmitted, ACK received */
-+#define TWI_STAT_TX_AR_ACK	0x40
-+/* Address+Read bit transmitted, ACK not received */
-+#define TWI_STAT_TX_AR_NAK	0x48
-+/* Second Address byte + Write bit transmitted, ACK received */
-+#define TWI_STAT_TX_2AW_ACK	0xd0
-+/* Second Address byte + Write bit transmitted, ACK received */
-+#define TWI_STAT_TX_2AW_NAK	0xd8
-+/* data byte received in master mode ,ack transmitted */
-+#define TWI_STAT_RXD_ACK	0x50
-+/* date byte received in master mode,not ack transmitted */
-+#define TWI_STAT_RXD_NAK	0x58
-+
-+/* Slave mode use only */
-+/* Slave address+Write bit received, ACK transmitted */
-+#define TWI_STAT_RXWS_ACK	0x60
-+/*
-+ * Arbitration lost in address as master, slave address + Write bit received,
-+ * ACK transmitted
-+ */
-+#define TWI_STAT_ARBLOST_RXWS_ACK 0x68
-+/* General Call address received, ACK transmitted */
-+#define TWI_STAT_RXGCAS_ACK	0x70
-+/*
-+ * Arbitration lost in address as master, General Call address received,
-+ * ACK transmitted
-+ */
-+#define TWI_STAT_ARBLOST_RXGCAS_ACK 0x78
-+/* Data byte received after slave address received, ACK transmitted */
-+#define TWI_STAT_RXDS_ACK	0x80
-+/* Data byte received after slave address received, not ACK transmitted */
-+#define TWI_STAT_RXDS_NAK	0x88
-+/* Data byte received after General Call received, ACK transmitted */
-+#define TWI_STAT_RXDGCAS_ACK	0x90
-+/* Data byte received after General Call received, not ACK transmitted */
-+#define TWI_STAT_RXDGCAS_NAK	0x98
-+/* STOP or repeated START condition received in slave  */
-+#define TWI_STAT_RXSTPS_RXRESTAS 0xa0
-+/* Slave address + Read bit received, ACK transmitted */
-+#define TWI_STAT_RXRS_ACK	0xa8
-+/*
-+ * Arbitration lost in address as master, slave address + Read bit received,
-+ * ACK transmitted
-+ */
-+#define TWI_STAT_ARBLOST_SLAR_ACK 0xb0
-+/* Data byte transmitted in slave mode, ACK received */
-+#define TWI_STAT_TXDS_ACK	0xb8
-+/* Data byte transmitted in slave mode, ACK not received */
-+#define TWI_STAT_TXDS_NAK	0xc0
-+/* Last byte transmitted in slave mode, ACK received */
-+#define TWI_STAT_TXDSL_ACK	0xc8
-+
-+/* 10bit Address, second part of address */
-+/* Second Address byte+Write bit transmitted,ACK received */
-+#define TWI_STAT_TX_SAW_ACK	0xd0
-+/* Second Address byte+Write bit transmitted,ACK not received */
-+#define TWI_STAT_TX_SAW_NAK	0xd8
-+
-+/* No relevant status infomation,INT_FLAG = 0 */
-+#define TWI_STAT_IDLE		0xf8
++#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
++/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
++#define CONFIG_SYS_TCLK		24000000
 +
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/key.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/key.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/key.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/key.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,53 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/mmc.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/mmc.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,122 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ * Tom Cubie <tangliang@allwinnertech.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
++ * Aaron <leafy.myeh@allwinnertech.com>
 + *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * MMC register definition for allwinner sunxi platform.
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
-+#ifndef _SUNXI_KEY_H
-+#define _SUNXI_KEY_H
++#ifndef _SUNXI_MMC_H
++#define _SUNXI_MMC_H
 +
 +#include <linux/types.h>
 +
-+struct sunxi_lradc {
-+	u32 ctrl;         /* lradc control */
-+	u32 intc;         /* interrupt control */
-+	u32 ints;         /* interrupt status */
-+	u32 data0;        /* lradc 0 data */
-+	u32 data1;        /* lradc 1 data */
++struct sunxi_mmc {
++	u32 gctrl;		/* 0x00 global control */
++	u32 clkcr;		/* 0x04 clock control */
++	u32 timeout;		/* 0x08 time out */
++	u32 width;		/* 0x0c bus width */
++	u32 blksz;		/* 0x10 block size */
++	u32 bytecnt;		/* 0x14 byte count */
++	u32 cmd;		/* 0x18 command */
++	u32 arg;		/* 0x1c argument */
++	u32 resp0;		/* 0x20 response 0 */
++	u32 resp1;		/* 0x24 response 1 */
++	u32 resp2;		/* 0x28 response 2 */
++	u32 resp3;		/* 0x2c response 3 */
++	u32 imask;		/* 0x30 interrupt mask */
++	u32 mint;		/* 0x34 masked interrupt status */
++	u32 rint;		/* 0x38 raw interrupt status */
++	u32 status;		/* 0x3c status */
++	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
++	u32 funcsel;		/* 0x44 function select */
++	u32 cbcr;		/* 0x48 CIU byte count */
++	u32 bbcr;		/* 0x4c BIU byte count */
++	u32 dbgc;		/* 0x50 debug enable */
++	u32 res0[11];
++	u32 dmac;		/* 0x80 internal DMA control */
++	u32 dlba;		/* 0x84 internal DMA descr list base address */
++	u32 idst;		/* 0x88 internal DMA status */
++	u32 idie;		/* 0x8c internal DMA interrupt enable */
++	u32 chda;		/* 0x90 */
++	u32 cbda;		/* 0x94 */
 +};
 +
-+#define LRADC_EN                  0x1    /* LRADC enable */
-+#define LRADC_SAMPLE_RATE         0x2    /* 32.25 Hz */
-+#define LEVELB_VOL                0x2    /* 0x33(~1.6v) */
-+#define LRADC_HOLD_EN             0x1    /* sample hold enable */
-+#define KEY_MODE_SELECT           0x0    /* normal mode */
-+
-+#define ADC0_DATA_PENDING         (0x1 << 0)    /* adc0 has data */
-+#define ADC0_KEYDOWN_PENDING      (0x1 << 1)    /* key down */
-+#define ADC0_HOLDKEY_PENDING      (0x1 << 2)    /* key hold */
-+#define ADC0_ALRDY_HOLD_PENDING   (0x1 << 3)    /* key already hold */
-+#define ADC0_KEYUP_PENDING        (0x1 << 4)    /* key up */
-+
-+int sunxi_key_init(void);
-+u32 sunxi_read_key(void);
++#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
++#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
++#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
++
++#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
++#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
++#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
++#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
++					 SUNXI_MMC_GCTRL_FIFO_RESET|\
++					 SUNXI_MMC_GCTRL_DMA_RESET)
++#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
++#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
++
++#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
++#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
++#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
++#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
++#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
++#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
++#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
++#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
++#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
++#define SUNXI_MMC_CMD_START		(0x1 << 31)
++
++#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
++#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
++#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
++#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
++#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
++#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
++#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
++#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
++#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
++#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
++#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
++#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
++#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
++#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
++#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
++#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
++#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
++#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
++#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
++	(SUNXI_MMC_RINT_RESP_ERROR |		\
++	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
++	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
++	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
++	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
++	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
++	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
++#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
++	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
++	 SUNXI_MMC_RINT_DATA_OVER |		\
++	 SUNXI_MMC_RINT_COMMAND_DONE |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
++
++#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
++#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
++#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
++#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
++#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
++#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
++#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
++
++#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
++#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
++#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
++
++#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
++#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
 +
-+#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/mmc.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/mmc.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,66 @@
++int sunxi_mmc_init(int sdc_no);
++#endif /* _SUNXI_MMC_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/p2wi.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/p2wi.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/p2wi.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/p2wi.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,142 @@
 +/*
-+ * (C) Copyright 2007-2011
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ * Aaron <leafy.myeh@allwinnertech.com>
-+ *
-+ * MMC register definition for allwinner sunxi platform.
++ * Sunxi platform Push-Push i2c register definition.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
++ * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ * http://linux-sunxi.org
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
++ * (c)Copyright 2006-2013
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Berg Xing <bergxing@allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
-+#ifndef _SUNXI_MMC_H
-+#define _SUNXI_MMC_H
++#ifndef _SUNXI_P2WI_H
++#define _SUNXI_P2WI_H
 +
 +#include <linux/types.h>
 +
-+struct sunxi_mmc {
-+	u32 gctrl;		/* (0x00) SMC Global Control Register */
-+	u32 clkcr;		/* (0x04) SMC Clock Control Register */
-+	u32 timeout;		/* (0x08) SMC Time Out Register */
-+	u32 width;		/* (0x0c) SMC Bus Width Register */
-+	u32 blksz;		/* (0x10) SMC Block Size Register */
-+	u32 bytecnt;		/* (0x14) SMC Byte Count Register */
-+	u32 cmd;		/* (0x18) SMC Command Register */
-+	u32 arg;		/* (0x1c) SMC Argument Register */
-+	u32 resp0;		/* (0x20) SMC Response Register 0 */
-+	u32 resp1;		/* (0x24) SMC Response Register 1 */
-+	u32 resp2;		/* (0x28) SMC Response Register 2 */
-+	u32 resp3;		/* (0x2c) SMC Response Register 3 */
-+	u32 imask;		/* (0x30) SMC Interrupt Mask Register */
-+	u32 mint;		/* (0x34) SMC Masked Interrupt Status Reg */
-+	u32 rint;		/* (0x38) SMC Raw Interrupt Status Register */
-+	u32 status;		/* (0x3c) SMC Status Register */
-+	u32 ftrglevel;		/* (0x40) SMC FIFO Threshold Watermark Reg */
-+	u32 funcsel;		/* (0x44) SMC Function Select Register */
-+	u32 cbcr;		/* (0x48) SMC CIU Byte Count Register */
-+	u32 bbcr;		/* (0x4c) SMC BIU Byte Count Register */
-+	u32 dbgc;		/* (0x50) SMC Debug Enable Register */
-+	u32 res0[11];		/* (0x54~0x7c) */
-+	u32 dmac;		/* (0x80) SMC IDMAC Control Register */
-+	u32 dlba;		/* (0x84) SMC IDMAC Descr List Base Addr Reg */
-+	u32 idst;		/* (0x88) SMC IDMAC Status Register */
-+	u32 idie;		/* (0x8c) SMC IDMAC Interrupt Enable Register */
-+	u32 chda;		/* (0x90) */
-+	u32 cbda;		/* (0x94) */
-+	u32 res1[26];		/* (0x98~0xff) */
-+	u32 fifo;		/* (0x100) SMC FIFO Access Address */
++#define P2WI_CTRL_RESET (0x1 << 0)
++#define P2WI_CTRL_IRQ_EN (0x1 << 1)
++#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
++#define P2WI_CTRL_TRANS_START (0x1 << 7)
++
++#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
++#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
++#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
++#define P2WI_CC_CLK_DIV(n) \
++	__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
++#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
++#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
++
++#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
++#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
++#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
++
++#define P2WI_STAT_TRANS_DONE (0x1 << 0)
++#define P2WI_STAT_TRANS_ERR (0x1 << 1)
++#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
++#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
++#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
++#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
++#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
++#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
++#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
++#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
++#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
++#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
++#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
++#define P2WI_STAT_TRANS_ERR_BYTE_1 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
++#define P2WI_STAT_TRANS_ERR_BYTE_2 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
++#define P2WI_STAT_TRANS_ERR_BYTE_3 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
++#define P2WI_STAT_TRANS_ERR_BYTE_4 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
++#define P2WI_STAT_TRANS_ERR_BYTE_5 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
++#define P2WI_STAT_TRANS_ERR_BYTE_6 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
++#define P2WI_STAT_TRANS_ERR_BYTE_7 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
++#define P2WI_STAT_TRANS_ERR_BYTE_8 \
++	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
++
++#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
++#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
++#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
++#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
++#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
++#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
++#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
++#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
++#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
++#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
++#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
++#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
++#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
++#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
++#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
++#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
++
++#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
++#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
++#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
++#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
++
++#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
++#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
++#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
++#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
++#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
++#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
++#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
++#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
++#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
++#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
++#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
++#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
++#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
++#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
++#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
++#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
++
++#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
++#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
++#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
++#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
++#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
++#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
++
++#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
++#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
++#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
++#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
++#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
++#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
++#define P2WI_PM_INIT_SEND (0x1 << 31)
++
++#ifndef __ASSEMBLY__
++struct sunxi_p2wi_reg {
++	u32 ctrl;	/* 0x00 control */
++	u32 cc;		/* 0x04 clock control */
++	u32 irq;	/* 0x08 interrupt */
++	u32 status;	/* 0x0c status */
++	u32 dataddr0;	/* 0x10 data address 0 */
++	u32 dataddr1;	/* 0x14 data address 1 */
++	u32 numbytes;	/* 0x18 num bytes */
++	u32 data0;	/* 0x1c data buffer 0 */
++	u32 data1;	/* 0x20 data buffer 1 */
++	u32 linectrl;	/* 0x24 line control */
++	u32 pm;		/* 0x28 power management */
 +};
 +
-+int sunxi_mmc_init(int sdc_no);
-+#endif /* _SUNXI_MMC_H */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/smp.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/smp.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,38 @@
++void p2wi_init(void);
++int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data);
++int p2wi_read(const u8 addr, u8 *data);
++int p2wi_write(const u8 addr, u8 data);
++
++#endif /* __ASSEMBLY__ */
++#endif /* _SUNXI_P2WI_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/prcm.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/prcm.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/prcm.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/prcm.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,238 @@
++/*
++ * Sunxi A31 Power Management Unit register definition.
++ *
++ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ * http://linux-sunxi.org
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Berg Xing <bergxing@allwinnertech.com>
++ * Tom Cubie <tangliang@allwinnertech.com>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef _SUNXI_PRCM_H
++#define _SUNXI_PRCM_H
++
++#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
++#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
++#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
++#define PRCM_CPUS_CFG_PRE_DIV(n) \
++	__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
++#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
++#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
++#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
++#define PRCM_CPUS_CFG_POST_DIV(n) \
++	__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
++#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
++#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
++#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
++#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
++#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
++#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
++#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
++	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
++#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
++	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
++#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
++	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
++#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
++	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
++
++#define __PRCM_APB0_RATIO(n) (((n) & 0x3) <<0)
++#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
++#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
++#define PRCM_APB0_RATIO_DIV(n) \
++	__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
++
++#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
++#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
++
++#define PRCM_APB0_GATE_PIO (0x1 << 0)
++#define PRCM_APB0_GATE_IR (0x1 << 1)
++#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
++#define PRCM_APB0_GATE_P2WI (0x1 << 3)
++#define PRCM_APB0_GATE_UART (0x1 << 4)
++#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
++#define PRCM_APB0_GATE_I2C (0x1 << 6)
++
++#define PRCM_APB0_RESET_PIO (0x1 << 0)
++#define PRCM_APB0_RESET_IR (0x1 << 1)
++#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
++#define PRCM_APB0_RESET_P2WI (0x1 << 3)
++#define PRCM_APB0_RESET_UART (0x1 << 4)
++#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
++#define PRCM_APB0_RESET_I2C (0x1 << 6)
++
++#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
++#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
++#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
++#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
++	__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
++#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
++#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
++#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
++#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
++#define PRCM_PLL_CTRL_USB_CLK_0 \
++	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
++#define PRCM_PLL_CTRL_USB_CLK_1 \
++	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
++#define PRCM_PLL_CTRL_USB_CLK_2 \
++	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
++#define PRCM_PLL_CTRL_USB_CLK_3 \
++	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
++#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
++#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
++	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
++#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
++	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
++#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
++#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
++	__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
++#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
++#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
++#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
++#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
++#define PRCM_PLL_CTRL_HOSC_CLK_0 \
++	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
++#define PRCM_PLL_CTRL_HOSC_CLK_1 \
++	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
++#define PRCM_PLL_CTRL_HOSC_CLK_2 \
++	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
++#define PRCM_PLL_CTRL_HOSC_CLK_3 \
++	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
++#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
++#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
++#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
++#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
++#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
++#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
++#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
++#define PRCM_PLL_CTRL_LDO_OUT_MASK \
++	__PRCM_PLL_CTRL_LDO_OUT(0x7)
++/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
++#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
++#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
++#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
++#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
++#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
++
++#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
++
++#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
++#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
++#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
++#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
++#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
++#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
++#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
++#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
++#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) -1)
++#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
++#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
++#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
++#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
++#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
++#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
++
++#define PRCM_APB0_RESET_PIO (0x1 << 0)
++#define PRCM_APB0_RESET_IR (0x1 << 1)
++#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
++#define PRCM_APB0_RESET_P2WI (0x1 << 3)
++#define PRCM_APB0_RESET_UART (0x1 << 4)
++#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
++#define PRCM_APB0_RESET_I2C (0x1 << 6)
++
++#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
++#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
++#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
++#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
++#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
++#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
++#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
++#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
++#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
++#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
++#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
++#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
++#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
++#define __PRCM_CLK_OUTD_SRC_ERR 0x3
++#define PRCM_CLK_OUTD_SRC_LOSC2 \
++#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
++#define PRCM_CLK_OUTD_SRC_LOSC \
++#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
++#define PRCM_CLK_OUTD_SRC_HOSC \
++#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
++#define PRCM_CLK_OUTD_SRC_ERR \
++#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
++#define PRCM_CLK_OUTD_EN (0x1 << 31)
++
++#define PRCM_CPU0_PWROFF (0x1 << 0)
++#define PRCM_CPU1_PWROFF (0x1 << 1)
++#define PRCM_CPU2_PWROFF (0x1 << 2)
++#define PRCM_CPU3_PWROFF (0x1 << 3)
++#define PRCM_CPU_ALL_PWROFF (0xf << 0)
++
++#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
++#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
++#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
++#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
++
++#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
++
++#define PRCM_VDD_SYS_RESET (0x1 << 0)
++
++#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
++#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
++
++#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
++#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
++
++#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
++#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
++
++#ifndef __ASSEMBLY__
++struct sunxi_prcm_reg {
++	u32 cpus_cfg;		/* 0x000 */
++	u8 res0[0x8];		/* 0x004 */
++	u32 apb0_ratio;		/* 0x00c */
++	u32 cpu0_cfg;		/* 0x010 */
++	u32 cpu1_cfg;		/* 0x014 */
++	u32 cpu2_cfg;		/* 0x018 */
++	u32 cpu3_cfg;		/* 0x01c */
++	u8 res1[0x8];		/* 0x020 */
++	u32 apb0_gate;		/* 0x028 */
++	u8 res2[0x14];		/* 0x02c */
++	u32 pll_ctrl0;		/* 0x040 */
++	u32 pll_ctrl1;		/* 0x044 */
++	u8 res3[0x8];		/* 0x048 */
++	u32 clk_1wire;		/* 0x050 */
++	u32 clk_ir;		/* 0x054 */
++	u8 res4[0x58];		/* 0x058 */
++	u32 apb0_reset;		/* 0x0b0 */
++	u8 res5[0x3c];		/* 0x0b4 */
++	u32 clk_outd;		/* 0x0f0 */
++	u8 res6[0xc];		/* 0x0f4 */
++	u32 cpu_pwroff;		/* 0x100 */
++	u8 res7[0xc];		/* 0x104 */
++	u32 vdd_sys_pwroff;	/* 0x110 */
++	u8 res8[0x4];		/* 0x114 */
++	u32 gpu_pwroff;		/* 0x118 */
++	u8 res9[0x4];		/* 0x11c */
++	u32 vdd_pwr_reset;	/* 0x120 */
++	u8 res10[0x20];		/* 0x124 */
++	u32 cpu1_pwr_clamp;	/* 0x144 */
++	u32 cpu2_pwr_clamp;	/* 0x148 */
++	u32 cpu3_pwr_clamp;	/* 0x14c */
++	u8 res11[0x30];		/* 0x150 */
++	u32 dram_pwr;		/* 0x180 */
++	u8 res12[0xc];		/* 0x184 */
++	u32 dram_tst;		/* 0x190 */
++};
++
++void prcm_apb0_enable(u32 flags);
++#endif /* __ASSEMBLY__ */
++#endif /* _PRCM_H */
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/smp.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/smp.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,22 @@
 +/*
 + * (C) Copyright 2013
 + * Carl van Schaik <carl@ok-labs.com>
 + *
 + * CPU configuration registers for the sun7i (A20).
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_SMP_H_
@@ -4325,33 +3841,17 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/smp.h u-boot-sunxi/
 +#endif /* __ASSEMBLY__ */
 +
 +#endif /* _SUNXI_SMP_H_ */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/spl.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/spl.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,36 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/spl.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/spl.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,20 @@
 +/*
 + * This is a copy of omap3/spl.h:
 + *
 + * (C) Copyright 2012
 + * Texas Instruments, <www.ti.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +#ifndef	_ASM_ARCH_SPL_H_
 +#define	_ASM_SPL_H_
@@ -4365,32 +3865,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/spl.h u-boot-sunxi/
 +#define BOOT_DEVICE_XIPWAIT	7
 +#define BOOT_DEVICE_MMC2_2      0xff
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/sys_proto.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/sys_proto.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,33 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/sys_proto.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/sys_proto.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,16 @@
 +/*
 + * (C) Copyright 2007-2012
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SYS_PROTO_H_
@@ -4398,14 +3882,13 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/sys_proto.h u-boot-
 +
 +#include <linux/types.h>
 +
-+void sr32(u32 *, u32, u32, u32);
 +void sdelay(unsigned long);
 +
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,104 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/timer.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,88 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -4413,23 +3896,7 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunx
 + *
 + * Configuration settings for the Allwinner A10-evb board.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_TIMER_H_
@@ -4510,29 +3977,16 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunx
 +#endif /* __ASSEMBLY__ */
 +
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/watchdog.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/watchdog.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h	2014-03-05 23:14:47.176099871 +0100
-@@ -0,0 +1,35 @@
+diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/watchdog.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h
+--- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/watchdog.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h	2014-09-06 16:58:35.381953139 +0200
+@@ -0,0 +1,22 @@
 +/*
 + * Watchdog driver for the Allwinner sunxi platform.
 + * Copyright (C) 2013  Oliver Schinagl <oliver@schinagl.nl>
 + * http://www.linux-sunxi.org/
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-+ * MA  02110-1301, USA.
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_WATCHDOG_H_
@@ -4549,231 +4003,10 @@ diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/watchdog.h u-boot-s
 +#endif /* __ASSEMBLY__ */
 +
 +#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/armv7.h u-boot-sunxi/arch/arm/include/asm/armv7.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/armv7.h	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/armv7.h	2014-03-05 23:14:47.184099763 +0100
-@@ -78,13 +78,18 @@
- 
- #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
- 
--int armv7_switch_nonsec(void);
--int armv7_switch_hyp(void);
-+int armv7_init_nonsec(void);
-+int armv7_update_dt(void *fdt);
- 
- /* defined in assembly file */
- unsigned int _nonsec_init(void);
-+void _do_nonsec_entry(void *target_pc, unsigned long r0,
-+		      unsigned long r1, unsigned long r2);
- void _smp_pen(void);
--void _switch_to_hyp(void);
-+
-+extern char __secure_start[];
-+extern char __secure_end[];
-+
- #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
- 
- #endif /* ! __ASSEMBLY__ */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/proc-armv/ptrace.h u-boot-sunxi/arch/arm/include/asm/proc-armv/ptrace.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/proc-armv/ptrace.h	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/proc-armv/ptrace.h	2014-03-05 23:14:47.196099604 +0100
-@@ -19,12 +19,14 @@
- #define IRQ_MODE	0x12
- #define SVC_MODE	0x13
- #define ABT_MODE	0x17
-+#define HYP_MODE	0x1a
- #define UND_MODE	0x1b
- #define SYSTEM_MODE	0x1f
- #define MODE_MASK	0x1f
- #define T_BIT		0x20
- #define F_BIT		0x40
- #define I_BIT		0x80
-+#define A_BIT		0x100
- #define CC_V_BIT	(1 << 28)
- #define CC_C_BIT	(1 << 29)
- #define CC_Z_BIT	(1 << 30)
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/psci.h u-boot-sunxi/arch/arm/include/asm/psci.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/psci.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/psci.h	2014-03-05 23:14:47.196099604 +0100
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright (C) 2013 - ARM Ltd
-+ * Author: Marc Zyngier <marc.zyngier@arm.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef __ARM_PSCI_H__
-+#define __ARM_PSCI_H__
-+
-+/* PSCI interface */
-+#define ARM_PSCI_FN_BASE		0x95c1ba5e
-+#define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
-+
-+#define ARM_PSCI_FN_CPU_SUSPEND		ARM_PSCI_FN(0)
-+#define ARM_PSCI_FN_CPU_OFF		ARM_PSCI_FN(1)
-+#define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
-+#define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
-+
-+#define ARM_PSCI_RET_SUCCESS		0
-+#define ARM_PSCI_RET_NI			(-1)
-+#define ARM_PSCI_RET_INVAL		(-2)
-+#define ARM_PSCI_RET_DENIED		(-3)
-+
-+#endif /* __ARM_PSCI_H__ */
-diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/secure.h u-boot-sunxi/arch/arm/include/asm/secure.h
---- u-boot-2014.01-rc1/arch/arm/include/asm/secure.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/arch/arm/include/asm/secure.h	2014-03-05 23:14:47.196099604 +0100
-@@ -0,0 +1,26 @@
-+#ifndef __ASM_SECURE_H
-+#define __ASM_SECURE_H
-+
-+#include <config.h>
-+
-+#ifdef CONFIG_ARMV7_SECURE_BASE
-+/*
-+ * Warning, horror ahead.
-+ *
-+ * The target code lives in our "secure ram", but u-boot doesn't know
-+ * that, and has blindly added reloc_off to every relocation
-+ * entry. Gahh. Do the opposite conversion. This hack also prevents
-+ * GCC from generating code veeners, which u-boot doesn't relocate at
-+ * all...
-+ */
-+#define secure_ram_addr(_fn) ({						\
-+			DECLARE_GLOBAL_DATA_PTR;			\
-+			void *__fn = _fn;				\
-+			typeof(_fn) *__tmp = (__fn - gd->reloc_off);	\
-+			__tmp;						\
-+		})
-+#else
-+#define secure_ram_addr(_fn)	(_fn)
-+#endif
-+
-+#endif
-diff -ruN u-boot-2014.01-rc1/arch/arm/lib/bootm.c u-boot-sunxi/arch/arm/lib/bootm.c
---- u-boot-2014.01-rc1/arch/arm/lib/bootm.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/lib/bootm.c	2014-03-05 23:14:47.196099604 +0100
-@@ -20,6 +20,7 @@
- #include <libfdt.h>
- #include <fdt_support.h>
- #include <asm/bootm.h>
-+#include <asm/secure.h>
- #include <linux/compiler.h>
- 
- #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-@@ -185,19 +186,6 @@
- 
- __weak void setup_board_tags(struct tag **in_params) {}
- 
--static void do_nonsec_virt_switch(void)
--{
--#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
--	if (armv7_switch_nonsec() == 0)
--#ifdef CONFIG_ARMV7_VIRT
--		if (armv7_switch_hyp() == 0)
--			debug("entered HYP mode\n");
--#else
--		debug("entered non-secure state\n");
--#endif
--#endif
--}
--
- /* Subcommand: PREP */
- static void boot_prep_linux(bootm_headers_t *images)
- {
-@@ -234,7 +222,6 @@
- 		printf("FDT and ATAGS support not compiled in - hanging\n");
- 		hang();
- 	}
--	do_nonsec_virt_switch();
- }
- 
- /* Subcommand: GO */
-@@ -264,8 +251,15 @@
- 	else
- 		r2 = gd->bd->bi_boot_params;
- 
--	if (!fake)
-+	if (!fake) {
-+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-+		armv7_init_nonsec();
-+		secure_ram_addr(_do_nonsec_entry)(kernel_entry,
-+						  0, machid, r2);
-+#else
- 		kernel_entry(0, machid, r2);
-+#endif
-+	}
- }
- 
- /* Main Entry point for arm bootm implementation
-diff -ruN u-boot-2014.01-rc1/arch/arm/lib/bootm-fdt.c u-boot-sunxi/arch/arm/lib/bootm-fdt.c
---- u-boot-2014.01-rc1/arch/arm/lib/bootm-fdt.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/lib/bootm-fdt.c	2014-03-05 23:14:47.196099604 +0100
-@@ -17,6 +17,9 @@
- 
- #include <common.h>
- #include <fdt_support.h>
-+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-+#include <asm/armv7.h>
-+#endif
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
-@@ -34,3 +37,18 @@
- 
- 	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
- }
-+
-+int arch_fixup_fdt(void *blob)
-+{
-+	int ret;
-+
-+	ret = arch_fixup_memory_node(blob);
-+	if (ret)
-+		return ret;
-+
-+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-+	ret = armv7_update_dt(blob);
-+#endif
-+
-+	return ret;
-+}
-diff -ruN u-boot-2014.01-rc1/arch/arm/lib/interrupts.c u-boot-sunxi/arch/arm/lib/interrupts.c
---- u-boot-2014.01-rc1/arch/arm/lib/interrupts.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/lib/interrupts.c	2014-03-05 23:14:47.196099604 +0100
-@@ -103,7 +103,7 @@
- 	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
- 	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
- 	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
--	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-+	"UK8_32",	"UK9_32",	"HYP_32",	"UND_32",
- 	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
- 	};
- 
-diff -ruN u-boot-2014.01-rc1/arch/arm/lib/sections.c u-boot-sunxi/arch/arm/lib/sections.c
---- u-boot-2014.01-rc1/arch/arm/lib/sections.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/arch/arm/lib/sections.c	2014-03-05 23:14:47.196099604 +0100
-@@ -25,3 +25,5 @@
- char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
- char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
- char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
-+char __secure_start[0] __attribute__((section(".__secure_start")));
-+char __secure_end[0] __attribute__((section(".__secure_end")));
-diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.c
---- u-boot-2014.01-rc1/board/sunxi/board.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/board.c	2014-03-05 23:14:47.908090095 +0100
-@@ -0,0 +1,165 @@
+diff -ruN u-boot-2014.04/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.c
+--- u-boot-2014.04/board/sunxi/board.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/board.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,239 @@
 +/*
 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
@@ -4784,23 +4017,7 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 + *
 + * Some board init for the Allwinner A10-evb board.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -4810,9 +4027,16 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 +#ifdef CONFIG_AXP209_POWER
 +#include <axp209.h>
 +#endif
++#ifdef CONFIG_AXP221_POWER
++#include <axp221.h>
++#endif
 +#include <asm/arch/clock.h>
++#include <asm/arch/cpu.h>
 +#include <asm/arch/dram.h>
++#include <asm/arch/gpio.h>
 +#include <asm/arch/mmc.h>
++#include <asm/io.h>
++#include <net.h>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
@@ -4849,16 +4073,65 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 +
 +int dram_init(void)
 +{
-+	gd->ram_size = get_ram_size((unsigned long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
++	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
 +
 +	return 0;
 +}
 +
 +#ifdef CONFIG_GENERIC_MMC
++static void mmc_pinmux_setup(int sdc)
++{
++	unsigned int pin;
++
++	switch (sdc) {
++	case 0:
++		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
++		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
++			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
++			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
++			sunxi_gpio_set_drv(pin, 2);
++		}
++		break;
++
++	case 1:
++		/* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
++		for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
++			sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
++			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
++			sunxi_gpio_set_drv(pin, 2);
++		}
++		break;
++
++	case 2:
++		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
++		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
++			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
++			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
++			sunxi_gpio_set_drv(pin, 2);
++		}
++		break;
++
++	case 3:
++		/* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
++		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
++			sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
++			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
++			sunxi_gpio_set_drv(pin, 2);
++		}
++		break;
++
++	default:
++		printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
++		break;
++	}
++}
++
 +int board_mmc_init(bd_t *bis)
 +{
++	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
 +	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
 +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
++	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 +	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 +#endif
 +
@@ -4866,25 +4139,20 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 +}
 +#endif
 +
-+#ifdef CONFIG_SPL_BUILD
++void i2c_init_board(void)
++{
++	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
++	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
++	clock_twi_onoff(0, 1);
++}
++
++#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 +void sunxi_board_init(void)
 +{
 +	int power_failed = 0;
++#if !defined(CONFIG_SUN6I) && !defined(CONFIG_SUN8I)
 +	unsigned long ramsize;
-+
-+	printf("DRAM:");
-+	ramsize = sunxi_dram_init();
-+	if (!ramsize) {
-+		printf(" ?");
-+		ramsize = sunxi_dram_init();
-+	}
-+	if (!ramsize) {
-+		printf(" ?");
-+		ramsize = sunxi_dram_init();
-+	}
-+	printf(" %lu MiB\n", ramsize >> 20);
-+	if (!ramsize)
-+		hang();
++#endif
 +
 +#ifdef CONFIG_AXP152_POWER
 +	power_failed = axp152_init();
@@ -4905,20 +4173,36 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 +	power_failed |= axp209_set_ldo3(2800);
 +	power_failed |= axp209_set_ldo4(2800);
 +#endif
++#ifdef CONFIG_AXP221_POWER
++	power_failed = axp221_init();
++	power_failed |= axp221_set_dcdc1(3300);
++	power_failed |= axp221_set_dcdc2(1200);
++	power_failed |= axp221_set_dcdc3(1260);
++	power_failed |= axp221_set_dcdc4(1200);
++	power_failed |= axp221_set_dcdc5(1500);
++#ifdef CONFIG_ENABLE_DLDO1_POWER
++	power_failed |= axp221_set_dldo1(3300);
++#endif
++#endif
++
++#if !defined(CONFIG_SUN6I) && !defined(CONFIG_SUN8I)
++	printf("DRAM:");
++	ramsize = sunxi_dram_init();
++	printf(" %lu MiB\n", ramsize >> 20);
++	if (!ramsize)
++		hang();
 +
 +	/*
 +	 * Only clock up the CPU to full speed if we are reasonably
 +	 * assured it's being powered with suitable core voltage
 +	 */
 +	if (!power_failed)
-+#ifdef CONFIG_SUN7I
-+		clock_set_pll1(912000000);
-+#else
-+		clock_set_pll1(1008000000);
-+#endif
++		clock_set_pll1(CONFIG_CLK_FULL_SPEED);
 +	else
 +		printf("Failed to set core voltage! Can't set CPU frequency\n");
++#endif
 +}
++#endif
 +
 +#if defined(CONFIG_SPL_OS_BOOT) && defined(CONFIG_AXP209_POWER)
 +int spl_start_uboot(void)
@@ -4938,10 +4222,33 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.
 +}
 +#endif
 +
++#ifdef CONFIG_MISC_INIT_R
++int misc_init_r(void)
++{
++	if (!getenv("ethaddr")) {
++		uint32_t reg_val = readl(SUNXI_SID_BASE);
++
++		if (reg_val) {
++			uint8_t mac_addr[6];
++
++			mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
++			mac_addr[1] = (reg_val >>  0) & 0xff;
++			reg_val = readl(SUNXI_SID_BASE + 0x0c);
++			mac_addr[2] = (reg_val >> 24) & 0xff;
++			mac_addr[3] = (reg_val >> 16) & 0xff;
++			mac_addr[4] = (reg_val >>  8) & 0xff;
++			mac_addr[5] = (reg_val >>  0) & 0xff;
++
++			eth_setenv_enetaddr("ethaddr", mac_addr);
++		}
++	}
++
++	return 0;
++}
 +#endif
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a10_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a10_olinuxino_l.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_a10_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c
+--- u-boot-2014.04/board/sunxi/dram_a10_olinuxino_l.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -4974,79 +4281,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a10_olinuxino_l.c u-boot-sunxi/boa
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a10s_olinuxino_m.c u-boot-sunxi/board/sunxi/dram_a10s_olinuxino_m.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a10s_olinuxino_m.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a10s_olinuxino_m.c	2014-03-05 23:14:47.908090095 +0100
-@@ -0,0 +1,31 @@
-+/* this file is generated, don't edit it yourself */
-+
-+#include <common.h>
-+#include <asm/arch/dram.h>
-+
-+static struct dram_para dram_para = {
-+	.clock = 432,
-+	.type = 3,
-+	.rank_num = 1,
-+	.density = 4096,
-+	.io_width = 16,
-+	.bus_width = 16,
-+	.cas = 9,
-+	.zq = 123,
-+	.odt_en = 0,
-+	.size = 512,
-+	.tpr0 = 0x42d899b7,
-+	.tpr1 = 0xa090,
-+	.tpr2 = 0x22a00,
-+	.tpr3 = 0,
-+	.tpr4 = 0,
-+	.tpr5 = 0,
-+	.emr1 = 0x4,
-+	.emr2 = 0x10,
-+	.emr3 = 0,
-+};
-+
-+unsigned long sunxi_dram_init(void)
-+{
-+	return dramc_init(&dram_para);
-+}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_mid.c u-boot-sunxi/board/sunxi/dram_a13_mid.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a13_mid.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a13_mid.c	2014-03-05 23:14:47.908090095 +0100
-@@ -0,0 +1,31 @@
-+/* this file is generated, don't edit it yourself */
-+
-+#include <common.h>
-+#include <asm/arch/dram.h>
-+
-+static struct dram_para dram_para = {
-+	.clock = 408,
-+	.type = 3,
-+	.rank_num = 1,
-+	.density = 2048,
-+	.io_width = 8,
-+	.bus_width = 16,
-+	.cas = 9,
-+	.zq = 123,
-+	.odt_en = 1,
-+	.size = 512,
-+	.tpr0 = 0x42d899b7,
-+	.tpr1 = 0xa090,
-+	.tpr2 = 0x22a00,
-+	.tpr3 = 0,
-+	.tpr4 = 0,
-+	.tpr5 = 0,
-+	.emr1 = 0x4,
-+	.emr2 = 0x10,
-+	.emr3 = 0,
-+};
-+
-+unsigned long sunxi_dram_init(void)
-+{
-+	return dramc_init(&dram_para);
-+}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_oli_micro.c u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a13_oli_micro.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_a13_oli_micro.c u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c
+--- u-boot-2014.04/board/sunxi/dram_a13_oli_micro.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,32 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5080,9 +4317,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_oli_micro.c u-boot-sunxi/board
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_olinuxino.c u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a13_olinuxino.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_a13_olinuxino.c u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c
+--- u-boot-2014.04/board/sunxi/dram_a13_olinuxino.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5115,9 +4352,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_olinuxino.c u-boot-sunxi/board
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_m.c
---- u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_m.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l2.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l2.c
+--- u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l2.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l2.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5125,7 +4362,7 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c u-boot-sunxi/boa
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 384,
++	.clock = 480,
 +	.type = 3,
 +	.rank_num = 1,
 +	.density = 4096,
@@ -5150,33 +4387,33 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c u-boot-sunxi/boa
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_auxtek_t003.c u-boot-sunxi/board/sunxi/dram_auxtek_t003.c
---- u-boot-2014.01-rc1/board/sunxi/dram_auxtek_t003.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_auxtek_t003.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l.c
+--- u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
-+#include <common.h>
++#include "common.h"
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 408,
++	.clock = 480,
 +	.type = 3,
 +	.rank_num = 1,
-+	.density = 2048,
-+	.io_width = 8,
-+	.bus_width = 32,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
 +	.cas = 9,
-+	.zq = 123,
++	.zq = 0x7f,
 +	.odt_en = 0,
-+	.size = 1024,
++	.size = 512,
 +	.tpr0 = 0x42d899b7,
 +	.tpr1 = 0xa090,
 +	.tpr2 = 0x22a00,
 +	.tpr3 = 0,
 +	.tpr4 = 0,
 +	.tpr5 = 0,
-+	.emr1 = 0,
++	.emr1 = 0x4,
 +	.emr2 = 0x10,
 +	.emr3 = 0,
 +};
@@ -5185,44 +4422,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_auxtek_t003.c u-boot-sunxi/board/s
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard2.c u-boot-sunxi/board/sunxi/dram_cubieboard2.c
---- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard2.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_cubieboard2.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_ainol_aw1.c u-boot-sunxi/board/sunxi/dram_ainol_aw1.c
+--- u-boot-2014.04/board/sunxi/dram_ainol_aw1.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_ainol_aw1.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
-+#include <common.h>
++#include "common.h"
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 480,
++	.clock = 432,
 +	.type = 3,
 +	.rank_num = 1,
-+	.density = 4096,
++	.density = 2048,
 +	.io_width = 16,
 +	.bus_width = 32,
 +	.cas = 9,
-+	.zq = 0x7f,
++	.zq = 0x7b,
 +	.odt_en = 0,
-+	.size = 1024,
++	.size = 512,
 +	.tpr0 = 0x42d899b7,
 +	.tpr1 = 0xa090,
 +	.tpr2 = 0x22a00,
-+	.tpr3 = 0x0,
-+	.tpr4 = 0x1,
-+	.tpr5 = 0x0,
++	.tpr3 = 0,
++	.tpr4 = 1,
++	.tpr5 = 0,
 +	.emr1 = 0x4,
 +	.emr2 = 0x10,
-+	.emr3 = 0x0,
++	.emr3 = 0,
 +};
 +
 +unsigned long sunxi_dram_init(void)
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c u-boot-sunxi/board/sunxi/dram_cubieboard_512.c
---- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_cubieboard_512.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_auxtek_t003.c u-boot-sunxi/board/sunxi/dram_auxtek_t003.c
+--- u-boot-2014.04/board/sunxi/dram_auxtek_t003.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_auxtek_t003.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5230,24 +4467,24 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c u-boot-sunxi/boar
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 480,
++	.clock = 408,
 +	.type = 3,
 +	.rank_num = 1,
 +	.density = 2048,
-+	.io_width = 16,
++	.io_width = 8,
 +	.bus_width = 32,
-+	.cas = 6,
++	.cas = 9,
 +	.zq = 123,
 +	.odt_en = 0,
-+	.size = 512,
-+	.tpr0 = 0x30926692,
-+	.tpr1 = 0x1090,
-+	.tpr2 = 0x1a0c8,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
 +	.tpr3 = 0,
 +	.tpr4 = 0,
 +	.tpr5 = 0,
 +	.emr1 = 0,
-+	.emr2 = 0,
++	.emr2 = 0x10,
 +	.emr3 = 0,
 +};
 +
@@ -5255,9 +4492,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c u-boot-sunxi/boar
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard.c u-boot-sunxi/board/sunxi/dram_cubieboard.c
---- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_cubieboard.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_cubieboard.c u-boot-sunxi/board/sunxi/dram_cubieboard.c
+--- u-boot-2014.04/board/sunxi/dram_cubieboard.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_cubieboard.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5290,9 +4527,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard.c u-boot-sunxi/board/su
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/sunxi/dram_cubietruck.c
---- u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_cubietruck.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/sunxi/dram_cubietruck.c
+--- u-boot-2014.04/board/sunxi/dram_cubietruck.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_cubietruck.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5303,8 +4540,8 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/su
 +	.clock = 432,
 +	.type = 3,
 +	.rank_num = 1,
-+	.density = 8192,
-+	.io_width = 16,
++	.density = 4096,
++	.io_width = 8,
 +	.bus_width = 32,
 +	.cas = 9,
 +	.zq = 0x7f,
@@ -5325,9 +4562,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/su
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c u-boot-sunxi/board/sunxi/dram_eoma68_a20.c
---- u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_eoma68_a20.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/dram_eu3000.c
+--- u-boot-2014.04/board/sunxi/dram_eu3000.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_eu3000.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5335,21 +4572,21 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c u-boot-sunxi/board/su
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 384,
++	.clock = 432,
 +	.type = 3,
 +	.rank_num = 1,
 +	.density = 4096,
 +	.io_width = 16,
 +	.bus_width = 32,
 +	.cas = 9,
-+	.zq = 0x7f,
++	.zq = 0x7b,
 +	.odt_en = 0,
 +	.size = 1024,
 +	.tpr0 = 0x42d899b7,
 +	.tpr1 = 0xa090,
 +	.tpr2 = 0x22a00,
 +	.tpr3 = 0,
-+	.tpr4 = 0,
++	.tpr4 = 1,
 +	.tpr5 = 0,
 +	.emr1 = 0x4,
 +	.emr2 = 0x10,
@@ -5360,9 +4597,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c u-boot-sunxi/board/su
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/dram_eu3000.c
---- u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_eu3000.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_forfun_q88db.c u-boot-sunxi/board/sunxi/dram_forfun_q88db.c
+--- u-boot-2014.04/board/sunxi/dram_forfun_q88db.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_forfun_q88db.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5370,21 +4607,21 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/
 +#include <asm/arch/dram.h>
 +
 +static struct dram_para dram_para = {
-+	.clock = 432,
++	.clock = 384,
 +	.type = 3,
 +	.rank_num = 1,
 +	.density = 4096,
 +	.io_width = 16,
-+	.bus_width = 32,
++	.bus_width = 16,
 +	.cas = 9,
 +	.zq = 0x7b,
 +	.odt_en = 0,
-+	.size = 1024,
++	.size = 512,
 +	.tpr0 = 0x42d899b7,
 +	.tpr1 = 0xa090,
 +	.tpr2 = 0x22a00,
 +	.tpr3 = 0,
-+	.tpr4 = 1,
++	.tpr4 = 0,
 +	.tpr5 = 0,
 +	.emr1 = 0x4,
 +	.emr2 = 0x10,
@@ -5395,9 +4632,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_gooseberry_a721.c u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c
---- u-boot-2014.01-rc1/board/sunxi/dram_gooseberry_a721.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_gooseberry_a721.c u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c
+--- u-boot-2014.04/board/sunxi/dram_gooseberry_a721.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5430,9 +4667,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_gooseberry_a721.c u-boot-sunxi/boa
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_h6.c u-boot-sunxi/board/sunxi/dram_h6.c
---- u-boot-2014.01-rc1/board/sunxi/dram_h6.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_h6.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_h6.c u-boot-sunxi/board/sunxi/dram_h6.c
+--- u-boot-2014.04/board/sunxi/dram_h6.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_h6.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5465,9 +4702,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_h6.c u-boot-sunxi/board/sunxi/dram
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_hackberry.c u-boot-sunxi/board/sunxi/dram_hackberry.c
---- u-boot-2014.01-rc1/board/sunxi/dram_hackberry.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_hackberry.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_hackberry.c u-boot-sunxi/board/sunxi/dram_hackberry.c
+--- u-boot-2014.04/board/sunxi/dram_hackberry.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_hackberry.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5500,9 +4737,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_hackberry.c u-boot-sunxi/board/sun
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_inet_k70hc.c u-boot-sunxi/board/sunxi/dram_inet_k70hc.c
---- u-boot-2014.01-rc1/board/sunxi/dram_inet_k70hc.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_inet_k70hc.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_icou_fatty_i.c u-boot-sunxi/board/sunxi/dram_icou_fatty_i.c
+--- u-boot-2014.04/board/sunxi/dram_icou_fatty_i.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_icou_fatty_i.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 384,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 1,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_inet_k70hc.c u-boot-sunxi/board/sunxi/dram_inet_k70hc.c
+--- u-boot-2014.04/board/sunxi/dram_inet_k70hc.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_inet_k70hc.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5535,9 +4807,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_inet_k70hc.c u-boot-sunxi/board/su
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_megafeis_a08.c u-boot-sunxi/board/sunxi/dram_megafeis_a08.c
---- u-boot-2014.01-rc1/board/sunxi/dram_megafeis_a08.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_megafeis_a08.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_linksprite_pcduino3.c u-boot-sunxi/board/sunxi/dram_linksprite_pcduino3.c
+--- u-boot-2014.04/board/sunxi/dram_linksprite_pcduino3.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_linksprite_pcduino3.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 480,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7a,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0x0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_megafeis_a08.c u-boot-sunxi/board/sunxi/dram_megafeis_a08.c
+--- u-boot-2014.04/board/sunxi/dram_megafeis_a08.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_megafeis_a08.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5570,9 +4877,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_megafeis_a08.c u-boot-sunxi/board/
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mini_x_a10s.c u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c
---- u-boot-2014.01-rc1/board/sunxi/dram_mini_x_a10s.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_merrii_m2.c u-boot-sunxi/board/sunxi/dram_merrii_m2.c
+--- u-boot-2014.04/board/sunxi/dram_merrii_m2.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_merrii_m2.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 432,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 127,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0x0,
++	.tpr4 = 0x0,
++	.tpr5 = 0x0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0x0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_mini_x_a10s.c u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c
+--- u-boot-2014.04/board/sunxi/dram_mini_x_a10s.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5605,9 +4947,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mini_x_a10s.c u-boot-sunxi/board/s
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802_a10s.c u-boot-sunxi/board/sunxi/dram_mk802_a10s.c
---- u-boot-2014.01-rc1/board/sunxi/dram_mk802_a10s.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_mk802_a10s.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_mk802_a10s.c u-boot-sunxi/board/sunxi/dram_mk802_a10s.c
+--- u-boot-2014.04/board/sunxi/dram_mk802_a10s.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_mk802_a10s.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5640,9 +4982,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802_a10s.c u-boot-sunxi/board/su
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802ii_a20.c u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c
---- u-boot-2014.01-rc1/board/sunxi/dram_mk802ii_a20.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_mk802ii_a20.c u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c
+--- u-boot-2014.04/board/sunxi/dram_mk802ii_a20.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5675,9 +5017,45 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802ii_a20.c u-boot-sunxi/board/s
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2.c u-boot-sunxi/board/sunxi/dram_pov_protab2.c
---- u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_pov_protab2.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_olimex_a13_som.c u-boot-sunxi/board/sunxi/dram_olimex_a13_som.c
+--- u-boot-2014.04/board/sunxi/dram_olimex_a13_som.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_olimex_a13_som.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,32 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 408,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 123,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0,
++	.emr2 = 0x10,
++	.emr3 = 0,
++
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_pov_protab2.c u-boot-sunxi/board/sunxi/dram_pov_protab2.c
+--- u-boot-2014.04/board/sunxi/dram_pov_protab2.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_pov_protab2.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5710,9 +5088,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2.c u-boot-sunxi/board/s
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2_xxl.c u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c
---- u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2_xxl.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_pov_protab2_xxl.c u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c
+--- u-boot-2014.04/board/sunxi/dram_pov_protab2_xxl.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5745,9 +5123,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2_xxl.c u-boot-sunxi/boa
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_r7dongle.c u-boot-sunxi/board/sunxi/dram_r7dongle.c
---- u-boot-2014.01-rc1/board/sunxi/dram_r7dongle.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_r7dongle.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_pov_tab_p703.c u-boot-sunxi/board/sunxi/dram_pov_tab_p703.c
+--- u-boot-2014.04/board/sunxi/dram_pov_tab_p703.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_pov_tab_p703.c	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 360,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 0x56b9697b,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_r7dongle.c u-boot-sunxi/board/sunxi/dram_r7dongle.c
+--- u-boot-2014.04/board/sunxi/dram_r7dongle.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_r7dongle.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5780,9 +5193,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_r7dongle.c u-boot-sunxi/board/sunx
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sanei_n90.c u-boot-sunxi/board/sunxi/dram_sanei_n90.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sanei_n90.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sanei_n90.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sanei_n90.c u-boot-sunxi/board/sunxi/dram_sanei_n90.c
+--- u-boot-2014.04/board/sunxi/dram_sanei_n90.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sanei_n90.c	2014-09-06 16:58:36.161953116 +0200
 @@ -0,0 +1,30 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5814,9 +5227,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sanei_n90.c u-boot-sunxi/board/sun
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_312_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_312_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_semitime_g2.c u-boot-sunxi/board/sunxi/dram_semitime_g2.c
+--- u-boot-2014.04/board/sunxi/dram_semitime_g2.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_semitime_g2.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 432,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7b,
++	.odt_en = 0,
++	.size = 1024, /* in MiB */
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0x00,
++	.tpr4 = 0x00,
++	.tpr5 = 0x00,
++	.emr1 = 0x00,
++	.emr2 = 0x10,
++	.emr3 = 0x00,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_312_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_312_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5849,9 +5297,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_312_1024_iow8.c u-boot-sunxi
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5884,9 +5332,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow16.c u-boot-sunx
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5919,9 +5367,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow8.c u-boot-sunxi
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_512.c u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_512.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_512.c u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_360_512.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5954,9 +5402,44 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_512.c u-boot-sunxi/board
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_384_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_384_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c	2014-03-05 23:14:47.908090095 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 384,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 6,
++	.zq = 123,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x30926692,
++	.tpr1 = 0x1090,
++	.tpr2 = 0x1a0c8,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -5989,9 +5472,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_384_1024_iow8.c u-boot-sunxi
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6024,9 +5507,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow16.c u-boot-sunx
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow8.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6059,9 +5542,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow8.c u-boot-sunxi
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_512.c u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c
---- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_512.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_512.c u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c
+--- u-boot-2014.04/board/sunxi/dram_sun4i_408_512.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6094,9 +5577,324 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_512.c u-boot-sunxi/board
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_wobo_i5.c u-boot-sunxi/board/sunxi/dram_wobo_i5.c
---- u-boot-2014.01-rc1/board/sunxi/dram_wobo_i5.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_wobo_i5.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun5i_408_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun5i_408_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun5i_408_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 408,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7b,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_408_512_busw16_iow8.c u-boot-sunxi/board/sunxi/dram_sun5i_408_512_busw16_iow8.c
+--- u-boot-2014.04/board/sunxi/dram_sun5i_408_512_busw16_iow8.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun5i_408_512_busw16_iow8.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 408,
++	.type = 3,
++	.rank_num = 1,
++	.density = 2048,
++	.io_width = 8,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 123,
++	.odt_en = 1,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_432_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun5i_432_512_busw16_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun5i_432_512_busw16_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun5i_432_512_busw16_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 432,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 123,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_360_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_360_512_busw16_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun7i_360_512_busw16_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun7i_360_512_busw16_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 360,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_384_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_384_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun7i_384_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun7i_384_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 384,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_384_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun7i_384_512_busw16_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun7i_384_512_busw16_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 384,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_432_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_432_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun7i_432_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun7i_432_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 432,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 1,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_460_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_460_1024_iow16.c
+--- u-boot-2014.04/board/sunxi/dram_sun7i_460_1024_iow16.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_sun7i_460_1024_iow16.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include <common.h>
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 480,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 0,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0x0,
++	.tpr4 = 0x1,
++	.tpr5 = 0x0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0x0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_wexler_tab_7200.c u-boot-sunxi/board/sunxi/dram_wexler_tab_7200.c
+--- u-boot-2014.04/board/sunxi/dram_wexler_tab_7200.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_wexler_tab_7200.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,31 @@
++/* this file is generated, don't edit it yourself */
++
++#include "common.h"
++#include <asm/arch/dram.h>
++
++static struct dram_para dram_para = {
++	.clock = 384,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 32,
++	.cas = 9,
++	.zq = 0x7f,
++	.odt_en = 1,
++	.size = 1024,
++	.tpr0 = 0x42d899b7,
++	.tpr1 = 0xa090,
++	.tpr2 = 0x22a00,
++	.tpr3 = 0,
++	.tpr4 = 1,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0x10,
++	.emr3 = 0,
++};
++
++unsigned long sunxi_dram_init(void)
++{
++	return dramc_init(&dram_para);
++}
+diff -ruN u-boot-2014.04/board/sunxi/dram_wobo_i5.c u-boot-sunxi/board/sunxi/dram_wobo_i5.c
+--- u-boot-2014.04/board/sunxi/dram_wobo_i5.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_wobo_i5.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6129,9 +5927,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_wobo_i5.c u-boot-sunxi/board/sunxi
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_xzpad700.c u-boot-sunxi/board/sunxi/dram_xzpad700.c
---- u-boot-2014.01-rc1/board/sunxi/dram_xzpad700.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_xzpad700.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_xzpad700.c u-boot-sunxi/board/sunxi/dram_xzpad700.c
+--- u-boot-2014.04/board/sunxi/dram_xzpad700.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_xzpad700.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6164,9 +5962,9 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_xzpad700.c u-boot-sunxi/board/sunx
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_zatab.c u-boot-sunxi/board/sunxi/dram_zatab.c
---- u-boot-2014.01-rc1/board/sunxi/dram_zatab.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/dram_zatab.c	2014-03-05 23:14:47.912090042 +0100
+diff -ruN u-boot-2014.04/board/sunxi/dram_zatab.c u-boot-sunxi/board/sunxi/dram_zatab.c
+--- u-boot-2014.04/board/sunxi/dram_zatab.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/dram_zatab.c	2014-09-06 16:58:36.165953115 +0200
 @@ -0,0 +1,31 @@
 +/* this file is generated, don't edit it yourself */
 +
@@ -6199,10 +5997,57 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_zatab.c u-boot-sunxi/board/sunxi/d
 +{
 +	return dramc_init(&dram_para);
 +}
-diff -ruN u-boot-2014.01-rc1/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makefile
---- u-boot-2014.01-rc1/board/sunxi/Makefile	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/board/sunxi/Makefile	2014-03-05 23:14:47.908090095 +0100
-@@ -0,0 +1,85 @@
+diff -ruN u-boot-2014.04/board/sunxi/gmac.c u-boot-sunxi/board/sunxi/gmac.c
+--- u-boot-2014.04/board/sunxi/gmac.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/gmac.c	2014-09-06 16:58:36.165953115 +0200
+@@ -0,0 +1,43 @@
++#include <common.h>
++#include <netdev.h>
++#include <miiphy.h>
++#include <asm/gpio.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/gpio.h>
++
++int sunxi_gmac_initialize(bd_t *bis)
++{
++	int pin;
++	struct sunxi_ccm_reg *const ccm =
++		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++	/* Set up clock gating */
++	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
++
++	/* Set MII clock */
++#ifdef CONFIG_RGMII
++	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
++		CCM_GMAC_CTRL_GPIT_RGMII);
++#else
++	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
++		CCM_GMAC_CTRL_GPIT_MII);
++#endif
++
++	/* Configure pin mux settings for GMAC */
++	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
++#ifdef CONFIG_RGMII
++		/* skip unused pins in RGMII mode */
++		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
++			continue;
++#endif
++		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
++		sunxi_gpio_set_drv(pin, 3);
++	}
++
++#ifdef CONFIG_RGMII
++	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
++#else
++	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
++#endif
++}
+diff -ruN u-boot-2014.04/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makefile
+--- u-boot-2014.04/board/sunxi/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/board/sunxi/Makefile	2014-09-06 16:58:36.161953116 +0200
+@@ -0,0 +1,95 @@
 +#
 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 +#
@@ -6211,36 +6056,24 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makef
 +# (C) Copyright 2000-2003
 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 +#
-+# See file CREDITS for list of people who contributed to this
-+# project.
++# SPDX-License-Identifier:	GPL-2.0+
 +#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
 +obj-y	+= board.o
++obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
 +obj-$(CONFIG_A10_MID_1GB)	+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_A10_OLINUXINO_L)	+= dram_a10_olinuxino_l.o
-+obj-$(CONFIG_A10S_OLINUXINO_M)	+= dram_a10s_olinuxino_m.o
++obj-$(CONFIG_A10S_OLINUXINO_M)	+= dram_sun5i_432_512_busw16_iow16.o
 +obj-$(CONFIG_A13_OLINUXINO)	+= dram_a13_olinuxino.o
 +obj-$(CONFIG_A13_OLINUXINOM)	+= dram_a13_oli_micro.o
-+obj-$(CONFIG_A13_MID)		+= dram_a13_mid.o
-+obj-$(CONFIG_A20_OLINUXINO_M)	+= dram_a20_olinuxino_m.o
++obj-$(CONFIG_A13_MID)		+= dram_sun5i_408_512_busw16_iow8.o
++obj-$(CONFIG_A20_OLINUXINO_L)	+= dram_a20_olinuxino_l.o
++obj-$(CONFIG_A20_OLINUXINO_L2)	+= dram_a20_olinuxino_l2.o
++obj-$(CONFIG_A20_OLINUXINO_M)	+= dram_sun7i_384_1024_iow16.o
++obj-$(CONFIG_A20_SOM)		+= dram_sun7i_384_1024_iow16.o
++obj-$(CONFIG_AINOL_AW1)		+= dram_ainol_aw1.o
++obj-$(CONFIG_AMPE_A76)		+= dram_sun5i_432_512_busw16_iow16.o
 +obj-$(CONFIG_AUXTEK_T003)	+= dram_auxtek_t003.o
-+# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
-+obj-$(CONFIG_AUXTEK_T004)	+= dram_a10s_olinuxino_m.o
++obj-$(CONFIG_AUXTEK_T004)	+= dram_sun5i_432_512_busw16_iow16.o
 +obj-$(CONFIG_BA10_TV_BOX)	+= dram_sun4i_384_1024_iow8.o
 +obj-$(CONFIG_COBY_MID7042)	+= dram_sun4i_408_1024_iow16.o
 +obj-$(CONFIG_COBY_MID8042)	+= dram_sun4i_360_1024_iow16.o
@@ -6248,51 +6081,73 @@ diff -ruN u-boot-2014.01-rc1/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makef
 +obj-$(CONFIG_MARSBOARD_A10)	+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_MARSBOARD_A20)	+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_CUBIEBOARD)	+= dram_cubieboard.o
-+obj-$(CONFIG_CUBIEBOARD_512)	+= dram_cubieboard_512.o
-+obj-$(CONFIG_CUBIEBOARD2)	+= dram_cubieboard2.o
++obj-$(CONFIG_CUBIEBOARD2)	+= dram_sun7i_460_1024_iow16.o
++obj-$(CONFIG_BANANAPI)		+= dram_sun7i_432_1024_iow16.o
 +obj-$(CONFIG_CUBIETRUCK)	+= dram_cubietruck.o
 +obj-$(CONFIG_DNS_M82)		+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_EOMA68_A10)	+= dram_sun4i_360_1024_iow8.o
-+obj-$(CONFIG_EOMA68_A20)	+= dram_eoma68_a20.o
++obj-$(CONFIG_EOMA68_A20)	+= dram_sun7i_384_1024_iow16.o
 +obj-$(CONFIG_EU3000)		+= dram_eu3000.o
++obj-$(CONFIG_FORFUN_Q88DB)	+= dram_forfun_q88db.o
 +obj-$(CONFIG_GOOSEBERRY_A721)	+= dram_gooseberry_a721.o
 +obj-$(CONFIG_H6)		+= dram_h6.o
-+obj-$(CONFIG_HACKBERRY)	+= dram_hackberry.o
++obj-$(CONFIG_HACKBERRY)		+= dram_hackberry.o
++obj-$(CONFIG_HBD_MID_S906)	+= dram_sun7i_432_1024_iow16.o
++obj-$(CONFIG_HCORE_HC860)	+= dram_sun4i_384_1024_iow16.o
++obj-$(CONFIG_HYUNDAI_A7)	+= dram_sun4i_360_512.o
 +obj-$(CONFIG_A7HD)		+= dram_sun4i_360_1024_iow8.o
++obj-$(CONFIG_I12_TVBOX)		+= dram_sun7i_384_1024_iow16.o
++obj-$(CONFIG_ICOU_FATTY_I)	+= dram_icou_fatty_i.o
 +obj-$(CONFIG_INTERRA3)		+= dram_mk802ii_a20.o
-+obj-$(CONFIG_INET_86VZ)         += dram_a10s_olinuxino_m.o
++obj-$(CONFIG_INET_86VZ)		+= dram_sun5i_432_512_busw16_iow16.o
 +obj-$(CONFIG_INET97F_II)	+= dram_sun4i_408_512.o
 +obj-$(CONFIG_INET_K70HC)	+= dram_inet_k70hc.o
++obj-$(CONFIG_ITEADA10)		+= dram_cubieboard.o
++obj-$(CONFIG_ITEADA20)		+= dram_sun7i_460_1024_iow16.o
 +obj-$(CONFIG_JESURUN_Q5)	+= dram_sun4i_312_1024_iow8.o
-+obj-$(CONFIG_K1001L1C)	+= dram_a20_olinuxino_m.o
++obj-$(CONFIG_K1001L1C)		+= dram_sun7i_384_1024_iow16.o
++obj-$(CONFIG_KURIO_7S)		+= dram_sun7i_432_1024_iow16.o
++obj-$(CONFIG_LANGCENT_H6S)	+= dram_sun7i_360_512_busw16_iow16.o
++obj-$(CONFIG_LINKSPRITE_PCDUINO3)	+= dram_linksprite_pcduino3.o
 +obj-$(CONFIG_MEFAFEIS_A08)	+= dram_megafeis_a08.o
 +obj-$(CONFIG_MELE_A1000)	+= dram_sun4i_360_512.o
 +obj-$(CONFIG_MELE_A1000G)	+= dram_sun4i_360_1024_iow8.o
 +obj-$(CONFIG_MELE_A3700)	+= dram_sun4i_360_1024_iow8.o
++obj-$(CONFIG_MERRII_HUMMINGBIRD_A20)	+= dram_sun7i_460_1024_iow16.o
 +obj-$(CONFIG_MINI_X)		+= dram_sun4i_360_512.o
 +obj-$(CONFIG_MINI_X_1GB)	+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_MINI_X_A10S)	+= dram_mini_x_a10s.o
 +obj-$(CONFIG_MK802)		+= dram_sun4i_360_512.o
-+obj-$(CONFIG_MK802_1GB)	+= dram_sun4i_360_1024_iow16.o
++obj-$(CONFIG_MK802_1GB)		+= dram_sun4i_360_1024_iow16.o
 +obj-$(CONFIG_MK802_A10S)	+= dram_mk802_a10s.o
 +obj-$(CONFIG_MK802II)		+= dram_sun4i_408_1024_iow8.o
-+obj-$(CONFIG_MK802II_A20)		+= dram_mk802ii_a20.o
++obj-$(CONFIG_MK802II_A20)	+= dram_mk802ii_a20.o
++obj-$(CONFIG_MK808C_A20)	+= dram_sun7i_384_1024_iow16.o
++obj-$(CONFIG_OLIMEX_A13_SOM)	+= dram_olimex_a13_som.o
 +obj-$(CONFIG_PCDUINO)		+= dram_sun4i_408_1024_iow8.o
 +obj-$(CONFIG_PENGPOD700)	+= dram_sun4i_384_1024_iow8.o
 +obj-$(CONFIG_PENGPOD1000)	+= dram_sun4i_408_1024_iow16.o
++obj-$(CONFIG_PINERIVER-H25)	+= dram_sun5i_408_1024_iow16.o
++obj-$(CONFIG_POV_TAB_P703)	+= dram_pov_tab_p703.o
 +obj-$(CONFIG_POV_PROTAB2)	+= dram_pov_protab2.o
 +obj-$(CONFIG_POV_PROTAB2_XXL)	+= dram_pov_protab2_xxl.o
-+obj-$(CONFIG_R7DONGLE)	+= dram_r7dongle.o
-+obj-$(CONFIG_SANEI_N90)	+= dram_sanei_n90.o
-+obj-$(CONFIG_UHOST_U1A)	+= dram_sun4i_360_1024_iow8.o
++obj-$(CONFIG_QT840A)		+= dram_sun7i_384_512_busw16_iow16.o
++obj-$(CONFIG_R7DONGLE)		+= dram_r7dongle.o
++obj-$(CONFIG_SANEI_N90)		+= dram_sanei_n90.o
++obj-$(CONFIG_SEMITIME_G2)	+= dram_semitime_g2.o
++obj-$(CONFIG_TZX_Q8_713B6)	+= dram_sun5i_408_512_busw16_iow8.o
++obj-$(CONFIG_TZX_Q8_713B7)	+= dram_sun5i_408_512_busw16_iow8.o
++obj-$(CONFIG_UHOST_U1A)		+= dram_sun4i_360_1024_iow8.o
++obj-$(CONFIG_WEXLER_TAB_7200)	+= dram_wexler_tab_7200.o
 +obj-$(CONFIG_WOBO_I5)		+= dram_wobo_i5.o
-+obj-$(CONFIG_XZPAD700)	+= dram_xzpad700.o
++obj-$(CONFIG_XZPAD700)		+= dram_xzpad700.o
 +obj-$(CONFIG_ZATAB)		+= dram_zatab.o
-diff -ruN u-boot-2014.01-rc1/boards.cfg u-boot-sunxi/boards.cfg
---- u-boot-2014.01-rc1/boards.cfg	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/boards.cfg	2014-03-05 23:14:47.948089561 +0100
-@@ -344,6 +344,82 @@
- Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
++obj-$(CONFIG_MERRII_M2)		+= dram_merrii_m2.o
+diff -ruN u-boot-2014.04/boards.cfg u-boot-sunxi/boards.cfg
+--- u-boot-2014.04/boards.cfg	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/boards.cfg	2014-09-06 16:58:36.185953115 +0200
+@@ -371,6 +371,111 @@
+ Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
  Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
  Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
 +Active  arm         armv7          sunxi       -               sunxi               A10_MID_1GB                          sun4i:A10_MID_1GB,SPL                                                                                                             -
@@ -6305,21 +6160,30 @@ diff -ruN u-boot-2014.01-rc1/boards.cfg u-boot-sunxi/boards.cfg
 +Active  arm         armv7          sunxi       -               sunxi               A13-OLinuXinoM                       sun5i:A13_OLINUXINOM,SPL,NO_AXP,STATUSLED=201,CONS_INDEX=2                                                                        -
 +Active  arm         armv7          sunxi       -               sunxi               A13-OLinuXinoM_FEL                   sun5i:A13_OLINUXINOM,SPL_FEL,NO_AXP,STATUSLED=201,CONS_INDEX=2                                                                    -
 +Active  arm         armv7          sunxi       -               sunxi               A13_MID                              sun5i:A13_MID,SPL,CONS_INDEX=2                                                                                                    -
-+Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_MICRO                  sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_GMAC,FAST_MBUS                                                         -
-+Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_MICRO_FEL              sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL_FEL,SUNXI_GMAC,FAST_MBUS                                                     -
++Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_Lime                   sun7i:A20_OLINUXINO_L,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_EMAC                                                                   -
++Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_Lime2                  sun7i:A20_OLINUXINO_L2,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_GMAC                                                                  -
++Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_MICRO                  sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_EMAC                                                                   -
++Active  arm         armv7          sunxi       -               sunxi               A20-OLinuXino_MICRO_FEL              sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL_FEL,SUNXI_EMAC                                                               -
++Active  arm         armv7          sunxi       -               sunxi               A20-SOM                              sun7i:A20_SOM,SPL,SUNXI_GMAC,RGMII,STATUSLED1=245,FAST_MBUS                                                                       -
++Active  arm         armv7          sunxi       -               sunxi               Ainol_AW1                            sun7i:AINOL_AW1,SPL                                                                                                               -
++Active  arm         armv7          sunxi       -               sunxi               Ampe_A76                             sun5i:AMPE_A76,SPL,CONS_INDEX=2                                                                                                   -
 +Active  arm         armv7          sunxi       -               sunxi               Auxtek-T003                          sun5i:AUXTEK_T003,SPL,AXP152_POWER,STATUSLED=34                                                                                   -
 +Active  arm         armv7          sunxi       -               sunxi               Auxtek-T004                          sun5i:AUXTEK_T004,SPL,AXP152_POWER,STATUSLED=34                                                                                   -
 +Active  arm         armv7          sunxi       -               sunxi               ba10_tv_box                          sun4i:BA10_TV_BOX,SPL,SUNXI_EMAC                                                                                                  -
++Active  arm         armv7          sunxi       -               sunxi               Bananapi                             sun7i:BANANAPI,SPL,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),STATUSLED=244,STATUSLED1=245,FAST_MBUS                                   -
++Active  arm         armv7          sunxi       -               sunxi               Bananapi_FEL                         sun7i:BANANAPI,SPL_FEL,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),STATUSLED=244,STATUSLED1=245,FAST_MBUS                               -
 +Active  arm         armv7          sunxi       -               sunxi               Coby_MID7042                         sun4i:COBY_MID7042,SPL                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               Coby_MID8042                         sun4i:COBY_MID8042,SPL                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               Coby_MID9742                         sun4i:COBY_MID9742,SPL                                                                                                            -
-+Active  arm         armv7          sunxi       -               sunxi               Colombus                             sun6i:COLOMBUS                                                                                                                    -
++Active  arm         armv7          sunxi       -               sunxi               Iteaduino_Plus_A10                   sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245                                                                        -
++Active  arm         armv7          sunxi       -               sunxi               Iteaduino_Plus_A20                   sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245                                                                        -
++Active  arm         armv7          sunxi       -               sunxi               Colombus                             sun6i:COLOMBUS,AXP221_POWER,ENABLE_DLDO1_POWER                                                                                    -
++Active  arm         armv7          sunxi       -               sunxi               Ippo_q8h                             sun8i:IPPO_Q8H,NO_AXP,CONS_INDEX=5                                                                                                -
 +Active  arm         armv7          sunxi       -               sunxi               Cubieboard                           sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245                                                                      -
 +Active  arm         armv7          sunxi       -               sunxi               Cubieboard2                          sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS                                                           -
 +Active  arm         armv7          sunxi       -               sunxi               Cubieboard2_FEL                      sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS                                                       -
 +Active  arm         armv7          sunxi       -               sunxi               Cubietruck                           sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS                        -
 +Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                       sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS                    -
-+Active  arm         armv7          sunxi       -               sunxi               Cubieboard_512                       sun4i:CUBIEBOARD_512,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               Cubieboard_FEL                       sun4i:CUBIEBOARD,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               DNS_M82                              sun4i:DNS_M82,SPL                                                                                                                 -
 +Active  arm         armv7          sunxi       -               sunxi               EOMA68_A10                           sun4i:EOMA68_A10,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC                                                                                  -
@@ -6327,10 +6191,16 @@ diff -ruN u-boot-2014.01-rc1/boards.cfg u-boot-sunxi/boards.cfg
 +Active  arm         armv7          sunxi       -               sunxi               EOMA68_A20                           sun7i:EOMA68_A20,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC                                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               EOMA68_A20_FEL                       sun7i:EOMA68_A20,SPL_FEL,MMC_SUNXI_SLOT=3,SUNXI_EMAC                                                                              -
 +Active  arm         armv7          sunxi       -               sunxi               EU3000                               sun7i:EU3000,SPL                                                                                                                  -
++Active  arm         armv7          sunxi       -               sunxi               Forfun_Q88DB                         sun7i:FORFUN_Q88DB,SPL                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               Gooseberry_A721                      sun4i:GOOSEBERRY_A721,SPL                                                                                                         -
 +Active  arm         armv7          sunxi       -               sunxi               H6                                   sun4i:H6,SPL                                                                                                                      -
-+Active  arm         armv7          sunxi       -               sunxi               Hackberry                            sun4i:HACKBERRY,SPL                                                                                                               -
++Active  arm         armv7          sunxi       -               sunxi               Hackberry                            sun4i:HACKBERRY,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(19)                                                                               -
++Active  arm         armv7          sunxi       -               sunxi               HBD_MID_S906                         sun7i:HBD_MID_S906,SPL                                                                                                            -
++Active  arm         armv7          sunxi       -               sunxi               HCore_HC860                          sun4i:HCORE_HC860,SPL                                                                                                             -
++Active  arm         armv7          sunxi       -               sunxi               Hyundai_A7                           sun4i:HYUNDAI_A7,SPL                                                                                                              -
 +Active  arm         armv7          sunxi       -               sunxi               Hyundai_A7HD                         sun4i:A7HD,SPL                                                                                                                    -
++Active  arm         armv7          sunxi       -               sunxi               i12-tvbox                            sun7i:I12_TVBOX,SPL,FAST_MBUS,STATUSLED=244                                                                                       -
++Active  arm         armv7          sunxi       -               sunxi               ICOU_Fatty_I                         sun7i:ICOU_FATTY_I,SPL                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               Interra-3                            sun7i:INTERRA3,SPL,SUNXI_GMAC,FAST_MBUS,MMC_SUNXI_SLOT=2                                                                          -
 +Active  arm         armv7          sunxi       -               sunxi               INet_86VZ                            sun5i:INET_86VZ,SPL														  -
 +Active  arm         armv7          sunxi       -               sunxi               INet_86VZ_FEL                        sun5i:INET_86VZ,SPL_FEL,UART0_PORT_F                                                                                              -
@@ -6338,160 +6208,60 @@ diff -ruN u-boot-2014.01-rc1/boards.cfg u-boot-sunxi/boards.cfg
 +Active  arm         armv7          sunxi       -               sunxi               INet_K70HC                           sun7i:INET_K70HC,SPL                                                                                                              -
 +Active  arm         armv7          sunxi       -               sunxi               Jesurun-Q5                           sun4i:JESURUN_Q5,SPL,SUNXI_EMAC,STATUSLED=244                                                                                     -
 +Active  arm         armv7          sunxi       -               sunxi               K1001L1C                             sun7i:K1001L1C,SPL                                                                                                                -
++Active  arm         armv7          sunxi       -               sunxi               Kurio_7S                             sun7i:KURIO_7S,SPL                                                                                                                -
++Active  arm         armv7          sunxi       -               sunxi               Langcent_H6S                         sun7i:LANGCENT_H6S,SPL                                                                                                            -
++Active  arm         armv7          sunxi       -               sunxi               Linksprite_pcDuino3                  sun7i:LINKSPRITE_PCDUINO3,SPL,SUNXI_GMAC,FAST_MBUS                                                                                -
 +Active  arm         armv7          sunxi       -               sunxi               Marsboard_A10                        sun4i:MARSBOARD_A10,SPL,SUNXI_EMAC,NO_AXP                                                                                         -
 +Active  arm         armv7          sunxi       -               sunxi               Marsboard_A20                        sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP                                                                                         -
 +Active  arm         armv7          sunxi       -               sunxi               Marsboard_A20_debug                  sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP,SYS_SECONDARY_ON                                                                        -
 +Active  arm         armv7          sunxi       -               sunxi               Megafeis_A08                         sun5i:MEFAFEIS_A08,SPL                                                                                                            -
-+Active  arm         armv7          sunxi       -               sunxi               Mele_A1000                           sun4i:MELE_A1000,SPL,SUNXI_EMAC,STATUSLED=234                                                                                     -
-+Active  arm         armv7          sunxi       -               sunxi               Mele_A1000_FEL                       sun4i:MELE_A1000,SPL_FEL,SUNXI_EMAC,STATUSLED=234                                                                                 -
-+Active  arm         armv7          sunxi       -               sunxi               Mele_A1000G                          sun4i:MELE_A1000G,SPL,SUNXI_EMAC,STATUSLED=234                                                                                    -
-+Active  arm         armv7          sunxi       -               sunxi               Mele_A3700                           sun4i:MELE_A3700,SPL,SUNXI_EMAC,STATUSLED=234                                                                                     -
++Active  arm         armv7          sunxi       -               sunxi               Mele_A1000                           sun4i:MELE_A1000,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234                                                                -
++Active  arm         armv7          sunxi       -               sunxi               Mele_A1000_FEL                       sun4i:MELE_A1000,SPL_FEL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234                                                            -
++Active  arm         armv7          sunxi       -               sunxi               Mele_A1000G                          sun4i:MELE_A1000G,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234                                                               -
++Active  arm         armv7          sunxi       -               sunxi               Mele_A3700                           sun4i:MELE_A3700,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234                                                                -
++Active  arm         armv7          sunxi       -               sunxi               Merrii_Hummingbird_A20               sun7i:MERRII_HUMMINGBIRD_A20,SPL                                                                                                  -
++Active  arm         armv7          sunxi       -               sunxi               merrii_m2                            sun7i:MERRII_M2,SPL,SUNXI_EMAC                                                                                                    -
 +Active  arm         armv7          sunxi       -               sunxi               Mini-X                               sun4i:MINI_X,SPL                                                                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               Mini-X-1Gb                           sun4i:MINI_X_1GB,SPL                                                                                                              -
 +Active  arm         armv7          sunxi       -               sunxi               Mini-X_A10s                          sun5i:MINI_X_A10S,SPL                                                                                                             -
 +Active  arm         armv7          sunxi       -               sunxi               mk802                                sun4i:MK802,SPL,NO_AXP                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               mk802-1gb                            sun4i:MK802_1GB,SPL,NO_AXP                                                                                                        -
 +Active  arm         armv7          sunxi       -               sunxi               mk802_a10s                           sun5i:MK802_A10S,SPL,AXP152_POWER,STATUSLED=34                                                                                    -
-+Active  arm         armv7          sunxi       -               sunxi               mk802ii_A20                              sun7i:MK802II_A20,SPL                                                                                                                 -
++Active  arm         armv7          sunxi       -               sunxi               mk802ii_A20                          sun7i:MK802II_A20,SPL                                                                                                             -
 +Active  arm         armv7          sunxi       -               sunxi               mk802ii                              sun4i:MK802II,SPL                                                                                                                 -
++Active  arm         armv7          sunxi       -               sunxi               mk808c_A20                           sun7i:MK808C_A20,SPL                                                                                                              -
++Active  arm         armv7          sunxi       -               sunxi               OLIMEX-A13-SOM                       sun5i:OLIMEX_A13_SOM,SPL,NO_AXP,STATUSLED=201,CONS_INDEX=2                                                                        -
 +Active  arm         armv7          sunxi       -               sunxi               pcDuino                              sun4i:PCDUINO,SPL,SUNXI_EMAC                                                                                                      -
 +Active  arm         armv7          sunxi       -               sunxi               pengpod1000                          sun4i:PENGPOD1000,SPL                                                                                                             -
 +Active  arm         armv7          sunxi       -               sunxi               pengpod700                           sun4i:PENGPOD700,SPL                                                                                                              -
++Active	arm         armv7          suxni       -               sunxi               pineriver-h25                        sun5i:PINERIVER-H25,SPL
++Active  arm         armv7          sunxi       -               sunxi               POV_TAB_P703                         sun5i:POV_TAB_P703,SPL                                                                                                            -
 +Active  arm         armv7          sunxi       -               sunxi               PoV_ProTab2_IPS9                     sun4i:POV_PROTAB2,SPL                                                                                                             -
 +Active  arm         armv7          sunxi       -               sunxi               PoV_ProTab2_IPS_3g                   sun4i:POV_PROTAB2,SPL                                                                                                             -
 +Active  arm         armv7          sunxi       -               sunxi               PoV_ProTab2_XXL                      sun4i:POV_PROTAB2_XXL,SPL                                                                                                         -
++Active  arm         armv7          sunxi       -               sunxi               qt840a                               sun7i:QT840A,SPL,FAST_MBUS,STATUSLED=244                                                                                          -
 +Active  arm         armv7          sunxi       -               sunxi               r7-tv-dongle                         sun5i:R7DONGLE,SPL,AXP152_POWER,STATUSLED=34                                                                                      -
 +Active  arm         armv7          sunxi       -               sunxi               Sanei_N90                            sun4i:SANEI_N90,SPL                                                                                                               -
++Active  arm         armv7          sunxi       -               sunxi               Semitime_G2                          sun5i:SEMITIME_G2,SPL,AXP152_POWER,STATUSLED=34                                                                                   -
 +Active  arm         armv7          sunxi       -               sunxi               sun4i                                sun4i:SUNXI_EMAC                                                                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               sun4i_sdcon                          sun4i:UART0_PORT_F,SUNXI_EMAC                                                                                                     -
 +Active  arm         armv7          sunxi       -               sunxi               sun5i                                sun5i:SUNXI_EMAC                                                                                                                  -
 +Active  arm         armv7          sunxi       -               sunxi               sun5i_sdcon                          sun5i:UART0_PORT_F,SUNXI_EMAC                                                                                                     -
 +Active  arm         armv7          sunxi       -               sunxi               sun5i_uart1                          sun5i:CONS_INDEX=2,SUNXI_EMAC                                                                                                     -
++Active  arm         armv7          sunxi       -               sunxi               TZX-Q8-713B6                         sun5i:TZX_Q8_713B6,SPL,CONS_INDEX=2                                                                                               -
++Active  arm         armv7          sunxi       -               sunxi               TZX-Q8-713B7                         sun5i:TZX_Q8_713B7,SPL,CONS_INDEX=2                                                                                               -
 +Active  arm         armv7          sunxi       -               sunxi               uhost_u1a                            sun4i:UHOST_U1A,SPL,STATUSLED=34                                                                                                  -
++Active  arm         armv7          sunxi       -               sunxi               Wexler_TAB_7200                      sun7i:WEXLER_TAB_7200,SPL                                                                                                         -
 +Active  arm         armv7          sunxi       -               sunxi               wobo-i5                              sun5i:WOBO_I5,SPL,STATUSLED=34                                                                                                    -
 +Active  arm         armv7          sunxi       -               sunxi               xzpad700                             sun5i:XZPAD700,SPL                                                                                                                -
 +Active  arm         armv7          sunxi       -               sunxi               zatab                                sun4i:ZATAB,SPL                                                                                                                   -
  Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
  Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
  Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
-diff -ruN u-boot-2014.01-rc1/common/cmd_gpio.c u-boot-sunxi/common/cmd_gpio.c
---- u-boot-2014.01-rc1/common/cmd_gpio.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/common/cmd_gpio.c	2014-03-05 23:14:47.952089507 +0100
-@@ -20,6 +20,7 @@
- 	GPIO_SET,
- 	GPIO_CLEAR,
- 	GPIO_TOGGLE,
-+	GPIO_OSCILLATE,
- };
- 
- static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-@@ -48,6 +49,7 @@
- 		case 's': sub_cmd = GPIO_SET;    break;
- 		case 'c': sub_cmd = GPIO_CLEAR;  break;
- 		case 't': sub_cmd = GPIO_TOGGLE; break;
-+		case 'o': sub_cmd = GPIO_OSCILLATE; break;
- 		default:  goto show_usage;
- 	}
- 
-@@ -66,6 +68,14 @@
- 	if (sub_cmd == GPIO_INPUT) {
- 		gpio_direction_input(gpio);
- 		value = gpio_get_value(gpio);
-+	} else if (sub_cmd == GPIO_OSCILLATE) {
-+		int i;
-+		gpio_direction_output(gpio, 0);
-+		for (i = 0; i < 100000000; i++) {
-+			gpio_set_value(gpio, i&1);
-+		}
-+		gpio_direction_input(gpio);
-+		value = 0;
- 	} else {
- 		switch (sub_cmd) {
- 			case GPIO_SET:    value = 1; break;
-diff -ruN u-boot-2014.01-rc1/common/image-fdt.c u-boot-sunxi/common/image-fdt.c
---- u-boot-2014.01-rc1/common/image-fdt.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/common/image-fdt.c	2014-03-05 23:14:47.968089294 +0100
-@@ -445,7 +445,7 @@
- 	return 1;
- }
- 
--__weak int arch_fixup_memory_node(void *blob)
-+__weak int arch_fixup_fdt(void *blob)
- {
- 	return 0;
- }
-@@ -462,7 +462,10 @@
- 		puts(" - must RESET the board to recover.\n");
- 		return -1;
- 	}
--	arch_fixup_memory_node(blob);
-+	if (arch_fixup_fdt(blob) < 0) {
-+		puts("ERROR: arch specific fdt fixup failed");
-+		return -1;
-+	}
- 	if (IMAAGE_OF_BOARD_SETUP)
- 		ft_board_setup(blob, gd->bd);
- 	fdt_fixup_ethernet(blob);
-diff -ruN u-boot-2014.01-rc1/common/memsize.c u-boot-sunxi/common/memsize.c
---- u-boot-2014.01-rc1/common/memsize.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/common/memsize.c	2014-03-05 23:14:47.968089294 +0100
-@@ -21,16 +21,16 @@
-  * the actually available RAM size between addresses `base' and
-  * `base + maxsize'.
-  */
--long get_ram_size(long *base, long maxsize)
-+unsigned long get_ram_size(unsigned long *base, unsigned long maxsize)
- {
--	volatile long *addr;
--	long           save[32];
--	long           cnt;
--	long           val;
--	long           size;
--	int            i = 0;
-+	volatile unsigned long *addr;
-+	unsigned long           save[32];
-+	unsigned long           cnt;
-+	unsigned long           val;
-+	unsigned long           size;
-+	int                     i = 0;
- 
--	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
-+	for (cnt = (maxsize / sizeof (unsigned long)) >> 1; cnt > 0; cnt >>= 1) {
- 		addr = base + cnt;	/* pointer arith! */
- 		sync ();
- 		save[i++] = *addr;
-@@ -50,7 +50,7 @@
- 		 */
- 		sync ();
- 		*addr = save[i];
--		for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
-+		for (cnt = 1; cnt < maxsize / sizeof(unsigned long); cnt <<= 1) {
- 			addr  = base + cnt;
- 			sync ();
- 			*addr = save[--i];
-@@ -58,15 +58,15 @@
- 		return (0);
- 	}
- 
--	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-+	for (cnt = 1; cnt < maxsize / sizeof (unsigned long); cnt <<= 1) {
- 		addr = base + cnt;	/* pointer arith! */
- 		val = *addr;
- 		*addr = save[--i];
- 		if (val != ~cnt) {
--			size = cnt * sizeof (long);
-+			size = cnt * sizeof (unsigned long);
- 			/* Restore the original data before leaving the function.
- 			 */
--			for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-+			for (cnt <<= 1; cnt < maxsize / sizeof (unsigned long); cnt <<= 1) {
- 				addr  = base + cnt;
- 				*addr = save[--i];
- 			}
-diff -ruN u-boot-2014.01-rc1/common/spl/spl_mmc.c u-boot-sunxi/common/spl/spl_mmc.c
---- u-boot-2014.01-rc1/common/spl/spl_mmc.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/common/spl/spl_mmc.c	2014-03-05 23:14:47.968089294 +0100
-@@ -30,8 +30,10 @@
+diff -ruN u-boot-2014.04/common/spl/spl_mmc.c u-boot-sunxi/common/spl/spl_mmc.c
+--- u-boot-2014.04/common/spl/spl_mmc.c	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/common/spl/spl_mmc.c	2014-09-06 16:58:36.205953114 +0200
+@@ -29,8 +29,10 @@
  	if (err == 0)
  		goto end;
  
@@ -6503,18 +6273,18 @@ diff -ruN u-boot-2014.01-rc1/common/spl/spl_mmc.c u-boot-sunxi/common/spl/spl_mm
  
  	spl_parse_image_header(header);
  
-diff -ruN u-boot-2014.01-rc1/drivers/gpio/Makefile u-boot-sunxi/drivers/gpio/Makefile
---- u-boot-2014.01-rc1/drivers/gpio/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/gpio/Makefile	2014-03-05 23:14:47.996088920 +0100
-@@ -31,3 +31,4 @@
+diff -ruN u-boot-2014.04/drivers/gpio/Makefile u-boot-sunxi/drivers/gpio/Makefile
+--- u-boot-2014.04/drivers/gpio/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/gpio/Makefile	2014-09-06 16:58:36.253953113 +0200
+@@ -34,3 +34,4 @@
  obj-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
  obj-$(CONFIG_TCA642X)		+= tca642x.o
  oby-$(CONFIG_SX151X)		+= sx151x.o
 +obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
-diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio/sunxi_gpio.c
---- u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/gpio/sunxi_gpio.c	2014-03-05 23:14:47.996088920 +0100
-@@ -0,0 +1,120 @@
+diff -ruN u-boot-2014.04/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio/sunxi_gpio.c
+--- u-boot-2014.04/drivers/gpio/sunxi_gpio.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/gpio/sunxi_gpio.c	2014-09-06 16:58:36.253953113 +0200
+@@ -0,0 +1,102 @@
 +/*
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
@@ -6524,23 +6294,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + * Tom Cubie <tangliang@allwinnertech.com>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -6552,8 +6306,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio
 +	u32 dat;
 +	u32 bank = GPIO_BANK(pin);
 +	u32 num = GPIO_NUM(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
 +	dat = readl(&pio->dat);
 +	if (val)
@@ -6571,8 +6324,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio
 +	u32 dat;
 +	u32 bank = GPIO_BANK(pin);
 +	u32 num = GPIO_NUM(pin);
-+	struct sunxi_gpio *pio =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
++	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 +
 +	dat = readl(&pio->dat);
 +	dat >>= num;
@@ -6614,7 +6366,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio
 +	return sunxi_gpio_output(gpio, value);
 +}
 +
-+int name_to_gpio(const char *name)
++int sunxi_name_to_gpio(const char *name)
 +{
 +	int group = 0;
 +	int groupsize = 9 * 32;
@@ -6635,312 +6387,131 @@ diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio
 +		return -1;
 +	return group * 32 + pin;
 +}
-diff -ruN u-boot-2014.01-rc1/drivers/i2c/Makefile u-boot-sunxi/drivers/i2c/Makefile
---- u-boot-2014.01-rc1/drivers/i2c/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/i2c/Makefile	2014-03-05 23:14:48.000088867 +0100
-@@ -16,6 +16,7 @@
- obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
- obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
- obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
-+obj-$(CONFIG_SUNXI_I2C) += sunxi_i2c.o
- obj-$(CONFIG_SYS_I2C) += i2c_core.o
- obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
- obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
-diff -ruN u-boot-2014.01-rc1/drivers/i2c/sunxi_i2c.c u-boot-sunxi/drivers/i2c/sunxi_i2c.c
---- u-boot-2014.01-rc1/drivers/i2c/sunxi_i2c.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/i2c/sunxi_i2c.c	2014-03-05 23:14:48.000088867 +0100
-@@ -0,0 +1,276 @@
-+/*
-+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#include <i2c.h>
-+#include <asm/io.h>
-+#include <asm/arch/clock.h>
-+#include <asm/arch/cpu.h>
-+#include <asm/arch/gpio.h>
+diff -ruN u-boot-2014.04/drivers/i2c/Makefile u-boot-sunxi/drivers/i2c/Makefile
+--- u-boot-2014.04/drivers/i2c/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/i2c/Makefile	2014-09-06 16:58:36.265953112 +0200
+@@ -27,5 +27,6 @@
+ obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
+ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
+ obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
++obj-$(CONFIG_SYS_I2C_SUNXI) += mvtwsi.o
+ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
+ obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
+diff -ruN u-boot-2014.04/drivers/i2c/mvtwsi.c u-boot-sunxi/drivers/i2c/mvtwsi.c
+--- u-boot-2014.04/drivers/i2c/mvtwsi.c	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/i2c/mvtwsi.c	2014-09-06 16:58:36.265953112 +0200
+@@ -22,6 +22,8 @@
+ #include <asm/arch/orion5x.h>
+ #elif defined(CONFIG_KIRKWOOD)
+ #include <asm/arch/kirkwood.h>
++#elif defined(CONFIG_SUNXI)
 +#include <asm/arch/i2c.h>
+ #else
+ #error Driver mvtwsi not supported by SoC or board
+ #endif
+@@ -30,6 +32,20 @@
+  * TWSI register structure
+  */
+ 
++#ifdef CONFIG_SUNXI
 +
-+static struct i2c __attribute__ ((section(".data"))) *i2c_base =
-+	(struct i2c *)0x1c2ac00;
-+
-+void i2c_init(int speed, int slaveaddr)
-+{
-+	int timeout = 0x2ff;
-+
-+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2);
-+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2);
-+	clock_twi_onoff(0, 1);
-+
-+	/* Enable the i2c bus */
-+	writel(TWI_CTL_BUSEN, &i2c_base->ctl);
-+
-+	/* 400KHz operation M=2, N=1, 24MHz APB clock */
-+	writel(TWI_CLK_DIV(2, 1), &i2c_base->clkr);
-+	writel(TWI_SRST_SRST, &i2c_base->reset);
-+
-+	while ((readl(&i2c_base->reset) & TWI_SRST_SRST) && timeout--);
-+}
-+
-+int i2c_probe(uchar chip)
-+{
-+	return -1;
-+}
-+
-+static int i2c_wait_ctl(int mask, int state)
-+{
-+	int timeout = 0x2ff;
-+	int value = state ? mask : 0;
-+
-+	debug("i2c_wait_ctl(%x == %x), ctl=%x, status=%x\n", mask, value,
-+	      i2c_base->ctl, i2c_base->status);
-+
-+	while (((readl(&i2c_base->ctl) & mask) != value) && timeout-- > 0);
-+
-+	debug("i2c_wait_ctl(), timeout=%d, ctl=%x, status=%x\n", timeout,
-+	      i2c_base->ctl, i2c_base->status);
-+
-+	if (timeout != 0)
-+		return 0;
-+	else
-+		return -1;
-+}
-+
-+static void i2c_clear_irq(void)
-+{
-+	writel(readl(&i2c_base->ctl) & ~TWI_CTL_INTFLG, &i2c_base->ctl);
-+}
-+
-+static int i2c_wait_irq(void)
-+{
-+	return i2c_wait_ctl(TWI_CTL_INTFLG, 1);
-+}
-+
-+static int i2c_wait_status(int status)
-+{
-+	int timeout = 0x2ff;
-+
-+	while (readl(&i2c_base->status) != status && timeout-- > 0);
-+
-+	if (timeout != 0)
-+		return 0;
-+	else
-+		return -1;
-+}
-+
-+static int i2c_wait_irq_status(int status)
-+{
-+	if (i2c_wait_irq() != 0)
-+		return -1;
-+
-+	if (readl(&i2c_base->status) != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static int i2c_wait_bus_idle(void)
-+{
-+	int timeout = 0x2ff;
-+
-+	while (readl(&i2c_base->lctl) != 0x3a && timeout-- > 0);
-+
-+	if (timeout != 0)
-+		return 0;
-+	else
-+		return -1;
-+}
-+
-+static int i2c_stop(void)
-+{
-+	u32 ctl;
-+
-+	ctl = readl(&i2c_base->ctl) & 0xc0;
-+	ctl |= TWI_CTL_STP;
-+
-+	writel(ctl, &i2c_base->ctl);
-+
-+	/* dummy to delay one I/O operation to make sure it's started */
-+	(void)readl(&i2c_base->ctl);
-+
-+	if (i2c_wait_ctl(TWI_CTL_STP, 0) != 0)
-+		return -1;
-+	if (i2c_wait_status(TWI_STAT_IDLE))
-+		return -1;
-+	if (i2c_wait_bus_idle() != 0)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static int i2c_send_data(u8 data, u8 status)
-+{
-+	debug("i2c_write(%02x, %x), ctl=%x, status=%x\n", data, status,
-+	      i2c_base->ctl, i2c_base->status);
-+
-+	writel(data, &i2c_base->data);
-+	i2c_clear_irq();
-+
-+	if (i2c_wait_irq_status(status) != 0)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static int i2c_start(int status)
-+{
-+	u32 ctl;
-+
-+	debug("i2c_start(%x), ctl=%x, status=%x\n", status, i2c_base->ctl,
-+	      i2c_base->status);
-+	/* Check that the controller is idle */
-+	if (status == TWI_STAT_TX_STA &&
-+	    readl(&i2c_base->status) != TWI_STAT_IDLE) {
-+		return -1;
-+	}
-+
-+	writel(0, &i2c_base->efr);
-+
-+	/* Send start */
-+	ctl = readl(&i2c_base->ctl);
-+	ctl |= TWI_CTL_STA;	/* Set start bit */
-+	ctl &= ~TWI_CTL_INTFLG;	/* Clear int flag */
-+	writel(ctl, &i2c_base->ctl);
-+
-+	if (i2c_wait_ctl(TWI_CTL_STA, 0) != 0)
-+		return -1;
-+	if (i2c_wait_irq_status(status) != 0)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int i2c_do_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-+{
++struct  mvtwsi_registers {
++	u32 slave_address;
++	u32 xtnd_slave_addr;
++	u32 data;
++	u32 control;
 +	u32 status;
-+	u32 ctl;
-+
-+	if (i2c_start(TWI_STAT_TX_STA) != 0)
-+		return -1;
-+
-+	/* Send chip address */
-+	if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0)
-+		return -1;
-+
-+	/* Send data address */
-+	if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0)
-+		return -1;
-+
-+	/* Send restart for read */
-+	if (i2c_start(TWI_STAT_TX_RESTA) != 0)
-+		return -1;
-+
-+	/* Send chip address */
-+	if (i2c_send_data(chip << 1 | 1, TWI_STAT_TX_AR_ACK) != 0)
-+		return -1;
-+
-+	/* Set ACK mode */
-+	ctl = readl(&i2c_base->ctl);
-+	ctl |= TWI_CTL_ACK;
-+	writel(ctl, &i2c_base->ctl);
-+	status = TWI_STAT_RXD_ACK;
-+
-+	/* Read data */
-+	while (len > 0) {
-+		if (len == 1) {
-+			/* Set NACK mode (last byte) */
-+			ctl = readl(&i2c_base->ctl);
-+			ctl &= ~TWI_CTL_ACK;
-+			writel(ctl, &i2c_base->ctl);
-+			status = TWI_STAT_RXD_NAK;
-+		}
-+
-+		i2c_clear_irq();
-+		if (i2c_wait_irq_status(status) != 0)
-+			return -1;
-+
-+		*buffer++ = readl(&i2c_base->data);
-+		len--;
-+	}
-+
-+	return 0;
-+}
-+
-+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-+{
-+	int rc = i2c_do_read(chip, addr, alen, buffer, len);
-+
-+	i2c_stop();
-+
-+	return rc;
-+}
-+
-+static int i2c_do_write(uchar chip, uint addr, int alen, uchar *buffer,
-+			int len)
-+{
-+	if (i2c_start(TWI_STAT_TX_STA) != 0)
-+		return -1;
-+
-+	/* Send chip address */
-+	if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0)
-+		return -1;
-+
-+	/* Send data address */
-+	if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0)
-+		return -1;
-+
-+	/* Send data */
-+	while (len > 0) {
-+		if (i2c_send_data(*buffer++, TWI_STAT_TXD_ACK) != 0)
-+			return -1;
-+		len--;
-+	}
-+
-+	return 0;
-+}
++	u32 baudrate;
++	u32 soft_reset;
++};
 +
-+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-+{
-+	int rc = i2c_do_write(chip, addr, alen, buffer, len);
++#else
 +
-+	i2c_stop();
+ struct  mvtwsi_registers {
+ 	u32 slave_address;
+ 	u32 data;
+@@ -43,6 +59,8 @@
+ 	u32 soft_reset;
+ };
+ 
++#endif
 +
-+	return rc;
-+}
-diff -ruN u-boot-2014.01-rc1/drivers/mmc/Makefile u-boot-sunxi/drivers/mmc/Makefile
---- u-boot-2014.01-rc1/drivers/mmc/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/mmc/Makefile	2014-03-05 23:14:48.004088813 +0100
-@@ -26,6 +26,7 @@
+ /*
+  * Control register fields
+  */
+@@ -216,21 +234,7 @@
+  */
+ 
+ #define TWSI_FREQUENCY(m, n) \
+-	((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
+-
+-/*
+- * These are required to be reprogrammed before enabling the controller
+- * because a reset loses them.
+- * Default values come from the spec, but a twsi_reset will change them.
+- * twsi_slave_address left uninitialized lest checkpatch.pl complains.
+- */
+-
+-/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
+-static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
+-/* Default frequency corresponding to default m=4, n=4 */
+-static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
+-/* Default slave address is 0 (so is an uninitialized static) */
+-static u8 twsi_slave_address;
++	(CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
+ 
+ /*
+  * Reset controller.
+@@ -238,7 +242,7 @@
+  * Controller reset also resets the baud rate and slave address, so
+  * re-establish them.
+  */
+-static void twsi_reset(void)
++static void twsi_reset(u8 baud_rate, u8 slave_address)
+ {
+ 	/* ensure controller will be enabled by any twsi*() function */
+ 	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
+@@ -247,9 +251,9 @@
+ 	/* wait 2 ms -- this is what the Marvell LSP does */
+ 	udelay(20000);
+ 	/* set baud rate */
+-	writel(twsi_baud_rate, &twsi->baudrate);
++	writel(baud_rate, &twsi->baudrate);
+ 	/* set slave address even though we don't use it */
+-	writel(twsi_slave_address, &twsi->slave_address);
++	writel(slave_address, &twsi->slave_address);
+ 	writel(0, &twsi->xtnd_slave_addr);
+ 	/* assert STOP but don't care for the result */
+ 	(void) twsi_stop(0);
+@@ -277,12 +281,8 @@
+ 			}
+ 		}
+ 	}
+-	/* save baud rate and slave for later calls to twsi_reset */
+-	twsi_baud_rate = baud;
+-	twsi_actual_speed = highest_speed;
+-	twsi_slave_address = slaveadd;
+ 	/* reset controller */
+-	twsi_reset();
++	twsi_reset(baud, slaveadd);
+ }
+ 
+ /*
+diff -ruN u-boot-2014.04/drivers/mmc/Makefile u-boot-sunxi/drivers/mmc/Makefile
+--- u-boot-2014.04/drivers/mmc/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/mmc/Makefile	2014-09-06 16:58:36.281953112 +0200
+@@ -28,6 +28,7 @@
  obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
  obj-$(CONFIG_DWMMC) += dw_mmc.o
  obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
 +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
  obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+ obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
  ifdef CONFIG_SPL_BUILD
- obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
-diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/sunxi_mmc.c
---- u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/mmc/sunxi_mmc.c	2014-03-05 23:14:48.008088759 +0100
-@@ -0,0 +1,660 @@
+diff -ruN u-boot-2014.04/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/sunxi_mmc.c
+--- u-boot-2014.04/drivers/mmc/sunxi_mmc.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/mmc/sunxi_mmc.c	2014-09-06 16:58:36.281953112 +0200
+@@ -0,0 +1,385 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -6948,23 +6519,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 + *
 + * MMC driver for allwinner sunxi platform.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -6973,81 +6528,8 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +#include <asm/io.h>
 +#include <asm/arch/clock.h>
 +#include <asm/arch/cpu.h>
-+#include <asm/arch/gpio.h>
 +#include <asm/arch/mmc.h>
 +
-+static void dumphex32(char *name, char *base, int len)
-+{
-+	__u32 i;
-+
-+	debug("dump %s registers:", name);
-+	for (i = 0; i < len; i += 4) {
-+		if (!(i & 0xf))
-+			debug("\n0x%p : ", base + i);
-+		debug("0x%08x ", readl(base + i));
-+	}
-+	debug("\n");
-+}
-+
-+static void dumpmmcreg(struct sunxi_mmc *reg)
-+{
-+	debug("dump mmc registers:\n");
-+	debug("gctrl     0x%08x\n", reg->gctrl);
-+	debug("clkcr     0x%08x\n", reg->clkcr);
-+	debug("timeout   0x%08x\n", reg->timeout);
-+	debug("width     0x%08x\n", reg->width);
-+	debug("blksz     0x%08x\n", reg->blksz);
-+	debug("bytecnt   0x%08x\n", reg->bytecnt);
-+	debug("cmd       0x%08x\n", reg->cmd);
-+	debug("arg       0x%08x\n", reg->arg);
-+	debug("resp0     0x%08x\n", reg->resp0);
-+	debug("resp1     0x%08x\n", reg->resp1);
-+	debug("resp2     0x%08x\n", reg->resp2);
-+	debug("resp3     0x%08x\n", reg->resp3);
-+	debug("imask     0x%08x\n", reg->imask);
-+	debug("mint      0x%08x\n", reg->mint);
-+	debug("rint      0x%08x\n", reg->rint);
-+	debug("status    0x%08x\n", reg->status);
-+	debug("ftrglevel 0x%08x\n", reg->ftrglevel);
-+	debug("funcsel   0x%08x\n", reg->funcsel);
-+	debug("dmac      0x%08x\n", reg->dmac);
-+	debug("dlba      0x%08x\n", reg->dlba);
-+	debug("idst      0x%08x\n", reg->idst);
-+	debug("idie      0x%08x\n", reg->idie);
-+}
-+
-+struct sunxi_mmc_des {
-+	u32 reserved1_1:1;
-+	u32 dic:1;		/* disable interrupt on completion */
-+	u32 last_des:1;		/* 1-this data buffer is the last buffer */
-+	u32 first_des:1;		/* 1-data buffer is the first buffer,
-+				   0-data buffer contained in the next
-+				   descriptor is 1st buffer */
-+	u32 des_chain:1;	/* 1-the 2nd address in the descriptor is the
-+				   next descriptor address */
-+	u32 end_of_ring:1;	/* 1-last descriptor flag when using dual
-+				   data buffer in descriptor */
-+	u32 reserved1_2:24;
-+	u32 card_err_sum:1;	/* transfer error flag */
-+	u32 own:1;		/* des owner:1-idma owns it, 0-host owns it */
-+#ifdef CONFIG_SUN4I
-+#define SDXC_DES_NUM_SHIFT 13
-+#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
-+	u32 data_buf1_sz:13;
-+	u32 data_buf2_sz:13;
-+	u32 reserverd2_1:6;
-+#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
-+#define SDXC_DES_NUM_SHIFT 16
-+#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
-+	u32 data_buf1_sz:16;
-+	u32 data_buf2_sz:16;
-+#else
-+#error ">>>> Wrong Platform for MMC <<<<"
-+#endif
-+	u32 buf_addr_ptr1;
-+	u32 buf_addr_ptr2;
-+};
-+
 +struct sunxi_mmc_host {
 +	unsigned mmc_no;
 +	uint32_t *mclkreg;
@@ -7055,10 +6537,10 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +	unsigned fatal_err;
 +	unsigned mod_clk;
 +	struct sunxi_mmc *reg;
++	struct mmc_config cfg;
 +};
 +
 +/* support 4 mmc hosts */
-+struct mmc mmc_dev[4];
 +struct sunxi_mmc_host mmc_host[4];
 +
 +static int mmc_resource_init(int sdc_no)
@@ -7089,7 +6571,11 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +		printf("Wrong mmc number %d\n", sdc_no);
 +		return -1;
 +	}
++#ifdef CONFIG_SUN6I
++	mmchost->database = (unsigned int)mmchost->reg + 0x200;
++#else
 +	mmchost->database = (unsigned int)mmchost->reg + 0x100;
++#endif
 +	mmchost->mmc_no = sdc_no;
 +
 +	return 0;
@@ -7097,104 +6583,49 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +static int mmc_clk_io_on(int sdc_no)
 +{
-+	unsigned int rval;
-+	unsigned int pll5_clk;
++	unsigned int pll_clk;
 +	unsigned int divider;
 +	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
-+	static struct sunxi_gpio *gpio_c =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
-+	static struct sunxi_gpio *gpio_f =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
-+#if CONFIG_MMC1_PG
-+	static struct sunxi_gpio *gpio_g =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
-+#endif
-+	static struct sunxi_gpio *gpio_h =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
-+	static struct sunxi_gpio *gpio_i =
-+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
 +	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 +
 +	debug("init mmc %d clock and io\n", sdc_no);
 +
-+	/* config gpio */
-+	switch (sdc_no) {
-+	case 0:
-+		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
-+		writel(0x222222, &gpio_f->cfg[0]);
-+		writel(0x555, &gpio_f->pull[0]);
-+		writel(0xaaa, &gpio_f->drv[0]);
-+		break;
++	/* config ahb clock */
++	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 +
-+	case 1:
-+#if CONFIG_MMC1_PG
-+		/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
-+		writel(0x444444, &gpio_g->cfg[0]);
-+		writel(0x555, &gpio_g->pull[0]);
-+		writel(0xaaa, &gpio_g->drv[0]);
-+#else
-+		/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
-+		writel(0x55 << 24, &gpio_h->cfg[2]);
-+		writel(0x5555, &gpio_h->cfg[3]);
-+		writel(0x555 << 12, &gpio_h->pull[1]);
-+		writel(0xaaa << 12, &gpio_h->drv[1]);
++#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
++	/* unassert reset */
++	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 +#endif
-+		break;
-+
-+	case 2:
-+		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
-+		writel(0x33 << 24, &gpio_c->cfg[0]);
-+		writel(0x3333, &gpio_c->cfg[1]);
-+		writel(0x555 << 12, &gpio_c->pull[0]);
-+		writel(0xaaa << 12, &gpio_c->drv[0]);
-+		break;
-+
-+	case 3:
-+		/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
-+		writel(0x2222 << 16, &gpio_i->cfg[0]);
-+		writel(0x22, &gpio_i->cfg[1]);
-+		writel(0x555 << 8, &gpio_i->pull[0]);
-+		writel(0x555 << 8, &gpio_i->drv[0]);
-+		break;
-+
-+	default:
-+		return -1;
-+	}
-+
-+	/* config ahb clock */
-+	rval = readl(&ccm->ahb_gate0);
-+	rval |= (1 << (8 + sdc_no));
-+	writel(rval, &ccm->ahb_gate0);
 +
 +	/* config mod clock */
-+	pll5_clk = clock_get_pll5();
-+	if (pll5_clk > 400000000)
-+		divider = 4;
-+	else
-+		divider = 3;
-+	writel((0x1 << 31) | (0x2 << 24) | divider, mmchost->mclkreg);
-+	mmchost->mod_clk = pll5_clk / (divider + 1);
-+
-+	dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
-+	dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
-+	dumphex32("mmc", (char *)mmchost->reg, 0x100);
-+	dumpmmcreg(mmchost->reg);
++	pll_clk = clock_get_pll6();
++	/* should be close to 100 MHz but no more, so round up */
++	divider = ((pll_clk + 99999999) / 100000000) - 1;
++	writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
++	       mmchost->mclkreg);
++	mmchost->mod_clk = pll_clk / (divider + 1);
 +
 +	return 0;
 +}
 +
 +static int mmc_update_clk(struct mmc *mmc)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
 +	unsigned int cmd;
-+	unsigned timeout = 0xfffff;
++	unsigned timeout_msecs = 2000;
 +
-+	cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
++	cmd = SUNXI_MMC_CMD_START |
++	      SUNXI_MMC_CMD_UPCLK_ONLY |
++	      SUNXI_MMC_CMD_WAIT_PRE_OVER;
 +	writel(cmd, &mmchost->reg->cmd);
-+	while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
-+	if (!timeout)
-+		return -1;
++	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
++		if (!timeout_msecs--)
++			return -1;
++		udelay(1000);
++	}
 +
++	/* clock update sets various irq status bits, clear these */
 +	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
 +
 +	return 0;
@@ -7202,28 +6633,23 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +static int mmc_config_clock(struct mmc *mmc, unsigned div)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
 +	unsigned rval = readl(&mmchost->reg->clkcr);
 +
-+	/*
-+	 * CLKCREG[7:0]: divider
-+	 * CLKCREG[16]:  on/off
-+	 * CLKCREG[17]:  power save
-+	 */
 +	/* Disable Clock */
-+	rval &= ~(0x1 << 16);
++	rval &= ~SUNXI_MMC_CLK_ENABLE;
 +	writel(rval, &mmchost->reg->clkcr);
 +	if (mmc_update_clk(mmc))
 +		return -1;
 +
 +	/* Change Divider Factor */
-+	rval &= ~(0xff);
++	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 +	rval |= div;
 +	writel(rval, &mmchost->reg->clkcr);
 +	if (mmc_update_clk(mmc))
 +		return -1;
 +	/* Re-enable Clock */
-+	rval |= (0x1 << 16);
++	rval |= SUNXI_MMC_CLK_ENABLE;
 +	writel(rval, &mmchost->reg->clkcr);
 +
 +	if (mmc_update_clk(mmc))
@@ -7234,7 +6660,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +static void mmc_set_ios(struct mmc *mmc)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
 +	unsigned int clkdiv = 0;
 +
 +	debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
@@ -7242,11 +6668,12 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +	/* Change clock first */
 +	clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
-+	if (mmc->clock)
++	if (mmc->clock) {
 +		if (mmc_config_clock(mmc, clkdiv)) {
 +			mmchost->fatal_err = 1;
 +			return;
 +		}
++	}
 +
 +	/* Change bus width */
 +	if (mmc->bus_width == 8)
@@ -7259,136 +6686,61 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +static int mmc_core_init(struct mmc *mmc)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
 +
 +	/* Reset controller */
-+	writel(0x7, &mmchost->reg->gctrl);
++	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
++	udelay(1000);
 +
 +	return 0;
 +}
 +
 +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
++	const int reading = !!(data->flags & MMC_DATA_READ);
++	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
++					      SUNXI_MMC_STATUS_FIFO_FULL;
 +	unsigned i;
 +	unsigned byte_cnt = data->blocksize * data->blocks;
-+	unsigned *buff;
-+	unsigned timeout = 0xfffff;
-+
-+	if (data->flags & MMC_DATA_READ) {
-+		buff = (unsigned int *)data->dest;
-+		for (i = 0; i < (byte_cnt >> 2); i++) {
-+			while (--timeout &&
-+				 (readl(&mmchost->reg->status) & (0x1 << 2)));
-+			if (timeout <= 0)
-+				goto out;
-+			buff[i] = readl(mmchost->database);
-+			timeout = 0xfffff;
++	unsigned timeout_msecs = 2000;
++	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
++
++	/* Always read / write data through the CPU */
++	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
++
++	for (i = 0; i < (byte_cnt >> 2); i++) {
++		while (readl(&mmchost->reg->status) & status_bit) {
++			if (!timeout_msecs--)
++				return -1;
++			udelay(1000);
 +		}
-+	} else {
-+		buff = (unsigned int *)data->src;
-+		for (i = 0; i < (byte_cnt >> 2); i++) {
-+			while (--timeout &&
-+				 (readl(&mmchost->reg->status) & (0x1 << 3)));
-+			if (timeout <= 0)
-+				goto out;
++
++		if (reading)
++			buff[i] = readl(mmchost->database);
++		else
 +			writel(buff[i], mmchost->database);
-+			timeout = 0xfffff;
-+		}
 +	}
 +
-+out:
-+	if (timeout <= 0)
-+		return -1;
-+
 +	return 0;
 +}
 +
-+static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
++static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
++			 unsigned int done_bit, const char *what)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
-+	unsigned byte_cnt = data->blocksize * data->blocks;
-+	unsigned char *buff;
-+	unsigned des_idx = 0;
-+	unsigned buff_frag_num =
-+		(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
-+	unsigned remain;
-+	unsigned i, rval;
-+	ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
-+
-+	buff = data->flags & MMC_DATA_READ ?
-+	    (unsigned char *)data->dest : (unsigned char *)data->src;
-+	remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-+	if (!remain)
-+		remain = SDXC_DES_BUFFER_MAX_LEN;
-+
-+	flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
-+	for (i = 0; i < buff_frag_num; i++, des_idx++) {
-+		memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
-+		pdes[des_idx].des_chain = 1;
-+		pdes[des_idx].own = 1;
-+		pdes[des_idx].dic = 1;
-+		if (buff_frag_num > 1 && i != buff_frag_num - 1)
-+			pdes[des_idx].data_buf1_sz =
-+			    (SDXC_DES_BUFFER_MAX_LEN -
-+			     1) & SDXC_DES_BUFFER_MAX_LEN;
-+		else
-+			pdes[des_idx].data_buf1_sz = remain;
-+
-+		pdes[des_idx].buf_addr_ptr1 =
-+		    (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
-+		if (i == 0)
-+			pdes[des_idx].first_des = 1;
-+
-+		if (i == buff_frag_num - 1) {
-+			pdes[des_idx].dic = 0;
-+			pdes[des_idx].last_des = 1;
-+			pdes[des_idx].end_of_ring = 1;
-+			pdes[des_idx].buf_addr_ptr2 = 0;
-+		} else {
-+			pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
-+		}
-+		debug("frag %d, remain %d, des[%d](%08x): ",
-+		      i, remain, des_idx, (u32)&pdes[des_idx]);
-+		debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
-+		      (u32)((u32 *)&pdes[des_idx])[0],
-+		      (u32)((u32 *)&pdes[des_idx])[1],
-+		      (u32)((u32 *)&pdes[des_idx])[2],
-+		      (u32)((u32 *)&pdes[des_idx])[3]);
-+	}
-+	flush_cache((unsigned long)pdes,
-+		    sizeof(struct sunxi_mmc_des) * (des_idx + 1));
++	struct sunxi_mmc_host *mmchost = mmc->priv;
++	unsigned int status;
 +
-+	/*
-+	 * GCTRLREG
-+	 * GCTRL[2]     : DMA reset
-+	 * GCTRL[5]     : DMA enable
-+	 *
-+	 * IDMACREG
-+	 * IDMAC[0]     : IDMA soft reset
-+	 * IDMAC[1]     : IDMA fix burst flag
-+	 * IDMAC[7]     : IDMA on
-+	 *
-+	 * IDIECREG
-+	 * IDIE[0]      : IDMA transmit interrupt flag
-+	 * IDIE[1]      : IDMA receive interrupt flag
-+	 */
-+	rval = readl(&mmchost->reg->gctrl);
-+	/* Enable DMA */
-+	writel(rval | (0x1 << 5) | (0x1 << 2), &mmchost->reg->gctrl);
-+	/* Reset iDMA */
-+	writel((0x1 << 0), &mmchost->reg->dmac);
-+	/* Enable iDMA */
-+	writel((0x1 << 1) | (1 << 7), &mmchost->reg->dmac);
-+	rval = readl(&mmchost->reg->idie) & (~3);
-+	if (data->flags & MMC_DATA_WRITE)
-+		rval |= (0x1 << 0);
-+	else
-+		rval |= (0x1 << 1);
-+	writel(rval, &mmchost->reg->idie);
-+	writel((u32) pdes, &mmchost->reg->dlba);
-+	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
-+	       &mmchost->reg->ftrglevel);
++	do {
++		status = readl(&mmchost->reg->rint);
++		if (!timeout_msecs-- ||
++		    (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
++			debug("%s timeout %x\n", what,
++			      status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
++			return TIMEOUT;
++		}
++		udelay(1000);
++	} while (!(status & done_bit));
 +
 +	return 0;
 +}
@@ -7396,12 +6748,11 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 +			struct mmc_data *data)
 +{
-+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
-+	unsigned int cmdval = 0x80000000;
-+	signed int timeout = 0;
++	struct sunxi_mmc_host *mmchost = mmc->priv;
++	unsigned int cmdval = SUNXI_MMC_CMD_START;
++	unsigned int timeout_msecs;
 +	int error = 0;
 +	unsigned int status = 0;
-+	unsigned int usedma = 0;
 +	unsigned int bytecnt = 0;
 +
 +	if (mmchost->fatal_err)
@@ -7411,30 +6762,14 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +	if (cmd->cmdidx == 12)
 +		return 0;
 +
-+	/*
-+	 * CMDREG
-+	 * CMD[5:0]     : Command index
-+	 * CMD[6]       : Has response
-+	 * CMD[7]       : Long response
-+	 * CMD[8]       : Check response CRC
-+	 * CMD[9]       : Has data
-+	 * CMD[10]      : Write
-+	 * CMD[11]      : Steam mode
-+	 * CMD[12]      : Auto stop
-+	 * CMD[13]      : Wait previous over
-+	 * CMD[14]      : About cmd
-+	 * CMD[15]      : Send initialization
-+	 * CMD[21]      : Update clock
-+	 * CMD[31]      : Load cmd
-+	 */
 +	if (!cmd->cmdidx)
-+		cmdval |= (0x1 << 15);
++		cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 +	if (cmd->resp_type & MMC_RSP_PRESENT)
-+		cmdval |= (0x1 << 6);
++		cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 +	if (cmd->resp_type & MMC_RSP_136)
-+		cmdval |= (0x1 << 7);
++		cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 +	if (cmd->resp_type & MMC_RSP_CRC)
-+		cmdval |= (0x1 << 8);
++		cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 +
 +	if (data) {
 +		if ((u32) data->dest & 0x3) {
@@ -7442,11 +6777,11 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +			goto out;
 +		}
 +
-+		cmdval |= (0x1 << 9) | (0x1 << 13);
++		cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 +		if (data->flags & MMC_DATA_WRITE)
-+			cmdval |= (0x1 << 10);
++			cmdval |= SUNXI_MMC_CMD_WRITE;
 +		if (data->blocks > 1)
-+			cmdval |= (0x1 << 12);
++			cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 +		writel(data->blocksize, &mmchost->reg->blksz);
 +		writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
 +	}
@@ -7468,69 +6803,43 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +
 +		bytecnt = data->blocksize * data->blocks;
 +		debug("trans data %d bytes\n", bytecnt);
-+#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
-+		if (bytecnt > 64) {
-+#else
-+		if (0) {
-+#endif
-+			usedma = 1;
-+			writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 31),
-+			       &mmchost->reg->gctrl);
-+			ret = mmc_trans_data_by_dma(mmc, data);
-+			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-+		} else {
-+			writel(readl(&mmchost->reg->gctrl) | 0x1 << 31,
-+			       &mmchost->reg->gctrl);
-+			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-+			ret = mmc_trans_data_by_cpu(mmc, data);
-+		}
++		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
++		ret = mmc_trans_data_by_cpu(mmc, data);
 +		if (ret) {
-+			error = readl(&mmchost->reg->rint) & 0xbfc2;
++			error = readl(&mmchost->reg->rint) & \
++				SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 +			error = TIMEOUT;
 +			goto out;
 +		}
 +	}
 +
-+	timeout = 0xfffff;
-+	do {
-+		status = readl(&mmchost->reg->rint);
-+		if (!timeout-- || (status & 0xbfc2)) {
-+			error = status & 0xbfc2;
-+			debug("cmd timeout %x\n", error);
-+			error = TIMEOUT;
-+			goto out;
-+		}
-+	} while (!(status & 0x4));
++	error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
++	if (error)
++		goto out;
 +
 +	if (data) {
-+		unsigned done = 0;
-+		timeout = usedma ? 0xffff * bytecnt : 0xffff;
-+		debug("cacl timeout %x\n", timeout);
-+		do {
-+			status = readl(&mmchost->reg->rint);
-+			if (!timeout-- || (status & 0xbfc2)) {
-+				error = status & 0xbfc2;
-+				debug("data timeout %x\n", error);
-+				error = TIMEOUT;
-+				goto out;
-+			}
-+			if (data->blocks > 1)
-+				done = status & (0x1 << 14);
-+			else
-+				done = status & (0x1 << 3);
-+		} while (!done);
++		timeout_msecs = 120;
++		debug("cacl timeout %x msec\n", timeout_msecs);
++		error = mmc_rint_wait(mmc, timeout_msecs,
++				      data->blocks > 1 ?
++				      SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
++				      SUNXI_MMC_RINT_DATA_OVER,
++				      "data");
++		if (error)
++			goto out;
 +	}
 +
 +	if (cmd->resp_type & MMC_RSP_BUSY) {
-+		timeout = 0xfffff;
++		timeout_msecs = 2000;
 +		do {
 +			status = readl(&mmchost->reg->status);
-+			if (!timeout--) {
++			if (!timeout_msecs--) {
 +				debug("busy timeout\n");
 +				error = TIMEOUT;
 +				goto out;
 +			}
-+		} while (status & (1 << 9));
++			udelay(1000);
++		} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 +	}
 +
 +	if (cmd->resp_type & MMC_RSP_136) {
@@ -7546,89 +6855,175 @@ diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/su
 +		debug("mmc resp 0x%08x\n", cmd->response[0]);
 +	}
 +out:
-+	if (data && usedma) {
-+		/* IDMASTAREG
-+		 * IDST[0] : idma tx int
-+		 * IDST[1] : idma rx int
-+		 * IDST[2] : idma fatal bus error
-+		 * IDST[4] : idma descriptor invalid
-+		 * IDST[5] : idma error summary
-+		 * IDST[8] : idma normal interrupt sumary
-+		 * IDST[9] : idma abnormal interrupt sumary
-+		 */
-+		status = readl(&mmchost->reg->idst);
-+		writel(status, &mmchost->reg->idst);
-+		writel(0, &mmchost->reg->idie);
-+		writel(0, &mmchost->reg->dmac);
-+		writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 5),
-+		       &mmchost->reg->gctrl);
-+	}
 +	if (error < 0) {
-+		writel(0x7, &mmchost->reg->gctrl);
++		writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 +		mmc_update_clk(mmc);
 +	}
 +	writel(0xffffffff, &mmchost->reg->rint);
-+	writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl);
++	writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
++	       &mmchost->reg->gctrl);
 +
 +	return error;
 +}
 +
++static const struct mmc_ops sunxi_mmc_ops = {
++	.send_cmd	= mmc_send_cmd,
++	.set_ios	= mmc_set_ios,
++	.init		= mmc_core_init,
++};
++
 +int sunxi_mmc_init(int sdc_no)
 +{
-+	struct mmc *mmc;
++	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
 +
-+	memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
 +	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
-+	mmc = &mmc_dev[sdc_no];
 +
-+	sprintf(mmc->name, "SUNXI SD/MMC");
-+	mmc->priv = &mmc_host[sdc_no];
-+	mmc->send_cmd = mmc_send_cmd;
-+	mmc->set_ios = mmc_set_ios;
-+	mmc->init = mmc_core_init;
++	cfg->name = "SUNXI SD/MMC";
++	cfg->ops  = &sunxi_mmc_ops;
 +
-+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-+	mmc->host_caps = MMC_MODE_4BIT;
-+	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
++	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
++	cfg->host_caps = MMC_MODE_4BIT;
++	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
++	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 +
-+	mmc->f_min = 400000;
-+	mmc->f_max = 52000000;
++	cfg->f_min = 400000;
++	cfg->f_max = 52000000;
 +
 +	mmc_resource_init(sdc_no);
 +	mmc_clk_io_on(sdc_no);
 +
-+	mmc_register(mmc);
++	if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
++		return -1;
 +
 +	return 0;
 +}
-diff -ruN u-boot-2014.01-rc1/drivers/net/designware.c u-boot-sunxi/drivers/net/designware.c
---- u-boot-2014.01-rc1/drivers/net/designware.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/net/designware.c	2014-03-05 23:14:48.024088546 +0100
-@@ -154,7 +154,7 @@
- 	/* Resore the HW MAC address as it has been lost during MAC reset */
- 	dw_write_hwaddr(dev);
+diff -ruN u-boot-2014.04/drivers/net/designware.c u-boot-sunxi/drivers/net/designware.c
+--- u-boot-2014.04/drivers/net/designware.c	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/net/designware.c	2014-09-06 16:58:36.301953111 +0200
+@@ -249,7 +249,7 @@
+ 	rx_descs_init(dev);
+ 	tx_descs_init(dev);
+ 
+-	writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
++	writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
+ 
+ 	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
+ 	       &dma_p->opmode);
+@@ -280,10 +280,18 @@
+ 	u32 desc_num = priv->tx_currdescnum;
+ 	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
+ 
+-	/* Invalidate only "status" field for the following check */
+-	invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
+-				(unsigned long)&desc_p->txrx_status +
+-				sizeof(desc_p->txrx_status));
++	/*
++	 * Strictly we only need to invalidate the "txrx_status" field
++	 * for the following check, but on some platforms we cannot
++	 * invalidate only 4 bytes, so roundup to
++	 * ARCH_DMA_MINALIGN. This is safe because the individual
++	 * descriptors in the array are each aligned to
++	 * ARCH_DMA_MINALIGN.
++	 */
++	invalidate_dcache_range(
++		(unsigned long)desc_p,
++		(unsigned long)desc_p +
++		roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
+ 
+ 	/* Check if the descriptor is owned by CPU */
+ 	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
+@@ -351,7 +359,7 @@
+ 		/* Invalidate received data */
+ 		invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
+ 					(unsigned long)desc_p->dmamac_addr +
+-					length);
++					roundup(length, ARCH_DMA_MINALIGN));
+ 
+ 		NetReceive(desc_p->dmamac_addr, length);
+ 
+@@ -390,6 +398,8 @@
+ 	if (!phydev)
+ 		return -1;
+ 
++	phy_connect_dev(phydev, dev);
++
+ 	phydev->supported &= PHY_GBIT_FEATURES;
+ 	phydev->advertising = phydev->supported;
+ 
+@@ -412,7 +422,8 @@
+ 	 * Since the priv structure contains the descriptors which need a strict
+ 	 * buswidth alignment, memalign is used to allocate memory
+ 	 */
+-	priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
++	priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
++					      sizeof(struct dw_eth_dev));
+ 	if (!priv) {
+ 		free(dev);
+ 		return -ENOMEM;
+diff -ruN u-boot-2014.04/drivers/net/designware.h u-boot-sunxi/drivers/net/designware.h
+--- u-boot-2014.04/drivers/net/designware.h	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/net/designware.h	2014-09-06 16:58:36.301953111 +0200
+@@ -77,18 +77,18 @@
+ 
+ #define DW_DMA_BASE_OFFSET	(0x1000)
+ 
++/* Default DMA Burst length */
++#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
++#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
++#endif
++
+ /* Bus mode register definitions */
+ #define FIXEDBURST		(1 << 16)
+ #define PRIORXTX_41		(3 << 14)
+ #define PRIORXTX_31		(2 << 14)
+ #define PRIORXTX_21		(1 << 14)
+ #define PRIORXTX_11		(0 << 14)
+-#define BURST_1			(1 << 8)
+-#define BURST_2			(2 << 8)
+-#define BURST_4			(4 << 8)
+-#define BURST_8			(8 << 8)
+-#define BURST_16		(16 << 8)
+-#define BURST_32		(32 << 8)
++#define DMA_PBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
+ #define RXHIGHPRIO		(1 << 1)
+ #define DMAMAC_SRST		(1 << 0)
+ 
+@@ -215,15 +215,14 @@
+ #endif
+ 
+ struct dw_eth_dev {
+-	u32 interface;
+-	u32 tx_currdescnum;
+-	u32 rx_currdescnum;
+-
+ 	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+ 	struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
++	char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
++	char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  
--	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
-+	writel(FIXEDBURST | PRIORXTX_41 | BURST_8,
- 			&dma_p->busmode);
+-	char txbuffs[TX_TOTAL_BUFSIZE];
+-	char rxbuffs[RX_TOTAL_BUFSIZE];
++	u32 interface;
++	u32 tx_currdescnum;
++	u32 rx_currdescnum;
  
- 	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
-diff -ruN u-boot-2014.01-rc1/drivers/net/Makefile u-boot-sunxi/drivers/net/Makefile
---- u-boot-2014.01-rc1/drivers/net/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/net/Makefile	2014-03-05 23:14:48.020088600 +0100
-@@ -50,7 +50,8 @@
+ 	struct eth_mac_regs *mac_regs_p;
+ 	struct eth_dma_regs *dma_regs_p;
+diff -ruN u-boot-2014.04/drivers/net/Makefile u-boot-sunxi/drivers/net/Makefile
+--- u-boot-2014.04/drivers/net/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/net/Makefile	2014-09-06 16:58:36.297953112 +0200
+@@ -50,7 +50,7 @@
  obj-$(CONFIG_SH_ETHER) += sh_eth.o
  obj-$(CONFIG_SMC91111) += smc91111.o
  obj-$(CONFIG_SMC911X) += smc911x.o
 -obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
 +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
-+obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
  obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
  obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
  obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
-diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/sunxi_emac.c
---- u-boot-2014.01-rc1/drivers/net/sunxi_emac.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/net/sunxi_emac.c	2014-03-05 23:14:48.056088119 +0100
+diff -ruN u-boot-2014.04/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/sunxi_emac.c
+--- u-boot-2014.04/drivers/net/sunxi_emac.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/net/sunxi_emac.c	2014-09-06 16:58:36.317953111 +0200
 @@ -0,0 +1,521 @@
 +/*
 + * sunxi_emac.c -- Allwinner A10 ethernet driver
@@ -8129,7 +7524,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/s
 +
 +	/* Configure pin mux settings for MII Ethernet */
 +	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-+		sunxi_gpio_set_cfgpin(pin, 2);
++		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
 +
 +	/* Set up clock gating */
 +	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
@@ -8151,57 +7546,8 @@ diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/s
 +
 +	return 0;
 +}
-diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_gmac.c u-boot-sunxi/drivers/net/sunxi_gmac.c
---- u-boot-2014.01-rc1/drivers/net/sunxi_gmac.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/net/sunxi_gmac.c	2014-03-05 23:14:48.056088119 +0100
-@@ -0,0 +1,45 @@
-+#include <common.h>
-+#include <netdev.h>
-+#include <miiphy.h>
-+#include <asm/gpio.h>
-+#include <asm/io.h>
-+#include <asm/arch/clock.h>
-+#include <asm/arch/gpio.h>
-+
-+int sunxi_gmac_initialize(bd_t *bis)
-+{
-+	int pin;
-+	struct sunxi_ccm_reg *const ccm =
-+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-+
-+	/* Set up clock gating */
-+	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-+
-+	/* Set MII clock */
-+#ifdef CONFIG_RGMII
-+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-+		CCM_GMAC_CTRL_GPIT_RGMII);
-+#else
-+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
-+		CCM_GMAC_CTRL_GPIT_MII);
-+#endif
-+
-+	/* Configure pin mux settings for GMAC */
-+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
-+#ifdef CONFIG_RGMII
-+		/* skip unused pins in RGMII mode */
-+		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
-+		    continue;
-+#endif
-+		sunxi_gpio_set_cfgpin(pin, 5);
-+		sunxi_gpio_set_drv(pin, 3);
-+	}
-+
-+#ifdef CONFIG_RGMII
-+	designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_RGMII);
-+#else
-+	designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
-+#endif
-+
-+	return 0;
-+}
-diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_wemac.c u-boot-sunxi/drivers/net/sunxi_wemac.c
---- u-boot-2014.01-rc1/drivers/net/sunxi_wemac.c	2013-11-25 22:49:32.000000000 +0100
+diff -ruN u-boot-2014.04/drivers/net/sunxi_wemac.c u-boot-sunxi/drivers/net/sunxi_wemac.c
+--- u-boot-2014.04/drivers/net/sunxi_wemac.c	2014-04-14 21:19:24.000000000 +0200
 +++ u-boot-sunxi/drivers/net/sunxi_wemac.c	1970-01-01 01:00:00.000000000 +0100
 @@ -1,525 +0,0 @@
 -/*
@@ -8729,31 +8075,15 @@ diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_wemac.c u-boot-sunxi/drivers/net/
 -
 -	return 0;
 -}
-diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/axp152.c
---- u-boot-2014.01-rc1/drivers/power/axp152.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/power/axp152.c	2014-03-05 23:14:48.060088066 +0100
-@@ -0,0 +1,138 @@
+diff -ruN u-boot-2014.04/drivers/power/axp152.c u-boot-sunxi/drivers/power/axp152.c
+--- u-boot-2014.04/drivers/power/axp152.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/power/axp152.c	2014-09-06 16:58:36.321953111 +0200
+@@ -0,0 +1,112 @@
 +/*
 + * (C) Copyright 2012
 + * Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +#include <common.h>
 +#include <i2c.h>
@@ -8768,26 +8098,35 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/a
 +	AXP152_SHUTDOWN = 0x32,
 +};
 +
-+int axp152_write(enum axp152_reg reg, u8 val)
++#define AXP152_POWEROFF			(1 << 7)
++
++static int axp152_write(enum axp152_reg reg, u8 val)
 +{
 +	return i2c_write(0x30, reg, 1, &val, 1);
 +}
 +
-+int axp152_read(enum axp152_reg reg, u8 *val)
++static int axp152_read(enum axp152_reg reg, u8 *val)
 +{
 +	return i2c_read(0x30, reg, 1, val, 1);
 +}
 +
++static int axp152_mvolt_to_target(int mvolt, int min, int max, int div)
++{
++	if (mvolt < min)
++		mvolt = min;
++	else if (mvolt > max)
++		mvolt = max;
++
++	return (mvolt - min) / div;
++}
++
 +int axp152_set_dcdc2(int mvolt)
 +{
-+	int target = (mvolt - 700) / 25;
-+	int rc;
++	int rc, target;
 +	u8 current;
 +
-+	if (target < 0)
-+		target = 0;
-+	if (target > (1<<6)-1)
-+		target = (1<<6)-1;
++	target = axp152_mvolt_to_target(mvolt, 700, 2275, 25);
++
 +	/* Do we really need to be this gentle? It has built-in voltage slope */
 +	while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, &current)) == 0 &&
 +	       current != target) {
@@ -8804,47 +8143,23 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/a
 +
 +int axp152_set_dcdc3(int mvolt)
 +{
-+	int target = (mvolt - 700) / 50;
-+	u8 reg;
-+	int rc;
++	int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
 +
-+	if (target < 0)
-+		target = 0;
-+	if (target > (1<<6)-1)
-+		target = (1<<6)-1;
-+	rc = axp152_write(AXP152_DCDC3_VOLTAGE, target);
-+	rc |= axp152_read(AXP152_DCDC3_VOLTAGE, &reg);
-+	return rc;
++	return axp152_write(AXP152_DCDC3_VOLTAGE, target);
 +}
 +
 +int axp152_set_dcdc4(int mvolt)
 +{
-+	int target = (mvolt - 700) / 25;
-+	u8 reg;
-+	int rc;
++	int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
 +
-+	if (target < 0)
-+		target = 0;
-+	if (target > (1<<7)-1)
-+		target = (1<<7)-1;
-+	rc = axp152_write(AXP152_DCDC4_VOLTAGE, target);
-+	rc |= axp152_read(AXP152_DCDC4_VOLTAGE, &reg);
-+	return rc;
++	return axp152_write(AXP152_DCDC4_VOLTAGE, target);
 +}
 +
 +int axp152_set_ldo2(int mvolt)
 +{
-+	int target = (mvolt - 700) / 100;
-+	int rc;
-+	u8 reg;
++	int target = axp152_mvolt_to_target(mvolt, 700, 3500, 100);
 +
-+	if (target < 0)
-+		target = 0;
-+	if (target > 31)
-+		target = 31;
-+	rc = axp152_write(AXP152_LDO2_VOLTAGE, target);
-+	rc |= axp152_read(AXP152_LDO2_VOLTAGE, &reg);
-+	return rc;
++	return axp152_write(AXP152_LDO2_VOLTAGE, target);
 +}
 +
 +void axp152_poweroff(void)
@@ -8853,9 +8168,12 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/a
 +
 +	if (axp152_read(AXP152_SHUTDOWN, &val) != 0)
 +		return;
-+	val |= 1 << 7;
++
++	val |= AXP152_POWEROFF;
++
 +	if (axp152_write(AXP152_SHUTDOWN, val) != 0)
 +		return;
++
 +	udelay(10000);	/* wait for power to drain */
 +}
 +
@@ -8867,35 +8185,21 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/a
 +	rc = axp152_read(AXP152_CHIP_VERSION, &ver);
 +	if (rc)
 +		return rc;
++
 +	if (ver != 0x05)
 +		return -1;
++
 +	return 0;
 +}
-diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/axp209.c
---- u-boot-2014.01-rc1/drivers/power/axp209.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/drivers/power/axp209.c	2014-03-05 23:14:48.060088066 +0100
-@@ -0,0 +1,215 @@
+diff -ruN u-boot-2014.04/drivers/power/axp209.c u-boot-sunxi/drivers/power/axp209.c
+--- u-boot-2014.04/drivers/power/axp209.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/power/axp209.c	2014-09-06 16:58:36.321953111 +0200
+@@ -0,0 +1,180 @@
 +/*
 + * (C) Copyright 2012
 + * Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
@@ -8909,39 +8213,43 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +	AXP209_DCDC3_VOLTAGE = 0x27,
 +	AXP209_LDO24_VOLTAGE = 0x28,
 +	AXP209_LDO3_VOLTAGE = 0x29,
-+	AXP209_IRQ_STATUS3 = 0x4a,
 +	AXP209_IRQ_STATUS5 = 0x4c,
 +	AXP209_SHUTDOWN = 0x32,
 +};
 +
-+#define AXP209_POWER_STATUS_ON_BY_DC	(1<<0)
++#define AXP209_POWER_STATUS_ON_BY_DC	(1 << 0)
 +
-+#define AXP209_IRQ3_PEK_SHORT		(1<<1)
-+#define AXP209_IRQ3_PEK_LONG		(1<<0)
++#define AXP209_IRQ5_PEK_UP		(1 << 6)
++#define AXP209_IRQ5_PEK_DOWN		(1 << 5)
 +
-+#define AXP209_IRQ5_PEK_UP		(1<<6)
-+#define AXP209_IRQ5_PEK_DOWN		(1<<5)
++#define AXP209_POWEROFF			(1 << 7)
 +
-+int axp209_write(enum axp209_reg reg, u8 val)
++static int axp209_write(enum axp209_reg reg, u8 val)
 +{
 +	return i2c_write(0x34, reg, 1, &val, 1);
 +}
 +
-+int axp209_read(enum axp209_reg reg, u8 *val)
++static int axp209_read(enum axp209_reg reg, u8 *val)
 +{
 +	return i2c_read(0x34, reg, 1, val, 1);
 +}
 +
++static int axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
++{
++	if (mvolt < min)
++		mvolt = min;
++	else if (mvolt > max)
++		mvolt = max;
++
++	return (mvolt - min) / div;
++}
++
 +int axp209_set_dcdc2(int mvolt)
 +{
-+	int cfg = (mvolt - 700) / 25;
-+	int rc;
++	int cfg, rc;
 +	u8 current;
 +
-+	if (cfg < 0)
-+		cfg = 0;
-+	if (cfg > (1 << 6) - 1)
-+		cfg = (1 << 6) - 1;
++	cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
 +
 +	/* Do we really need to be this gentle? It has built-in voltage slope */
 +	while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, &current)) == 0 &&
@@ -8961,62 +8269,40 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +
 +int axp209_set_dcdc3(int mvolt)
 +{
-+	int cfg = (mvolt - 700) / 25;
-+	u8 reg;
-+	int rc;
++	int cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
 +
-+	if (cfg < 0)
-+		cfg = 0;
-+	if (cfg > (1 << 7) - 1)
-+		cfg = (1 << 7) - 1;
-+
-+	rc = axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
-+	rc |= axp209_read(AXP209_DCDC3_VOLTAGE, &reg);
-+
-+	return rc;
++	return axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
 +}
 +
 +int axp209_set_ldo2(int mvolt)
 +{
-+	int cfg = (mvolt - 1800) / 100;
-+	int rc;
++	int rc, cfg;
 +	u8 reg;
 +
-+	if (cfg < 0)
-+		cfg = 0;
-+	if (cfg > 15)
-+		cfg = 15;
++	cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
 +
 +	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
 +	if (rc)
 +		return rc;
 +
++	/* LDO2 configuration is in upper 4 bits */
 +	reg = (reg & 0x0f) | (cfg << 4);
-+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
-+	if (rc)
-+		return rc;
-+
-+	return 0;
++	return axp209_write(AXP209_LDO24_VOLTAGE, reg);
 +}
 +
 +int axp209_set_ldo3(int mvolt)
 +{
-+	int cfg = (mvolt - 700) / 25;
++	int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
 +
-+	if (cfg < 0)
-+		cfg = 0;
-+	if (cfg > 127)
-+		cfg = 127;
 +	if (mvolt == -1)
-+		cfg = 0x80;	/* detemined by LDO3IN pin */
++		cfg = 0x80;	/* determined by LDO3IN pin */
 +
 +	return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
 +}
 +
 +int axp209_set_ldo4(int mvolt)
 +{
-+	int cfg = (mvolt - 1800) / 100;
-+	int rc;
++	int cfg, rc;
 +	static const int vindex[] = {
 +		1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
 +		2700, 2800, 3000, 3100, 3200, 3300
@@ -9024,7 +8310,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +	u8 reg;
 +
 +	/* Translate mvolt to register cfg value, requested <= selected */
-+	for (cfg = 0; mvolt < vindex[cfg] && cfg < 15; cfg++);
++	for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
 +
 +	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
 +	if (rc)
@@ -9032,11 +8318,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +
 +	/* LDO4 configuration is in lower 4 bits */
 +	reg = (reg & 0xf0) | (cfg << 0);
-+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
-+	if (rc)
-+		return rc;
-+
-+	return 0;
++	return axp209_write(AXP209_LDO24_VOLTAGE, reg);
 +}
 +
 +void axp209_poweroff(void)
@@ -9046,7 +8328,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +	if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
 +		return;
 +
-+	val |= 1 << 7;
++	val |= AXP209_POWEROFF;
 +
 +	if (axp209_write(AXP209_SHUTDOWN, val) != 0)
 +		return;
@@ -9078,6 +8360,7 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +
 +	if (axp209_read(AXP209_POWER_STATUS, &v))
 +		return 0;
++
 +	return (v & AXP209_POWER_STATUS_ON_BY_DC);
 +}
 +
@@ -9087,24 +8370,104 @@ diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/a
 +
 +	if (axp209_read(AXP209_IRQ_STATUS5, &v))
 +		return 0;
++
 +	axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
++
 +	return v & AXP209_IRQ5_PEK_DOWN;
 +}
-diff -ruN u-boot-2014.01-rc1/drivers/power/Makefile u-boot-sunxi/drivers/power/Makefile
---- u-boot-2014.01-rc1/drivers/power/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/power/Makefile	2014-03-05 23:14:48.060088066 +0100
-@@ -5,6 +5,8 @@
+diff -ruN u-boot-2014.04/drivers/power/axp221.c u-boot-sunxi/drivers/power/axp221.c
+--- u-boot-2014.04/drivers/power/axp221.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/drivers/power/axp221.c	2014-09-06 16:58:36.321953111 +0200
+@@ -0,0 +1,73 @@
++/*
++ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#include <common.h>
++#include <errno.h>
++#include <asm/arch/p2wi.h>
++#include <axp221.h>
++
++int axp221_set_dcdc1(unsigned int mvolt)
++{
++	return p2wi_write(AXP221_DCDC1_CTRL, (mvolt - 1600) / 100);
++}
++
++int axp221_set_dcdc2(unsigned int mvolt)
++{
++	return p2wi_write(AXP221_DCDC2_CTRL, (mvolt - 600) / 20);
++}
++
++int axp221_set_dcdc3(unsigned int mvolt)
++{
++	return p2wi_write(AXP221_DCDC3_CTRL, (mvolt - 600) / 20);
++}
++
++int axp221_set_dcdc4(unsigned int mvolt)
++{
++	return p2wi_write(AXP221_DCDC4_CTRL, (mvolt - 600) / 20);
++}
++
++int axp221_set_dcdc5(unsigned int mvolt)
++{
++	return p2wi_write(AXP221_DCDC5_CTRL, (mvolt - 600) / 20);
++}
++
++int axp221_set_dldo1(unsigned int mvolt)
++{
++	int ret;
++	u8 val;
++
++	ret = p2wi_write(AXP221_DLDO1_CTRL, (mvolt - 700) / 100);
++	if (ret)
++		return ret;
++
++	ret = p2wi_read(AXP221_OUTPUT_CTRL2, &val);
++	if (ret)
++		return ret;
++
++	val |= 1 << 3;
++	return p2wi_write(AXP221_OUTPUT_CTRL2, val);
++}
++
++int axp221_init(void)
++{
++	u8 axp_chip_id;
++	int ret;
++
++	p2wi_init();
++	ret = p2wi_set_pmu_address(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
++				   AXP221_INIT_DATA);
++	if (ret)
++		return ret;
++
++	ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id);
++	if (ret)
++		return ret;
++
++	if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
++		return -ENODEV;
++
++	return 0;
++}
+diff -ruN u-boot-2014.04/drivers/power/Makefile u-boot-sunxi/drivers/power/Makefile
+--- u-boot-2014.04/drivers/power/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/power/Makefile	2014-09-06 16:58:36.321953111 +0200
+@@ -5,6 +5,9 @@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
 +obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 +obj-$(CONFIG_AXP209_POWER)	+= axp209.o
++obj-$(CONFIG_AXP221_POWER)	+= axp221.o
  obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
  obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
  obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
-diff -ruN u-boot-2014.01-rc1/drivers/serial/arm_dcc.c u-boot-sunxi/drivers/serial/arm_dcc.c
---- u-boot-2014.01-rc1/drivers/serial/arm_dcc.c	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/drivers/serial/arm_dcc.c	2014-03-05 23:14:48.068087958 +0100
+diff -ruN u-boot-2014.04/drivers/serial/arm_dcc.c u-boot-sunxi/drivers/serial/arm_dcc.c
+--- u-boot-2014.04/drivers/serial/arm_dcc.c	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/drivers/serial/arm_dcc.c	2014-09-06 16:58:36.329953111 +0200
 @@ -29,7 +29,7 @@
  #include <common.h>
  #include <serial.h>
@@ -9114,9 +8477,9 @@ diff -ruN u-boot-2014.01-rc1/drivers/serial/arm_dcc.c u-boot-sunxi/drivers/seria
  /*
   * ARMV6
   */
-diff -ruN u-boot-2014.01-rc1/.git/config u-boot-sunxi/.git/config
---- u-boot-2014.01-rc1/.git/config	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/config	2014-03-05 23:14:46.924103235 +0100
+diff -ruN u-boot-2014.04/.git/config u-boot-sunxi/.git/config
+--- u-boot-2014.04/.git/config	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/config	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1,11 @@
 +[core]
 +	repositoryformatversion = 0
@@ -9125,23 +8488,23 @@ diff -ruN u-boot-2014.01-rc1/.git/config u-boot-sunxi/.git/config
 +	logallrefupdates = true
 +[remote "origin"]
 +	fetch = +refs/heads/*:refs/remotes/origin/*
-+	url = https://bitbucket.org/zuperman/u-boot-sunxi.git
-+[branch "sunxi-openwrt"]
++	url = https://github.com/linux-sunxi/u-boot-sunxi
++[branch "sunxi"]
 +	remote = origin
-+	merge = refs/heads/sunxi-openwrt
-diff -ruN u-boot-2014.01-rc1/.git/description u-boot-sunxi/.git/description
---- u-boot-2014.01-rc1/.git/description	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/description	2014-03-05 23:14:20.056462031 +0100
++	merge = refs/heads/sunxi
+diff -ruN u-boot-2014.04/.git/description u-boot-sunxi/.git/description
+--- u-boot-2014.04/.git/description	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/description	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1 @@
 +Unnamed repository; edit this file 'description' to name the repository.
-diff -ruN u-boot-2014.01-rc1/.git/HEAD u-boot-sunxi/.git/HEAD
---- u-boot-2014.01-rc1/.git/HEAD	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/HEAD	2014-03-05 23:14:46.924103235 +0100
+diff -ruN u-boot-2014.04/.git/HEAD u-boot-sunxi/.git/HEAD
+--- u-boot-2014.04/.git/HEAD	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/HEAD	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+ref: refs/heads/sunxi-openwrt
-diff -ruN u-boot-2014.01-rc1/.git/hooks/applypatch-msg.sample u-boot-sunxi/.git/hooks/applypatch-msg.sample
---- u-boot-2014.01-rc1/.git/hooks/applypatch-msg.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/applypatch-msg.sample	2014-03-05 23:14:20.072461819 +0100
++ref: refs/heads/sunxi
+diff -ruN u-boot-2014.04/.git/hooks/applypatch-msg.sample u-boot-sunxi/.git/hooks/applypatch-msg.sample
+--- u-boot-2014.04/.git/hooks/applypatch-msg.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/applypatch-msg.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,15 @@
 +#!/bin/sh
 +#
@@ -9158,9 +8521,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/applypatch-msg.sample u-boot-sunxi/.git/
 +test -x "$GIT_DIR/hooks/commit-msg" &&
 +	exec "$GIT_DIR/hooks/commit-msg" ${1+"$@"}
 +:
-diff -ruN u-boot-2014.01-rc1/.git/hooks/commit-msg.sample u-boot-sunxi/.git/hooks/commit-msg.sample
---- u-boot-2014.01-rc1/.git/hooks/commit-msg.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/commit-msg.sample	2014-03-05 23:14:20.064461925 +0100
+diff -ruN u-boot-2014.04/.git/hooks/commit-msg.sample u-boot-sunxi/.git/hooks/commit-msg.sample
+--- u-boot-2014.04/.git/hooks/commit-msg.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/commit-msg.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,24 @@
 +#!/bin/sh
 +#
@@ -9186,9 +8549,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/commit-msg.sample u-boot-sunxi/.git/hook
 +	echo >&2 Duplicate Signed-off-by lines.
 +	exit 1
 +}
-diff -ruN u-boot-2014.01-rc1/.git/hooks/post-update.sample u-boot-sunxi/.git/hooks/post-update.sample
---- u-boot-2014.01-rc1/.git/hooks/post-update.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/post-update.sample	2014-03-05 23:14:20.076461764 +0100
+diff -ruN u-boot-2014.04/.git/hooks/post-update.sample u-boot-sunxi/.git/hooks/post-update.sample
+--- u-boot-2014.04/.git/hooks/post-update.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/post-update.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,8 @@
 +#!/bin/sh
 +#
@@ -9198,9 +8561,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/post-update.sample u-boot-sunxi/.git/hoo
 +# To enable this hook, rename this file to "post-update".
 +
 +exec git update-server-info
-diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-applypatch.sample u-boot-sunxi/.git/hooks/pre-applypatch.sample
---- u-boot-2014.01-rc1/.git/hooks/pre-applypatch.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/pre-applypatch.sample	2014-03-05 23:14:20.072461819 +0100
+diff -ruN u-boot-2014.04/.git/hooks/pre-applypatch.sample u-boot-sunxi/.git/hooks/pre-applypatch.sample
+--- u-boot-2014.04/.git/hooks/pre-applypatch.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/pre-applypatch.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,14 @@
 +#!/bin/sh
 +#
@@ -9216,9 +8579,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-applypatch.sample u-boot-sunxi/.git/
 +test -x "$GIT_DIR/hooks/pre-commit" &&
 +	exec "$GIT_DIR/hooks/pre-commit" ${1+"$@"}
 +:
-diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-commit.sample u-boot-sunxi/.git/hooks/pre-commit.sample
---- u-boot-2014.01-rc1/.git/hooks/pre-commit.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/pre-commit.sample	2014-03-05 23:14:20.076461764 +0100
+diff -ruN u-boot-2014.04/.git/hooks/pre-commit.sample u-boot-sunxi/.git/hooks/pre-commit.sample
+--- u-boot-2014.04/.git/hooks/pre-commit.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/pre-commit.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,50 @@
 +#!/bin/sh
 +#
@@ -9270,9 +8633,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-commit.sample u-boot-sunxi/.git/hook
 +
 +# If there are whitespace errors, print the offending file names and fail.
 +exec git diff-index --check --cached $against --
-diff -ruN u-boot-2014.01-rc1/.git/hooks/prepare-commit-msg.sample u-boot-sunxi/.git/hooks/prepare-commit-msg.sample
---- u-boot-2014.01-rc1/.git/hooks/prepare-commit-msg.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/prepare-commit-msg.sample	2014-03-05 23:14:20.076461764 +0100
+diff -ruN u-boot-2014.04/.git/hooks/prepare-commit-msg.sample u-boot-sunxi/.git/hooks/prepare-commit-msg.sample
+--- u-boot-2014.04/.git/hooks/prepare-commit-msg.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/prepare-commit-msg.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,36 @@
 +#!/bin/sh
 +#
@@ -9310,9 +8673,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/prepare-commit-msg.sample u-boot-sunxi/.
 +
 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
-diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-rebase.sample u-boot-sunxi/.git/hooks/pre-rebase.sample
---- u-boot-2014.01-rc1/.git/hooks/pre-rebase.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/pre-rebase.sample	2014-03-05 23:14:20.076461764 +0100
+diff -ruN u-boot-2014.04/.git/hooks/pre-rebase.sample u-boot-sunxi/.git/hooks/pre-rebase.sample
+--- u-boot-2014.04/.git/hooks/pre-rebase.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/pre-rebase.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,169 @@
 +#!/bin/sh
 +#
@@ -9483,9 +8846,9 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-rebase.sample u-boot-sunxi/.git/hook
 +	if this is empty, it is fully merged to "master".
 +
 +DOC_END
-diff -ruN u-boot-2014.01-rc1/.git/hooks/update.sample u-boot-sunxi/.git/hooks/update.sample
---- u-boot-2014.01-rc1/.git/hooks/update.sample	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/hooks/update.sample	2014-03-05 23:14:20.068461872 +0100
+diff -ruN u-boot-2014.04/.git/hooks/update.sample u-boot-sunxi/.git/hooks/update.sample
+--- u-boot-2014.04/.git/hooks/update.sample	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/hooks/update.sample	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,128 @@
 +#!/bin/sh
 +#
@@ -9615,10 +8978,10 @@ diff -ruN u-boot-2014.01-rc1/.git/hooks/update.sample u-boot-sunxi/.git/hooks/up
 +
 +# --- Finished
 +exit 0
-Binary files u-boot-2014.01-rc1/.git/index and u-boot-sunxi/.git/index differ
-diff -ruN u-boot-2014.01-rc1/.git/info/exclude u-boot-sunxi/.git/info/exclude
---- u-boot-2014.01-rc1/.git/info/exclude	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/info/exclude	2014-03-05 23:14:20.064461925 +0100
+Binary files u-boot-2014.04/.git/index and u-boot-sunxi/.git/index differ
+diff -ruN u-boot-2014.04/.git/info/exclude u-boot-sunxi/.git/info/exclude
+--- u-boot-2014.04/.git/info/exclude	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/info/exclude	2014-09-06 16:58:09.553953909 +0200
 @@ -0,0 +1,6 @@
 +# git ls-files --others --exclude-from=.git/info/exclude
 +# Lines that start with '#' are comments.
@@ -9626,67 +8989,70 @@ diff -ruN u-boot-2014.01-rc1/.git/info/exclude u-boot-sunxi/.git/info/exclude
 +# exclude patterns (uncomment them if you want to use them):
 +# *.[oa]
 +# *~
-diff -ruN u-boot-2014.01-rc1/.git/logs/HEAD u-boot-sunxi/.git/logs/HEAD
---- u-boot-2014.01-rc1/.git/logs/HEAD	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/logs/HEAD	2014-03-05 23:14:46.924103235 +0100
+diff -ruN u-boot-2014.04/.git/logs/HEAD u-boot-sunxi/.git/logs/HEAD
+--- u-boot-2014.04/.git/logs/HEAD	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/logs/HEAD	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+0000000000000000000000000000000000000000 d57e8f49a52e59486f49346975c826cf4c298d7e root <root@trabant.deployis.eu> 1394057686 +0100	clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
-diff -ruN u-boot-2014.01-rc1/.git/logs/refs/heads/sunxi-openwrt u-boot-sunxi/.git/logs/refs/heads/sunxi-openwrt
---- u-boot-2014.01-rc1/.git/logs/refs/heads/sunxi-openwrt	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/logs/refs/heads/sunxi-openwrt	2014-03-05 23:14:46.924103235 +0100
++0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200	clone: from https://github.com/linux-sunxi/u-boot-sunxi
+diff -ruN u-boot-2014.04/.git/logs/refs/heads/sunxi u-boot-sunxi/.git/logs/refs/heads/sunxi
+--- u-boot-2014.04/.git/logs/refs/heads/sunxi	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/logs/refs/heads/sunxi	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+0000000000000000000000000000000000000000 d57e8f49a52e59486f49346975c826cf4c298d7e root <root@trabant.deployis.eu> 1394057686 +0100	clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
-diff -ruN u-boot-2014.01-rc1/.git/logs/refs/remotes/origin/HEAD u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD
---- u-boot-2014.01-rc1/.git/logs/refs/remotes/origin/HEAD	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD	2014-03-05 23:14:46.924103235 +0100
++0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200	clone: from https://github.com/linux-sunxi/u-boot-sunxi
+diff -ruN u-boot-2014.04/.git/logs/refs/remotes/origin/HEAD u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD
+--- u-boot-2014.04/.git/logs/refs/remotes/origin/HEAD	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+0000000000000000000000000000000000000000 a13f6664d65ce9bc68f05f8ecd10333ea9bcb012 root <root@trabant.deployis.eu> 1394057686 +0100	clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
-Binary files u-boot-2014.01-rc1/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.idx and u-boot-sunxi/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.idx differ
-Binary files u-boot-2014.01-rc1/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.pack and u-boot-sunxi/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.pack differ
-diff -ruN u-boot-2014.01-rc1/.git/packed-refs u-boot-sunxi/.git/packed-refs
---- u-boot-2014.01-rc1/.git/packed-refs	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/packed-refs	2014-03-05 23:14:46.760105425 +0100
-@@ -0,0 +1,6 @@
++0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200	clone: from https://github.com/linux-sunxi/u-boot-sunxi
+Binary files u-boot-2014.04/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.idx and u-boot-sunxi/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.idx differ
+Binary files u-boot-2014.04/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.pack and u-boot-sunxi/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.pack differ
+diff -ruN u-boot-2014.04/.git/packed-refs u-boot-sunxi/.git/packed-refs
+--- u-boot-2014.04/.git/packed-refs	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/packed-refs	2014-09-06 16:58:35.001953150 +0200
+@@ -0,0 +1,25 @@
 +# pack-refs with: peeled 
-+b83a10f893c1b36b878a4dc992a68879f2d98153 refs/remotes/origin/sunxi-3.12
-+d57e8f49a52e59486f49346975c826cf4c298d7e refs/remotes/origin/sunxi-openwrt
-+a13f6664d65ce9bc68f05f8ecd10333ea9bcb012 refs/remotes/origin/sunxi-test
-+adc9e13225d092362dea4e83c03ee161859f3a94 refs/tags/sunxi-openwrt-1
-+^d57e8f49a52e59486f49346975c826cf4c298d7e
-diff -ruN u-boot-2014.01-rc1/.git/refs/heads/sunxi-openwrt u-boot-sunxi/.git/refs/heads/sunxi-openwrt
---- u-boot-2014.01-rc1/.git/refs/heads/sunxi-openwrt	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/refs/heads/sunxi-openwrt	2014-03-05 23:14:46.924103235 +0100
++3212c6fd4beaa14a21a57e5241022702c986f82e refs/remotes/origin/lichee-dev
++c0860ba179bc0cf016831ceeeacd0dd4e287a860 refs/remotes/origin/lichee-dev-a20
++1076d3bdd67db39f34bc91857c636525874441ae refs/remotes/origin/lichee/lichee-dev
++40b4fba701c1824cc60c7ab966f4a5dd674e947d refs/remotes/origin/lichee/lichee-dev-ICS
++cf54463fd782c690cf790ca35b5a15504b57c287 refs/remotes/origin/lichee/lichee-dev-mmc
++218f643881c0dabd7e40cdb21a757416fa80afb2 refs/remotes/origin/old/sunxi-current
++509d96d4f1f602d62d36db660973249e16f9d088 refs/remotes/origin/sunxi
++43fb1236c3330676f49220cc1dfc235eb0558e4c refs/remotes/origin/sunxi-patchqueue
++80fd9a5c5b87ba2f48f4a71b666839870e780be6 refs/remotes/origin/wip/a20
++27113637710a574d1fb6325817ffa9ced7afe019 refs/tags/v2011.09-sun4i
++^22b38fa5c0348ac4f285f038999f9a617f98e73a
++9ba56441491542cd06b30c514e544d96b29ef801 refs/tags/v2011.09-sun4i-20120808
++88eacf3372855579760ba6bc8fa3e0d4e53fdef8 refs/tags/v2012.10-sunxi
++1ae18d97d24c5d6dd4cb7949d8e5fb602728601c refs/tags/v2013.01-sunxi
++fc40799c144d035c595c4abe3032a03be8f0e2c4 refs/tags/v2013.01.01-sunxi
++90c8c0c88362d1e39bb1433f04b9a21bb1c74e45 refs/tags/v2013.04-sunxi
++57ff4519ba0f47f1647f7def5864ae4c9ef3e6a0 refs/tags/v2013.07-rc1-sunxi
++c416374795b584f025a80b1f81db215456567155 refs/tags/v2013.07-sunxi
++8969c6f654248ececdfcf05eb51de9a8bc0a8703 refs/tags/v2013.07-sunxi.2
++88b1df7ee9c15c821a2209791f513b21596f21b4 refs/tags/v2013.07-sunxi.3
++569c37da7dfd4ed93b6e8b5993df760b9ed18c8d refs/tags/v2013.07-sunxi.4
++7a63a6882876b76e47746c1254e8cd1120a52b0d refs/tags/v2013.10-rc1-sunxi
++951e509384822e39149c22f44cde6a01f5105c40 refs/tags/v2013.10-rc2-sunxi
++09ef3a640a3eb58e66eedcf239193e2ab548e730 refs/tags/v2013.10-sunxi
+diff -ruN u-boot-2014.04/.git/refs/heads/sunxi u-boot-sunxi/.git/refs/heads/sunxi
+--- u-boot-2014.04/.git/refs/heads/sunxi	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/refs/heads/sunxi	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+d57e8f49a52e59486f49346975c826cf4c298d7e
-diff -ruN u-boot-2014.01-rc1/.git/refs/remotes/origin/HEAD u-boot-sunxi/.git/refs/remotes/origin/HEAD
---- u-boot-2014.01-rc1/.git/refs/remotes/origin/HEAD	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/.git/refs/remotes/origin/HEAD	2014-03-05 23:14:46.852104197 +0100
++509d96d4f1f602d62d36db660973249e16f9d088
+diff -ruN u-boot-2014.04/.git/refs/remotes/origin/HEAD u-boot-sunxi/.git/refs/remotes/origin/HEAD
+--- u-boot-2014.04/.git/refs/remotes/origin/HEAD	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/.git/refs/remotes/origin/HEAD	2014-09-06 16:58:35.001953150 +0200
 @@ -0,0 +1 @@
-+ref: refs/remotes/origin/sunxi-test
-diff -ruN u-boot-2014.01-rc1/include/axp152.h u-boot-sunxi/include/axp152.h
---- u-boot-2014.01-rc1/include/axp152.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/axp152.h	2014-03-05 23:14:48.156086783 +0100
-@@ -0,0 +1,27 @@
++ref: refs/remotes/origin/sunxi
+diff -ruN u-boot-2014.04/include/axp152.h u-boot-sunxi/include/axp152.h
+--- u-boot-2014.04/include/axp152.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/axp152.h	2014-09-06 16:58:36.397953109 +0200
+@@ -0,0 +1,11 @@
 +/*
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +int axp152_set_dcdc2(int mvolt);
 +int axp152_set_dcdc3(int mvolt);
@@ -9694,30 +9060,14 @@ diff -ruN u-boot-2014.01-rc1/include/axp152.h u-boot-sunxi/include/axp152.h
 +int axp152_set_ldo2(int mvolt);
 +void axp152_poweroff(void);
 +int axp152_init(void);
-diff -ruN u-boot-2014.01-rc1/include/axp209.h u-boot-sunxi/include/axp209.h
---- u-boot-2014.01-rc1/include/axp209.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/axp209.h	2014-03-05 23:14:48.156086783 +0100
-@@ -0,0 +1,31 @@
+diff -ruN u-boot-2014.04/include/axp209.h u-boot-sunxi/include/axp209.h
+--- u-boot-2014.04/include/axp209.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/axp209.h	2014-09-06 16:58:36.397953109 +0200
+@@ -0,0 +1,15 @@
 +/*
 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +extern int axp209_set_dcdc2(int mvolt);
@@ -9729,22 +9079,44 @@ diff -ruN u-boot-2014.01-rc1/include/axp209.h u-boot-sunxi/include/axp209.h
 +extern int axp209_init(void);
 +extern int axp209_poweron_by_dc(void);
 +extern int axp209_power_button(void);
-diff -ruN u-boot-2014.01-rc1/include/common.h u-boot-sunxi/include/common.h
---- u-boot-2014.01-rc1/include/common.h	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/include/common.h	2014-03-05 23:14:48.160086731 +0100
-@@ -453,7 +453,7 @@
- void	api_init (void);
- 
- /* common/memsize.c */
--long	get_ram_size  (long *, long);
-+unsigned long	get_ram_size  (unsigned long *, unsigned long);
- 
- /* $(BOARD)/$(BOARD).c */
- void	reset_phy     (void);
-diff -ruN u-boot-2014.01-rc1/include/config_fallbacks.h u-boot-sunxi/include/config_fallbacks.h
---- u-boot-2014.01-rc1/include/config_fallbacks.h	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/include/config_fallbacks.h	2014-03-05 23:14:48.160086731 +0100
-@@ -54,6 +54,10 @@
+diff -ruN u-boot-2014.04/include/axp221.h u-boot-sunxi/include/axp221.h
+--- u-boot-2014.04/include/axp221.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/axp221.h	2014-09-06 16:58:36.397953109 +0200
+@@ -0,0 +1,30 @@
++/*
++ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
++ *
++ * X-Powers AXP221 Power Management IC driver
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#define AXP221_CHIP_ADDR 0x68
++#define AXP221_CTRL_ADDR 0x3e
++#define AXP221_INIT_DATA 0x3e
++
++#define AXP221_CHIP_ID		0x03
++#define AXP221_OUTPUT_CTRL1	0x10
++#define AXP221_OUTPUT_CTRL2	0x12
++#define AXP221_OUTPUT_CTRL3	0x13
++#define AXP221_DLDO1_CTRL	0x15
++#define AXP221_DCDC1_CTRL	0x21
++#define AXP221_DCDC2_CTRL	0x22
++#define AXP221_DCDC3_CTRL	0x23
++#define AXP221_DCDC4_CTRL	0x24
++#define AXP221_DCDC5_CTRL	0x25
++
++int axp221_set_dcdc1(unsigned int mvolt);
++int axp221_set_dcdc2(unsigned int mvolt);
++int axp221_set_dcdc3(unsigned int mvolt);
++int axp221_set_dcdc4(unsigned int mvolt);
++int axp221_set_dcdc5(unsigned int mvolt);
++int axp221_set_dldo1(unsigned int mvolt);
++int axp221_init(void);
+diff -ruN u-boot-2014.04/include/config_fallbacks.h u-boot-sunxi/include/config_fallbacks.h
+--- u-boot-2014.04/include/config_fallbacks.h	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/include/config_fallbacks.h	2014-09-06 16:58:36.401953108 +0200
+@@ -55,6 +55,10 @@
  #define HAVE_BLOCK_DEVICE
  #endif
  
@@ -9752,37 +9124,20 @@ diff -ruN u-boot-2014.01-rc1/include/config_fallbacks.h u-boot-sunxi/include/con
 +#define CONFIG_SYS_BOARD_NAME CONFIG_SYS_TARGET
 +#endif
 +
- #ifndef CONFIG_SYS_PROMPT
- #define CONFIG_SYS_PROMPT	"=> "
- #endif
-diff -ruN u-boot-2014.01-rc1/include/configs/sun4i.h u-boot-sunxi/include/configs/sun4i.h
---- u-boot-2014.01-rc1/include/configs/sun4i.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/configs/sun4i.h	2014-03-05 23:14:48.236085715 +0100
-@@ -0,0 +1,41 @@
+ #if (defined(CONFIG_PARTITION_UUIDS) || \
+ 	defined(CONFIG_EFI_PARTITION) || \
+ 	defined(CONFIG_RANDOM_UUID) || \
+diff -ruN u-boot-2014.04/include/configs/sun4i.h u-boot-sunxi/include/configs/sun4i.h
+--- u-boot-2014.04/include/configs/sun4i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sun4i.h	2014-09-06 16:58:36.461953107 +0200
+@@ -0,0 +1,25 @@
 +/*
 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
 + * Configuration settings for the Allwinner A10 (sun4i) CPU
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
@@ -9790,6 +9145,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun4i.h u-boot-sunxi/include/config
 + * A10 specific configuration
 + */
 +#define CONFIG_SUN4I		/* sun4i SoC generation */
++#define CONFIG_CLK_FULL_SPEED		1008000000
 +
 +#define CONFIG_SYS_PROMPT		"sun4i# "
 +#define CONFIG_MACH_TYPE		4104
@@ -9800,34 +9156,17 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun4i.h u-boot-sunxi/include/config
 +#include <configs/sunxi-common.h>
 +
 +#endif /* __CONFIG_H */
-diff -ruN u-boot-2014.01-rc1/include/configs/sun5i.h u-boot-sunxi/include/configs/sun5i.h
---- u-boot-2014.01-rc1/include/configs/sun5i.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/configs/sun5i.h	2014-03-05 23:14:48.236085715 +0100
-@@ -0,0 +1,41 @@
+diff -ruN u-boot-2014.04/include/configs/sun5i.h u-boot-sunxi/include/configs/sun5i.h
+--- u-boot-2014.04/include/configs/sun5i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sun5i.h	2014-09-06 16:58:36.461953107 +0200
+@@ -0,0 +1,25 @@
 +/*
 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
 + * Configuration settings for the Allwinner A13 (sun5i) CPU
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
@@ -9835,6 +9174,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun5i.h u-boot-sunxi/include/config
 + * High Level Configuration Options
 + */
 +#define CONFIG_SUN5I		/* sun5i SoC generation */
++#define CONFIG_CLK_FULL_SPEED		1008000000
 +
 +#define CONFIG_SYS_PROMPT		"sun5i# "
 +#define CONFIG_MACH_TYPE		4138
@@ -9845,9 +9185,9 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun5i.h u-boot-sunxi/include/config
 +#include <configs/sunxi-common.h>
 +
 +#endif /* __CONFIG_H */
-diff -ruN u-boot-2014.01-rc1/include/configs/sun6i.h u-boot-sunxi/include/configs/sun6i.h
---- u-boot-2014.01-rc1/include/configs/sun6i.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/configs/sun6i.h	2014-03-05 23:14:48.236085715 +0100
+diff -ruN u-boot-2014.04/include/configs/sun6i.h u-boot-sunxi/include/configs/sun6i.h
+--- u-boot-2014.04/include/configs/sun6i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sun6i.h	2014-09-06 16:58:36.461953107 +0200
 @@ -0,0 +1,43 @@
 +/*
 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
@@ -9892,35 +9232,18 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun6i.h u-boot-sunxi/include/config
 +#include <configs/sunxi-common.h>
 +
 +#endif /* __CONFIG_H */
-diff -ruN u-boot-2014.01-rc1/include/configs/sun7i.h u-boot-sunxi/include/configs/sun7i.h
---- u-boot-2014.01-rc1/include/configs/sun7i.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/configs/sun7i.h	2014-03-05 23:14:48.236085715 +0100
-@@ -0,0 +1,53 @@
+diff -ruN u-boot-2014.04/include/configs/sun7i.h u-boot-sunxi/include/configs/sun7i.h
+--- u-boot-2014.04/include/configs/sun7i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sun7i.h	2014-09-06 16:58:36.461953107 +0200
+@@ -0,0 +1,30 @@
 +/*
 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 + *
 + * Configuration settings for the Allwinner A20 (sun7i) CPU
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +#ifndef __CONFIG_H
 +#define __CONFIG_H
 +
@@ -9928,6 +9251,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun7i.h u-boot-sunxi/include/config
 + * A20 specific configuration
 + */
 +#define CONFIG_SUN7I		/* sun7i SoC generation */
++#define CONFIG_CLK_FULL_SPEED		912000000
 +
 +#define CONFIG_SYS_PROMPT		"sun7i# "
 +#define CONFIG_MACH_TYPE		4283
@@ -9936,12 +9260,37 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun7i.h u-boot-sunxi/include/config
 +#define CONFIG_BOARD_POSTCLK_INIT 1
 +#endif
 +
-+#define CONFIG_ARMV7_VIRT		1
-+#define CONFIG_ARMV7_NONSEC		1
-+#define CONFIG_ARMV7_PSCI		1
-+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
-+#define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
-+#define CONFIG_SYS_CLK_FREQ		24000000
++/*
++ * Include common sunxi configuration where most the settings are
++ */
++#include <configs/sunxi-common.h>
++
++#endif /* __CONFIG_H */
+diff -ruN u-boot-2014.04/include/configs/sun8i.h u-boot-sunxi/include/configs/sun8i.h
+--- u-boot-2014.04/include/configs/sun8i.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sun8i.h	2014-09-06 16:58:36.461953107 +0200
+@@ -0,0 +1,28 @@
++/*
++ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
++ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
++ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
++ * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
++ *
++ * Configuration settings for the Allwinner A23 (sun8i) CPU
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/*
++ * A23 specific configuration
++ */
++#define CONFIG_SUN8I		/* sun8i SoC generation */
++
++#define CONFIG_SYS_PROMPT		"sun8i# "
++#define CONFIG_MACH_TYPE		4137
 +
 +/*
 + * Include common sunxi configuration where most the settings are
@@ -9949,10 +9298,10 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sun7i.h u-boot-sunxi/include/config
 +#include <configs/sunxi-common.h>
 +
 +#endif /* __CONFIG_H */
-diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include/configs/sunxi-common.h
---- u-boot-2014.01-rc1/include/configs/sunxi-common.h	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/include/configs/sunxi-common.h	2014-03-05 23:14:48.236085715 +0100
-@@ -0,0 +1,478 @@
+diff -ruN u-boot-2014.04/include/configs/sunxi-common.h u-boot-sunxi/include/configs/sunxi-common.h
+--- u-boot-2014.04/include/configs/sunxi-common.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/include/configs/sunxi-common.h	2014-09-06 16:58:36.461953107 +0200
+@@ -0,0 +1,427 @@
 +/*
 + * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 + *
@@ -9962,23 +9311,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 + *
 + * Configuration settings for the Allwinner sunxi series of boards.
 + *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef _SUNXI_COMMON_CONFIG_H
@@ -9987,8 +9320,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +/*
 + * High Level Configuration Options
 + */
-+#define CONFIG_ALLWINNER	/* It's a Allwinner chip */
-+#define CONFIG_SUNXI		/* which is sunxi family */
++#define CONFIG_SUNXI		/* sunxi family */
 +#ifdef CONFIG_SPL_BUILD
 +#ifndef CONFIG_SPL_FEL
 +#define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
@@ -10009,12 +9341,13 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#define CONFIG_SYS_NS16550
 +#define CONFIG_SYS_NS16550_SERIAL
 +/* ns16550 reg in the low bits of cpu reg */
-+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-+#define CONFIG_SYS_NS16550_CLK		(24000000)
++#define CONFIG_SYS_NS16550_REG_SIZE	-4
++#define CONFIG_SYS_NS16550_CLK		24000000
 +#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
 +#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
 +#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
 +#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
++#define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 +
 +/* DRAM Base */
 +#define CONFIG_SYS_SDRAM_BASE		0x40000000
@@ -10029,7 +9362,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +/* A10 has 1 banks of DRAM, we use only bank 1 in U-Boot */
 +#define CONFIG_NR_DRAM_BANKS		1
 +#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
-+#ifdef CONFIG_SUN7I
++#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I)
 +#define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 +#else
 +#define PHYS_SDRAM_0_SIZE		0x40000000 /* 1 GiB */
@@ -10049,11 +9382,9 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#define CONFIG_SETUP_MEMORY_TAGS
 +#define CONFIG_CMDLINE_TAG
 +#define CONFIG_INITRD_TAG
-+#define CONFIG_CMDLINE_EDITING
 +
 +/* mmc config */
 +/* Can't use MMC slot 0 if the UART is directed there */
-+#ifndef CONFIG_SUN6I
 +#if !defined CONFIG_UART0_PORT_F || CONFIG_MMC_SUNXI_SLOT != 0
 +#define CONFIG_MMC
 +#define CONFIG_GENERIC_MMC
@@ -10062,49 +9393,34 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#ifndef CONFIG_MMC_SUNXI_SLOT
 +#define CONFIG_MMC_SUNXI_SLOT		0
 +#endif
-+#define CONFIG_MMC_SUNXI_USE_DMA
 +#define CONFIG_ENV_IS_IN_MMC
 +#define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
 +#endif
-+#endif
 +
-+/*
-+ * Size of malloc() pool
-+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
-+ */
-+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
-+
-+/* Flat Device Tree (FDT/DT) support */
-+#define CONFIG_OF_LIBFDT
-+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
++/* 4MB of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
 +
 +/*
 + * Miscellaneous configurable options
 + */
-+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-+#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser    */
 +#define CONFIG_CMD_ECHO
-+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 +#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 +#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
 +#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
++#define CONFIG_SYS_GENERIC_BOARD
 +
 +/* Boot Argument Buffer Size */
 +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 +
-+/* memtest works on */
-+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (256 << 20))
-+#define CONFIG_SYS_LOAD_ADDR		0x50000000 /* default load address */
++#define CONFIG_SYS_LOAD_ADDR		0x48000000 /* default load address */
 +
 +/* standalone support */
-+#define CONFIG_STANDALONE_LOAD_ADDR	0x50000000
++#define CONFIG_STANDALONE_LOAD_ADDR	0x48000000
 +
 +#define CONFIG_SYS_HZ			1000
 +
-+/* valid baudrates */
++/* baudrate */
 +#define CONFIG_BAUDRATE			115200
-+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 +
 +/* The stack sizes are set up in start.S using the settings below */
 +#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
@@ -10149,6 +9465,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#endif
 +
 +#define CONFIG_EXTRA_ENV_SETTINGS \
++	"bootm_size=0x10000000\0" \
 +	"console=ttyS0,115200\0" \
 +	"panicarg=panic=10\0" \
 +	"extraargs=\0" \
@@ -10229,21 +9546,11 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +	  "\0" \
 +	""
 +
-+#define CONFIG_BOOTDELAY	3
 +#define CONFIG_SYS_BOOT_GET_CMDLINE
-+#define CONFIG_AUTO_COMPLETE
 +
 +#include <config_cmd_default.h>
 +
-+/* Accept zimage + raw ramdisk without mkimage headers */
-+#define CONFIG_CMD_BOOTZ
-+#define CONFIG_SUPPORT_RAW_INITRD
-+
-+#define CONFIG_DOS_PARTITION
-+#define CONFIG_CMD_FAT		/* with this we can access fat bootfs */
 +#define CONFIG_FAT_WRITE	/* enable write access */
-+#define CONFIG_CMD_EXT2		/* with this we can access ext2 bootfs */
-+#define CONFIG_CMD_EXT4		/* with this we can access ext4 bootfs */
 +
 +#define CONFIG_SPL_FRAMEWORK
 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -10270,7 +9577,7 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +
 +#else /* CONFIG_SPL */
 +
-+#define CONFIG_SPL_BSS_START_ADDR	0x50000000
++#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
 +#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */
 +
 +#define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
@@ -10290,8 +9597,10 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +
 +#endif /* CONFIG_SPL */
 +/* end of 32 KiB in sram */
-+#define LOW_LEVEL_SRAM_STACK		0x00008000
++#define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
 +#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
++#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
++#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */
 +
 +#ifdef CONFIG_SPL_OS_BOOT
 +#define CONFIG_CMD_SPL
@@ -10308,10 +9617,13 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#undef CONFIG_CMD_NFS
 +
 +/* I2C */
++#if !defined CONFIG_SUN6I && !defined CONFIG_SUN8I
 +#define CONFIG_SPL_I2C_SUPPORT
-+#define CONFIG_SYS_I2C_SPEED		400000
++#endif
++/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
 +#define CONFIG_HARD_I2C
-+#define CONFIG_SUNXI_I2C
++#define CONFIG_SYS_I2C_SUNXI
++#define CONFIG_SYS_I2C_SPEED		400000
 +#define CONFIG_SYS_I2C_SLAVE		0x7f
 +#define CONFIG_CMD_I2C
 +
@@ -10326,10 +9638,10 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#define CONFIG_CMD_GPIO
 +
 +/* PMU */
-+#if !defined CONFIG_AXP152_POWER && !defined CONFIG_NO_AXP
++#if !defined CONFIG_AXP152_POWER && !defined CONFIG_AXP221_POWER && !defined CONFIG_NO_AXP
 +#define CONFIG_AXP209_POWER
 +#endif
-+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
++#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
 +#define CONFIG_SPL_POWER_SUPPORT
 +#endif
 +
@@ -10384,43 +9696,23 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +/* Ethernet support */
 +#ifdef CONFIG_SUNXI_EMAC
 +#define CONFIG_MII			/* MII PHY management		*/
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_NET
 +#endif
 +
 +#ifdef CONFIG_SUNXI_GMAC
 +#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
 +#define CONFIG_DW_AUTONEG
 +#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
-+#define CONFIG_SYS_DCACHE_OFF		/* dw driver doesn't support dcache */
++#define CONFIG_PHY_ADDR		1
 +#define CONFIG_MII			/* MII PHY management		*/
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_NET
++#define CONFIG_PHYLIB
 +#endif
 +
 +#ifdef CONFIG_CMD_NET
-+#define CONFIG_CMD_PING
-+#define CONFIG_CMD_DHCP
 +#define CONFIG_CMD_NFS
-+#define CONFIG_CMD_SNTP
-+#define CONFIG_TIMESTAMP		/* Needed by SNTP */
 +#define CONFIG_CMD_DNS
 +#define CONFIG_NETCONSOLE
-+#define CONFIG_BOOTP_SUBNETMASK
-+#define CONFIG_BOOTP_GATEWAY
-+#define CONFIG_BOOTP_HOSTNAME
-+#define CONFIG_BOOTP_NISDOMAIN
-+#define CONFIG_BOOTP_BOOTPATH
-+#define CONFIG_BOOTP_BOOTFILESIZE
-+#define CONFIG_BOOTP_DNS
 +#define CONFIG_BOOTP_DNS2
 +#define CONFIG_BOOTP_SEND_HOSTNAME
-+#define CONFIG_BOOTP_NTPSERVER
-+#define CONFIG_BOOTP_TIMEOFFSET
-+#define CONFIG_BOOTP_MAY_FAIL
-+#define CONFIG_BOOTP_SERVERIP
-+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
-+#define CONFIG_CMD_ELF
 +#endif
 +
 +#if !defined CONFIG_ENV_IS_IN_MMC && \
@@ -10430,10 +9722,16 @@ diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include
 +#define CONFIG_ENV_IS_NOWHERE
 +#endif
 +
++#define CONFIG_MISC_INIT_R
++
++#ifndef CONFIG_SPL_BUILD
++#include <config_distro_defaults.h>
++#endif
++
 +#endif /* _SUNXI_COMMON_CONFIG_H */
-diff -ruN u-boot-2014.01-rc1/include/netdev.h u-boot-sunxi/include/netdev.h
---- u-boot-2014.01-rc1/include/netdev.h	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/include/netdev.h	2014-03-05 23:14:48.264085341 +0100
+diff -ruN u-boot-2014.04/include/netdev.h u-boot-sunxi/include/netdev.h
+--- u-boot-2014.04/include/netdev.h	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/include/netdev.h	2014-09-06 16:58:36.485953106 +0200
 @@ -79,7 +79,8 @@
  int skge_initialize(bd_t *bis);
  int smc91111_initialize(u8 dev_num, int base_addr);
@@ -10444,65 +9742,37 @@ diff -ruN u-boot-2014.01-rc1/include/netdev.h u-boot-sunxi/include/netdev.h
  int tsi108_eth_initialize(bd_t *bis);
  int uec_standard_init(bd_t *bis);
  int uli526x_initialize(bd_t *bis);
-diff -ruN u-boot-2014.01-rc1/Makefile u-boot-sunxi/Makefile
---- u-boot-2014.01-rc1/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/Makefile	2014-03-05 23:14:46.988102381 +0100
-@@ -486,6 +486,16 @@
- 			conv=notrunc 2>/dev/null
- 		cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
+diff -ruN u-boot-2014.04/Makefile u-boot-sunxi/Makefile
+--- u-boot-2014.04/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/Makefile	2014-09-06 16:58:35.065953148 +0200
+@@ -870,6 +870,13 @@
+ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
+ 	$(call if_changed,pad_cat)
  
-+# sunxi: Combined object with SPL U-Boot with sunxi header (sunxi-spl.bin)
-+# and the full-blown U-Boot attached to it
-+$(obj)u-boot-sunxi-with-spl.bin: $(obj)spl/sunxi-spl.bin $(obj)u-boot.img
-+		tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
-+			of=$(obj)spl/sunxi-spl-pad.bin 2>/dev/null
-+		dd if=$(obj)spl/sunxi-spl.bin of=$(obj)spl/sunxi-spl-pad.bin \
-+			conv=notrunc 2>/dev/null
-+		cat $(obj)spl/sunxi-spl-pad.bin $(obj)u-boot.img > $@
-+		rm $(obj)spl/sunxi-spl-pad.bin
++ifneq ($(CONFIG_SUNXI),)
++OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
++				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
++u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
++	$(call if_changed,pad_cat)
++endif
 +
  ifneq ($(CONFIG_TEGRA),)
- $(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-@@ -566,6 +576,9 @@
- $(obj)tpl/u-boot-tpl.bin:	$(SUBDIR_TOOLS) depend
- 		$(MAKE) -C spl all CONFIG_TPL_BUILD=y
+ OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
+ u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
+@@ -1081,6 +1088,9 @@
+ spl/u-boot-spl: tools prepare
+ 	$(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
  
-+$(obj)spl/sunxi-spl.bin:	$(SUBDIR_TOOLS) depend
-+		$(MAKE) -C spl all
-+
- # Explicitly make _depend in subdirs containing multiple targets to prevent
- # parallel sub-makes creating .depend files simultaneously.
- depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
-@@ -775,6 +788,8 @@
- sinclude $(obj).boards.depend
- $(obj).boards.depend:	boards.cfg
- 	@awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
-+	@awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print tolower($$7) ": " $$7 "_config; $$(MAKE)" }' $< >> $@
-+	@awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print ".PHONY: " tolower($$7) "_config"; print tolower($$7)"_config: " $$7 "_config" }' $< >> $@
- 
- #########################################################################
- #########################################################################
-@@ -798,6 +813,7 @@
- 	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
- 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
- 	       $(obj)tools/mk{$(BOARD),}spl				  \
-+	       $(obj)tools/mksunxiboot					  \
- 	       $(obj)tools/mxsboot					  \
- 	       $(obj)tools/ncb		   $(obj)tools/ubsha1		  \
- 	       $(obj)tools/kernel-doc/docproc				  \
-@@ -857,6 +873,7 @@
- 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
- 	@rm -f $(obj)dts/*.tmp
- 	@rm -f $(obj)spl/u-boot-spl{,-pad}.ais
-+	@rm -f $(obj)spl/sun?i-spl.bin
++spl/sunxi-spl.bin: spl/u-boot-spl
++	@:
++
+ tpl/u-boot-tpl.bin: tools prepare
+ 	$(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
  
- mrproper \
- distclean:	clobber unconfig
-diff -ruN u-boot-2014.01-rc1/mkconfig u-boot-sunxi/mkconfig
---- u-boot-2014.01-rc1/mkconfig	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/mkconfig	2014-03-05 23:14:48.292084967 +0100
-@@ -165,6 +165,7 @@
+diff -ruN u-boot-2014.04/mkconfig u-boot-sunxi/mkconfig
+--- u-boot-2014.04/mkconfig	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/mkconfig	2014-09-06 16:58:36.509953105 +0200
+@@ -174,6 +174,7 @@
  echo "#define CONFIG_SYS_ARCH  \"${arch}\""  >> config.h
  echo "#define CONFIG_SYS_CPU   \"${cpu}\""   >> config.h
  echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h
@@ -10510,86 +9780,69 @@ diff -ruN u-boot-2014.01-rc1/mkconfig u-boot-sunxi/mkconfig
  
  [ "${vendor}" ] && echo "#define CONFIG_SYS_VENDOR \"${vendor}\"" >> config.h
  
-diff -ruN u-boot-2014.01-rc1/snapshot.commit u-boot-sunxi/snapshot.commit
---- u-boot-2014.01-rc1/snapshot.commit	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/snapshot.commit	2014-03-05 23:14:48.300084861 +0100
+diff -ruN u-boot-2014.04/snapshot.commit u-boot-sunxi/snapshot.commit
+--- u-boot-2014.04/snapshot.commit	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/snapshot.commit	2014-09-06 16:58:36.521953105 +0200
 @@ -1 +1 @@
--d19ad726bcd5d9106f7ba9c750462fcc369f1020  Mon, 25 Nov 2013 16:49:32 -0500
+-dda0dbfc69f3d560c87f5be85f127ed862ea6721  Mon, 14 Apr 2014 15:19:24 -0400
 +$Format:%H  %cD$
-diff -ruN u-boot-2014.01-rc1/spl/Makefile u-boot-sunxi/spl/Makefile
---- u-boot-2014.01-rc1/spl/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/spl/Makefile	2014-03-05 23:14:48.300084861 +0100
-@@ -162,6 +162,12 @@
- ALL-y	+= $(obj)$(BOARD)-spl.bin
+diff -ruN u-boot-2014.04/spl/Makefile u-boot-sunxi/spl/Makefile
+--- u-boot-2014.04/spl/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/spl/Makefile	2014-09-06 16:58:36.521953105 +0200
+@@ -188,6 +188,12 @@
+ ALL-y	+= $(obj)/$(BOARD)-spl.bin
  endif
  
 +ifdef CONFIG_SUNXI
 +ifndef CONFIG_SPL_FEL
-+ALL-y	+= $(obj)sunxi-spl.bin
++ALL-y	+= $(obj)/sunxi-spl.bin
 +endif
 +endif
 +
  all:	$(ALL-y)
  
  ifdef CONFIG_SAMSUNG
-@@ -169,6 +175,12 @@
- 	$(OBJTREE)/tools/mk$(BOARD)spl $< $@
+@@ -215,6 +221,13 @@
+ LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
  endif
  
 +ifdef CONFIG_SUNXI
-+$(obj)sunxi-spl.bin: $(obj)u-boot-spl.bin
-+	$(OBJTREE)/tools/mksunxiboot \
-+		$(obj)u-boot-spl.bin $(obj)sunxi-spl.bin
++quiet_cmd_mksunxiboot = MKSUNXI $@
++cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
++$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin
++	$(call if_changed,mksunxiboot)
 +endif
 +
- $(obj)$(SPL_BIN).bin:	$(obj)$(SPL_BIN)
- 	$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
- 
-diff -ruN u-boot-2014.01-rc1/tools/.gitignore u-boot-sunxi/tools/.gitignore
---- u-boot-2014.01-rc1/tools/.gitignore	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/tools/.gitignore	2014-03-05 23:14:48.300084861 +0100
-@@ -7,6 +7,7 @@
- /mkimage
+ quiet_cmd_u-boot-spl = LD      $@
+       cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+ 		       $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
+diff -ruN u-boot-2014.04/tools/.gitignore u-boot-sunxi/tools/.gitignore
+--- u-boot-2014.04/tools/.gitignore	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/tools/.gitignore	2014-09-06 16:58:36.521953105 +0200
+@@ -9,6 +9,7 @@
+ /mkexynosspl
  /mpc86x_clk
  /mxsboot
 +/mksunxiboot
  /ncb
- /ncp
  /proftool
-diff -ruN u-boot-2014.01-rc1/tools/Makefile u-boot-sunxi/tools/Makefile
---- u-boot-2014.01-rc1/tools/Makefile	2013-11-25 22:49:32.000000000 +0100
-+++ u-boot-sunxi/tools/Makefile	2014-03-05 23:14:48.300084861 +0100
-@@ -54,6 +54,7 @@
- BIN_FILES-y += mkimage$(SFX)
- BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
- BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
-+BIN_FILES-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
- BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
- BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
- BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
-@@ -91,6 +92,7 @@
- OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
- OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
- OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
-+OBJ_FILES-$(CONFIG_SUNXI) += mksunxiboot.o
- OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
- OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
- OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
-@@ -235,6 +237,10 @@
- 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- 	$(HOSTSTRIP) $@
+ /relocate-rela
+diff -ruN u-boot-2014.04/tools/Makefile u-boot-sunxi/tools/Makefile
+--- u-boot-2014.04/tools/Makefile	2014-04-14 21:19:24.000000000 +0200
++++ u-boot-sunxi/tools/Makefile	2014-09-06 16:58:36.521953105 +0200
+@@ -120,6 +120,8 @@
+ hostprogs-$(CONFIG_MX28) += mxsboot$(SFX)
+ HOSTCFLAGS_mxsboot$(SFX).o := -pedantic
  
-+$(obj)mksunxiboot$(SFX):	$(obj)mksunxiboot.o
-+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-+	$(HOSTSTRIP) $@
-+
- $(obj)mxsboot$(SFX):	$(obj)mxsboot.o
- 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- 	$(HOSTSTRIP) $@
-diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.c
---- u-boot-2014.01-rc1/tools/mksunxiboot.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/tools/mksunxiboot.c	2014-03-05 23:14:48.312084700 +0100
-@@ -0,0 +1,163 @@
++hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
++
+ hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX)
+ hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
+ 
+diff -ruN u-boot-2014.04/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.c
+--- u-boot-2014.04/tools/mksunxiboot.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/tools/mksunxiboot.c	2014-09-06 16:58:36.529953105 +0200
+@@ -0,0 +1,140 @@
 +/*
 + * (C) Copyright 2007-2011
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
@@ -10597,22 +9850,8 @@ diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.
 + *
 + * a simple tool to generate bootable image for sunxi platform.
 + *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * SPDX-License-Identifier:	GPL-2.0+
 + */
-+
 +#include <fcntl.h>
 +#include <stdio.h>
 +#include <unistd.h>
@@ -10622,49 +9861,37 @@ diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.
 +#include <sys/types.h>
 +#include <sys/stat.h>
 +
-+typedef unsigned char u8;
-+typedef unsigned int u32;
-+
 +/* boot head definition from sun4i boot code */
 +struct boot_file_head {
-+	u32 jump_instruction;	/* one intruction jumping to real code */
-+	u8 magic[8];		/* ="eGON.BT0" or "eGON.BT1", not C-style str */
-+	u32 check_sum;		/* generated by PC */
-+	u32 length;		/* generated by PC */
-+#if 1
-+	/* We use a simplified header, only filling in what is needed by the
-+	 * boot ROM. To be compatible with Allwinner tools the larger header
-+	 * below should be used, followed by a custom header if desired. */
-+	u8 pad[12];		/* align to 32 bytes */
-+#else
-+	u32 pub_head_size;	/* the size of boot_file_head */
-+	u8 pub_head_vsn[4];	/* the version of boot_file_head */
-+	u8 file_head_vsn[4];	/* the version of boot0_file_head or
-+				   boot1_file_head */
-+	u8 Boot_vsn[4];		/* Boot version */
-+	u8 eGON_vsn[4];		/* eGON version */
-+	u8 platform[8];		/* platform information */
-+#endif
++	uint32_t b_instruction;	/* one intruction jumping to real code */
++	uint8_t magic[8];	/* ="eGON.BT0" or "eGON.BT1", not C-style str */
++	uint32_t check_sum;	/* generated by PC */
++	uint32_t length;	/* generated by PC */
++	/*
++	 * We use a simplified header, only filling in what is needed
++	 * by the boot ROM. To be compatible with Allwinner tools we
++	 * would need to implement the proper fields here instead of
++	 * padding.
++	 */
++	uint8_t pad[12];		/* align to 32 bytes */
 +};
 +
 +#define BOOT0_MAGIC                     "eGON.BT0"
 +#define STAMP_VALUE                     0x5F0A6C39
 +
 +/* check sum functon from sun4i boot code */
-+int gen_check_sum(void *boot_buf)
++int gen_check_sum(struct boot_file_head *head_p)
 +{
-+	struct boot_file_head *head_p;
-+	u32 length;
-+	u32 *buf;
-+	u32 loop;
-+	u32 i;
-+	u32 sum;
++	uint32_t length;
++	uint32_t *buf;
++	uint32_t loop;
++	uint32_t i;
++	uint32_t sum;
 +
-+	head_p = (struct boot_file_head *)boot_buf;
 +	length = head_p->length;
 +	if ((length & 0x3) != 0)	/* must 4-byte-aligned */
 +		return -1;
-+	buf = (u32 *)boot_buf;
++	buf = (uint32_t *)head_p;
 +	head_p->check_sum = STAMP_VALUE;	/* fill stamp */
 +	loop = length >> 2;
 +
@@ -10695,7 +9922,7 @@ diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.
 +{
 +	int fd_in, fd_out;
 +	struct boot_img img;
-+	unsigned file_size, load_size;
++	unsigned file_size;
 +	int count;
 +
 +	if (argc < 2) {
@@ -10707,55 +9934,58 @@ diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.
 +
 +	fd_in = open(argv[1], O_RDONLY);
 +	if (fd_in < 0) {
-+		perror("Open input file:");
++		perror("Open input file");
 +		return EXIT_FAILURE;
 +	}
 +
-+	memset((void *)img.pad, 0, BLOCK_SIZE);
++	memset(img.pad, 0, BLOCK_SIZE);
 +
 +	/* get input file size */
 +	file_size = lseek(fd_in, 0, SEEK_END);
-+	printf("File size: 0x%x\n", file_size);
 +
 +	if (file_size > SRAM_LOAD_MAX_SIZE) {
 +		fprintf(stderr, "ERROR: File too large!\n");
 +		return EXIT_FAILURE;
-+	} else
-+		load_size = ALIGN(file_size, sizeof(int));
-+	printf("Load size: 0x%x\n", load_size);
++	}
 +
 +	fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
 +	if (fd_out < 0) {
-+		perror("Open output file:");
++		perror("Open output file");
 +		return EXIT_FAILURE;
 +	}
 +
 +	/* read file to buffer to calculate checksum */
 +	lseek(fd_in, 0, SEEK_SET);
-+	count = read(fd_in, img.code, load_size);
-+	printf("Read 0x%x bytes\n", count);
++	count = read(fd_in, img.code, file_size);
++	if (count != file_size) {
++		perror("Reading input image");
++		return EXIT_FAILURE;
++	}
 +
 +	/* fill the header */
-+	img.header.jump_instruction =	/* b instruction */
++	img.header.b_instruction =	/* b instruction */
 +		0xEA000000 |	/* jump to the first instr after the header */
 +		((sizeof(struct boot_file_head) / sizeof(int) - 2)
 +		 & 0x00FFFFFF);
 +	memcpy(img.header.magic, BOOT0_MAGIC, 8);	/* no '0' termination */
 +	img.header.length =
-+		ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
-+	gen_check_sum((void *)&img);
++		ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
++	gen_check_sum(&img.header);
 +
-+	count = write(fd_out, (void *)&img, img.header.length);
-+	printf("Write 0x%x bytes\n", count);
++	count = write(fd_out, &img, img.header.length);
++	if (count != img.header.length) {
++		perror("Writing output");
++		return EXIT_FAILURE;
++	}
 +
 +	close(fd_in);
 +	close(fd_out);
 +
 +	return EXIT_SUCCESS;
 +}
-diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.README u-boot-sunxi/tools/mksunxiboot.README
---- u-boot-2014.01-rc1/tools/mksunxiboot.README	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-sunxi/tools/mksunxiboot.README	2014-03-05 23:14:48.312084700 +0100
+diff -ruN u-boot-2014.04/tools/mksunxiboot.README u-boot-sunxi/tools/mksunxiboot.README
+--- u-boot-2014.04/tools/mksunxiboot.README	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-sunxi/tools/mksunxiboot.README	2014-09-06 16:58:36.529953105 +0200
 @@ -0,0 +1,13 @@
 +This program make a arm binary file can be loaded by Allwinner A10 and related
 +chips from storage media such as nand and mmc.
diff --git a/package/boot/uboot-sunxi/patches/002-pcduino3.patch b/package/boot/uboot-sunxi/patches/002-pcduino3.patch
deleted file mode 100644
index 4580b8d..0000000
--- a/package/boot/uboot-sunxi/patches/002-pcduino3.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-diff -ruN u-boot-2014.01-rc1.old/board/sunxi/dram_pcduino3.c u-boot-2014.01-rc1/board/sunxi/dram_pcduino3.c
---- u-boot-2014.01-rc1.old/board/sunxi/dram_pcduino3.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2014.01-rc1/board/sunxi/dram_pcduino3.c	2014-04-23 20:04:00.919994615 +0200
-@@ -0,0 +1,31 @@
-+/* this file is generated, don't edit it yourself */
-+
-+#include <common.h>
-+#include <asm/arch/dram.h>
-+
-+static struct dram_para dram_para = {
-+	.clock = 480,
-+	.type = 3,
-+	.rank_num = 1,
-+	.density = 4096,
-+	.io_width = 16,
-+	.bus_width = 32,
-+	.cas = 9,
-+	.zq = 0x7a,
-+	.odt_en = 0,
-+	.size = 1024,
-+	.tpr0 = 0x42d899b7,
-+	.tpr1 = 0xa090,
-+	.tpr2 = 0x22a00,
-+	.tpr3 = 0,
-+	.tpr4 = 0,
-+	.tpr5 = 0,
-+	.emr1 = 0x4,
-+	.emr2 = 0x10,
-+	.emr3 = 0x0,
-+};
-+
-+unsigned long sunxi_dram_init(void)
-+{
-+	return dramc_init(&dram_para);
-+}
-diff -ruN u-boot-2014.01-rc1.old/board/sunxi/Makefile u-boot-2014.01-rc1/board/sunxi/Makefile
---- u-boot-2014.01-rc1.old/board/sunxi/Makefile	2014-04-12 18:51:34.000000000 +0200
-+++ u-boot-2014.01-rc1/board/sunxi/Makefile	2014-04-23 20:02:51.828839920 +0200
-@@ -73,6 +73,7 @@
- obj-$(CONFIG_MK802II)		+= dram_sun4i_408_1024_iow8.o
- obj-$(CONFIG_MK802II_A20)		+= dram_mk802ii_a20.o
- obj-$(CONFIG_PCDUINO)		+= dram_sun4i_408_1024_iow8.o
-+obj-$(CONFIG_PCDUINO3)		+= dram_pcduino3.o
- obj-$(CONFIG_PENGPOD700)	+= dram_sun4i_384_1024_iow8.o
- obj-$(CONFIG_PENGPOD1000)	+= dram_sun4i_408_1024_iow16.o
- obj-$(CONFIG_POV_PROTAB2)	+= dram_pov_protab2.o
-diff -ruN u-boot-2014.01-rc1.old/boards.cfg u-boot-2014.01-rc1/boards.cfg
---- u-boot-2014.01-rc1.old/boards.cfg	2014-04-12 18:51:34.000000000 +0200
-+++ u-boot-2014.01-rc1/boards.cfg	2014-04-23 20:02:27.897132713 +0200
-@@ -404,6 +404,7 @@
- Active  arm         armv7          sunxi       -               sunxi               mk802ii_A20                              sun7i:MK802II_A20,SPL                                                                                                                 -
- Active  arm         armv7          sunxi       -               sunxi               mk802ii                              sun4i:MK802II,SPL                                                                                                                 -
- Active  arm         armv7          sunxi       -               sunxi               pcDuino                              sun4i:PCDUINO,SPL,SUNXI_EMAC                                                                                                      -
-+Active  arm         armv7          sunxi       -               sunxi               pcDuino3                             sun7i:PCDUINO3,SPL,SUNXI_EMAC,FAST_MBUS                                                                                           -
- Active  arm         armv7          sunxi       -               sunxi               pengpod1000                          sun4i:PENGPOD1000,SPL                                                                                                             -
- Active  arm         armv7          sunxi       -               sunxi               pengpod700                           sun4i:PENGPOD700,SPL                                                                                                              -
- Active  arm         armv7          sunxi       -               sunxi               PoV_ProTab2_IPS9                     sun4i:POV_PROTAB2,SPL                                                                                                             -
diff --git a/package/boot/uboot-sunxi/patches/003-bananapi.patch b/package/boot/uboot-sunxi/patches/003-bananapi.patch
deleted file mode 100644
index fb6b2c2..0000000
--- a/package/boot/uboot-sunxi/patches/003-bananapi.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From 600e61eed037eb27df6301db9e7dab0a86cc1012 Mon Sep 17 00:00:00 2001
-From: Bo Shen <voice.shen@gmail.com>
-Date: Sat, 12 Apr 2014 07:42:11 +0800
-Subject: [PATCH] bananapi: add bananapi board support
-
-BananaPi is A20 based board. More information:
-  www.banana-pi.org
-
-The bananapi.h is original from sun7i.h + sunxi-common.h
-The dram_bananapi.c is original from dram_cubieboard2.c
-
-Signed-off-by: Bo Shen <voice.shen@gmail.com>
----
- arch/arm/cpu/armv7/sunxi/board.c |   3 +
- board/sunxi/Makefile             |   1 +
- board/sunxi/dram_bananapi.c      |  31 +++
- boards.cfg                       |   1 +
- include/configs/bananapi.h       | 432 +++++++++++++++++++++++++++++++++++++++
- 5 files changed, 468 insertions(+)
- create mode 100644 board/sunxi/dram_bananapi.c
- create mode 100644 include/configs/bananapi.h
-
-diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
-index 9b3d5a2..2df7704 100644
-diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
-index bed033b..bbe73f6 100644
---- a/board/sunxi/Makefile
-+++ b/board/sunxi/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_AUXTEK_T003)	+= dram_auxtek_t003.o
- # This is not a typo, uses the same mem settings as the a10s-olinuxino-m
- obj-$(CONFIG_AUXTEK_T004)	+= dram_a10s_olinuxino_m.o
- obj-$(CONFIG_BA10_TV_BOX)	+= dram_sun4i_384_1024_iow8.o
-+obj-$(CONFIG_BANANAPI)		+= dram_bananapi.o
- obj-$(CONFIG_COBY_MID7042)	+= dram_sun4i_408_1024_iow16.o
- obj-$(CONFIG_COBY_MID8042)	+= dram_sun4i_360_1024_iow16.o
- obj-$(CONFIG_COBY_MID9742)	+= dram_sun4i_408_1024_iow16.o
-diff --git a/board/sunxi/dram_bananapi.c b/board/sunxi/dram_bananapi.c
-new file mode 100644
-index 0000000..9e75367
---- /dev/null
-+++ b/board/sunxi/dram_bananapi.c
-@@ -0,0 +1,31 @@
-+/* this file is generated, don't edit it yourself */
-+
-+#include <common.h>
-+#include <asm/arch/dram.h>
-+
-+static struct dram_para dram_para = {
-+	.clock = 480,
-+	.type = 3,
-+	.rank_num = 1,
-+	.density = 4096,
-+	.io_width = 16,
-+	.bus_width = 32,
-+	.cas = 9,
-+	.zq = 0x7f,
-+	.odt_en = 0,
-+	.size = 1024,
-+	.tpr0 = 0x42d899b7,
-+	.tpr1 = 0xa090,
-+	.tpr2 = 0x22a00,
-+	.tpr3 = 0x0,
-+	.tpr4 = 0x1,
-+	.tpr5 = 0x0,
-+	.emr1 = 0x4,
-+	.emr2 = 0x10,
-+	.emr3 = 0x0,
-+};
-+
-+unsigned long sunxi_dram_init(void)
-+{
-+	return dramc_init(&dram_para);
-+}
-diff --git a/boards.cfg b/boards.cfg
-index f1a5d07..5073644 100644
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -381,6 +381,7 @@ Active  arm         armv7          sunxi       -               sunxi
- Active  arm         armv7          sunxi       -               sunxi               Auxtek-T003                          sun5i:AUXTEK_T003,SPL,AXP152_POWER,STATUSLED=34                                                                                   -
- Active  arm         armv7          sunxi       -               sunxi               Auxtek-T004                          sun5i:AUXTEK_T004,SPL,AXP152_POWER,STATUSLED=34                                                                                   -
- Active  arm         armv7          sunxi       -               sunxi               ba10_tv_box                          sun4i:BA10_TV_BOX,SPL,SUNXI_EMAC                                                                                                  -
-+Active  arm         armv7          sunxi       -               sunxi               bananapi                             sun7i:BANANAPI,SPL,SUNXI_GMAC,STATUSLED=248                                                                                                  -
- Active  arm         armv7          sunxi       -               sunxi               Coby_MID7042                         sun4i:COBY_MID7042,SPL                                                                                                            -
- Active  arm         armv7          sunxi       -               sunxi               Coby_MID8042                         sun4i:COBY_MID8042,SPL                                                                                                            -
- Active  arm         armv7          sunxi       -               sunxi               Coby_MID9742                         sun4i:COBY_MID9742,SPL                                                                                                            -
-diff --git a/include/configs/bananapi.h b/include/configs/bananapi.h
-new file mode 100644
-index 0000000..5e70e63
--- 
-1.9.3
-