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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 20:00:41 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 20:00:41 +0000 |
| commit | c9ae01d3c868020747b32424188f12542a69efc2 (patch) | |
| tree | aa62bcee5087d6c9f7f961f97bcd0bf3eea40197 /target/linux/ar71xx/files/include | |
| parent | 1c77ec0587c585f53a7bb8b3979a0303a1527a66 (diff) | |
| download | mtk-20170518-c9ae01d3c868020747b32424188f12542a69efc2.zip mtk-20170518-c9ae01d3c868020747b32424188f12542a69efc2.tar.gz mtk-20170518-c9ae01d3c868020747b32424188f12542a69efc2.tar.bz2 | |
ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup
SVN-Revision: 13369
Diffstat (limited to 'target/linux/ar71xx/files/include')
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h | 22 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h | 4 |
2 files changed, 18 insertions, 8 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index f68bfff..e9a69cd 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -106,13 +106,10 @@ extern enum ar71xx_soc_type ar71xx_soc; /* * PLL block */ -#define PLL_REG_CPU_PLL_CFG 0x00 -#define PLL_REG_SEC_PLL_CFG 0x04 -#define PLL_REG_CPU_CLK_CTRL 0x08 -#define PLL_REG_ETH_INT0_CLK 0x10 -#define PLL_REG_ETH_INT1_CLK 0x14 -#define PLL_REG_ETH_EXT_CLK 0x18 -#define PLL_REG_PCI_CLK 0x1c +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 #define AR71XX_PLL_DIV_SHIFT 3 #define AR71XX_PLL_DIV_MASK 0x1f @@ -123,6 +120,14 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR71XX_AHB_DIV_SHIFT 20 #define AR71XX_AHB_DIV_MASK 0x7 +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR91XX_PLL_REG_CPU_CONFIG 0x00 +#define AR91XX_PLL_REG_ETH_CONFIG 0x04 +#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 + #define AR91XX_PLL_DIV_SHIFT 0 #define AR91XX_PLL_DIV_MASK 0x3ff #define AR91XX_DDR_DIV_SHIFT 22 @@ -130,6 +135,9 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR91XX_AHB_DIV_SHIFT 19 #define AR91XX_AHB_DIV_MASK 0x1 +#define AR91XX_ETH0_PLL_SHIFT 20 +#define AR91XX_ETH1_PLL_SHIFT 22 + extern void __iomem *ar71xx_pll_base; static inline void ar71xx_pll_wr(unsigned reg, u32 val) diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h index f845c42..9d567a6 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h @@ -25,11 +25,13 @@ struct ag71xx_platform_data { int speed; int duplex; u32 reset_bit; - u32 flush_reg; u32 mii_if; u8 mac_addr[ETH_ALEN]; u8 has_gbit:1; + + void (* ddr_flush)(void); + void (* set_pll)(u32 pll); }; struct ag71xx_mdio_platform_data { |