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authorGabor Juhos <juhosg@openwrt.org>2010-09-27 14:53:43 +0000
committerGabor Juhos <juhosg@openwrt.org>2010-09-27 14:53:43 +0000
commit4ae167959bb7a6cbca9aae1b1dfdf9ef6906fcd0 (patch)
tree943c7a44f07a52ad6dde966c526093b2fd6f708e /target/linux/ar71xx/files
parente5b081335e1a976bb3cd6abe9327f9d0d0dd7ecc (diff)
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ar71xx: use different address in ap91_pci_fixup for the AR724[012] SoCs
With this change ath9k can handle the wireless chip on the TL-WR841N v7 board which is based on the AR7241 SoC. SVN-Revision: 23130
Diffstat (limited to 'target/linux/ar71xx/files')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
index e81a01a..f24d469 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
@@ -67,7 +67,20 @@ static void ap91_pci_fixup(struct pci_dev *dev)
}
/* Setup the PCI device to allow access to the internal registers */
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
+ break;
+
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
+ break;
+
+ default:
+ BUG();
+ }
+
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(dev, PCI_COMMAND, cmd);