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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-07-05 08:26:47 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-07-05 08:26:47 +0000 |
| commit | d1b237b335776be151889d5339c672d784475c3c (patch) | |
| tree | be879011f76a6bdf58b86fdac7f05b69c39e5fcb /target/linux/ar71xx/files | |
| parent | 7284cf73d69ffad645078ac5c7910913bf9757a5 (diff) | |
| download | mtk-20170518-d1b237b335776be151889d5339c672d784475c3c.zip mtk-20170518-d1b237b335776be151889d5339c672d784475c3c.tar.gz mtk-20170518-d1b237b335776be151889d5339c672d784475c3c.tar.bz2 | |
ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
Diffstat (limited to 'target/linux/ar71xx/files')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 45817e1..e6a5076 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -154,7 +154,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) if (ath79_soc == ATH79_SOC_AR9341 || ath79_soc == ATH79_SOC_AR9342 || - ath79_soc == ATH79_SOC_AR9344) + ath79_soc == ATH79_SOC_AR9344 || + ath79_soc == ATH79_SOC_QCA9558) max_id = 1; else max_id = 0; @@ -175,6 +176,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: if (id == 0) { mdio_dev = &ath79_mdio0_device; mdio_data = &ath79_mdio0_data; @@ -215,6 +217,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: if (id == 1) mdio_data->builtin_switch = 1; mdio_data->is_ar934x = 1; @@ -504,6 +507,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; pll_1000 = AR934X_PLL_VAL_1000; @@ -568,6 +572,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -616,6 +621,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -822,6 +828,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: if (id == 0) { pdata->reset_bit = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO; @@ -879,6 +886,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: if (id == 0) pdata->mii_bus_dev = &ath79_mdio0_device.dev; else |