ar71xx: add initial support for 3.2

Tested on the following boards:
  ALFA AP96
  TL-MR3220 v1
  TL-WR1043ND v1
  TL-WR2543ND v1
  TL-WR703N v1
  TL-WR741ND v1
  TL-WR741ND v4
  WNDR3700 v1
  WZR-HP-G300NH

SVN-Revision: 29868

1 files changed, 266 insertions, 0 deletions

diff --git a/target/linux/ar71xx/patches-3.2/107-MIPS-ath79-replace-ath724x-to-ar724x.patch b/target/linux/ar71xx/patches-3.2/107-MIPS-ath79-replace-ath724x-to-ar724x.patch
new file mode 100644
index 0000000..7e5df9f
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/107-MIPS-ath79-replace-ath724x-to-ar724x.patch
@@ -0,0 +1,266 @@
+From 0cbee5634678ffbd10bee9e302d013392dd8289e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 11:16:33 +0100
+Subject: [PATCH 07/35] MIPS: ath79: replace ath724x to ar724x
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Replace the 'ath724x' to 'ar724x' in function, variable and
+structure names to reflect the name of the real SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+    - refreshed due to the changes in a previous patch
+v3: - no changes
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c         |    4 +-
+ arch/mips/ath79/pci.c                  |    6 ++--
+ arch/mips/ath79/pci.h                  |   10 +++---
+ arch/mips/include/asm/mach-ath79/pci.h |    4 +-
+ arch/mips/pci/pci-ar724x.c             |   62 ++++++++++++++++----------------
+ 5 files changed, 43 insertions(+), 43 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub
+ #ifdef CONFIG_PCI
+ static struct ath9k_platform_data ubnt_xm_eeprom_data;
+ 
+-static struct ath724x_pci_data ubnt_xm_pci_data[] = {
++static struct ar724x_pci_data ubnt_xm_pci_data[] = {
+ 	{
+ 		.irq	= UBNT_XM_PCI_IRQ,
+ 		.pdata	= &ubnt_xm_eeprom_data,
+@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void)
+ 	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+ 	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
+ 
+-	ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
++	ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+ #endif /* CONFIG_PCI */
+ 
+ 	ath79_register_pci();
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -13,10 +13,10 @@
+ #include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+ 
+-static struct ath724x_pci_data *pci_data;
++static struct ar724x_pci_data *pci_data;
+ static int pci_data_size;
+ 
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
+ {
+ 	pci_data	= data;
+ 	pci_data_size	= size;
+@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev
+ int __init ath79_register_pci(void)
+ {
+ 	if (soc_is_ar724x())
+-		return ath724x_pcibios_init();
++		return ar724x_pcibios_init();
+ 
+ 	return -ENODEV;
+ }
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -8,15 +8,15 @@
+  *  by the Free Software Foundation.
+  */
+ 
+-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+-#define __ASM_MACH_ATH79_PCI_ATH724X_H
++#ifndef _ATH79_PCI_H
++#define _ATH79_PCI_H
+ 
+-struct ath724x_pci_data {
++struct ar724x_pci_data {
+ 	int irq;
+ 	void *pdata;
+ };
+ 
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
+ 
+ #ifdef CONFIG_PCI
+ int ath79_register_pci(void);
+@@ -24,4 +24,4 @@ int ath79_register_pci(void);
+ static inline int ath79_register_pci(void) { return 0; }
+ #endif
+ 
+-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
++#endif /* _ATH79_PCI_H */
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -12,9 +12,9 @@
+ #define __ASM_MACH_ATH79_PCI_H
+ 
+ #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
+-int ath724x_pcibios_init(void);
++int ar724x_pcibios_init(void);
+ #else
+-static inline int ath724x_pcibios_init(void) { return 0 };
++static inline int ar724x_pcibios_init(void) { return 0 };
+ #endif
+ 
+ #endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -14,13 +14,13 @@
+ #define reg_read(_phys)		(*(unsigned int *) KSEG1ADDR(_phys))
+ #define reg_write(_phys, _val)	((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+ 
+-#define ATH724X_PCI_DEV_BASE	0x14000000
+-#define ATH724X_PCI_MEM_BASE	0x10000000
+-#define ATH724X_PCI_MEM_SIZE	0x08000000
++#define AR724X_PCI_DEV_BASE	0x14000000
++#define AR724X_PCI_MEM_BASE	0x10000000
++#define AR724X_PCI_MEM_SIZE	0x08000000
+ 
+-static DEFINE_SPINLOCK(ath724x_pci_lock);
++static DEFINE_SPINLOCK(ar724x_pci_lock);
+ 
+-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
++static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ 			    int size, uint32_t *value)
+ {
+ 	unsigned long flags, addr, tval, mask;
+@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b
+ 	if (where & (size - 1))
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 
+-	spin_lock_irqsave(&ath724x_pci_lock, flags);
++	spin_lock_irqsave(&ar724x_pci_lock, flags);
+ 
+ 	switch (size) {
+ 	case 1:
+ 		addr = where & ~3;
+ 		mask = 0xff000000 >> ((where % 4) * 8);
+-		tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++		tval = reg_read(AR724X_PCI_DEV_BASE + addr);
+ 		tval = tval & ~mask;
+ 		*value = (tval >> ((4 - (where % 4))*8));
+ 		break;
+ 	case 2:
+ 		addr = where & ~3;
+ 		mask = 0xffff0000 >> ((where % 4)*8);
+-		tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++		tval = reg_read(AR724X_PCI_DEV_BASE + addr);
+ 		tval = tval & ~mask;
+ 		*value = (tval >> ((4 - (where % 4))*8));
+ 		break;
+ 	case 4:
+-		*value = reg_read(ATH724X_PCI_DEV_BASE + where);
++		*value = reg_read(AR724X_PCI_DEV_BASE + where);
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+ 
+-	spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+ 
+-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
++static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ 			     int size, uint32_t value)
+ {
+ 	unsigned long flags, tval, addr, mask;
+@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_
+ 	if (where & (size - 1))
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 
+-	spin_lock_irqsave(&ath724x_pci_lock, flags);
++	spin_lock_irqsave(&ar724x_pci_lock, flags);
+ 
+ 	switch (size) {
+ 	case 1:
+-		addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++		addr = (AR724X_PCI_DEV_BASE + where) & ~3;
+ 		mask = 0xff000000 >> ((where % 4)*8);
+ 		tval = reg_read(addr);
+ 		tval = tval & ~mask;
+@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_
+ 		reg_write(addr, tval);
+ 		break;
+ 	case 2:
+-		addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++		addr = (AR724X_PCI_DEV_BASE + where) & ~3;
+ 		mask = 0xffff0000 >> ((where % 4)*8);
+ 		tval = reg_read(addr);
+ 		tval = tval & ~mask;
+@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_
+ 		reg_write(addr, tval);
+ 		break;
+ 	case 4:
+-		reg_write((ATH724X_PCI_DEV_BASE + where), value);
++		reg_write((AR724X_PCI_DEV_BASE + where), value);
+ 		break;
+ 	default:
+-		spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+ 
+ 		return PCIBIOS_BAD_REGISTER_NUMBER;
+ 	}
+ 
+-	spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+ 
+-static struct pci_ops ath724x_pci_ops = {
+-	.read	= ath724x_pci_read,
+-	.write	= ath724x_pci_write,
++static struct pci_ops ar724x_pci_ops = {
++	.read	= ar724x_pci_read,
++	.write	= ar724x_pci_write,
+ };
+ 
+-static struct resource ath724x_io_resource = {
++static struct resource ar724x_io_resource = {
+ 	.name   = "PCI IO space",
+ 	.start  = 0,
+ 	.end    = 0,
+ 	.flags  = IORESOURCE_IO,
+ };
+ 
+-static struct resource ath724x_mem_resource = {
++static struct resource ar724x_mem_resource = {
+ 	.name   = "PCI memory space",
+-	.start  = ATH724X_PCI_MEM_BASE,
+-	.end    = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
++	.start  = AR724X_PCI_MEM_BASE,
++	.end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+ 	.flags  = IORESOURCE_MEM,
+ };
+ 
+-static struct pci_controller ath724x_pci_controller = {
+-	.pci_ops        = &ath724x_pci_ops,
+-	.io_resource    = &ath724x_io_resource,
+-	.mem_resource	= &ath724x_mem_resource,
++static struct pci_controller ar724x_pci_controller = {
++	.pci_ops        = &ar724x_pci_ops,
++	.io_resource    = &ar724x_io_resource,
++	.mem_resource	= &ar724x_mem_resource,
+ };
+ 
+-int __init ath724x_pcibios_init(void)
++int __init ar724x_pcibios_init(void)
+ {
+-	register_pci_controller(&ath724x_pci_controller);
++	register_pci_controller(&ar724x_pci_controller);
+ 
+ 	return PCIBIOS_SUCCESSFUL;
+ }