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| author | Felix Fietkau <nbd@openwrt.org> | 2012-02-10 11:46:37 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2012-02-10 11:46:37 +0000 |
| commit | 512df38f5cb2b9a34b71ec674a4ae9bf2e769597 (patch) | |
| tree | 2d6a03d0f15f397d65bfe642a7489be027876ad5 /target/linux/ar71xx/patches-3.2 | |
| parent | 61f48beadd602e9eb2aed609e1ba4f85a5109fb7 (diff) | |
| download | mtk-20170518-512df38f5cb2b9a34b71ec674a4ae9bf2e769597.zip mtk-20170518-512df38f5cb2b9a34b71ec674a4ae9bf2e769597.tar.gz mtk-20170518-512df38f5cb2b9a34b71ec674a4ae9bf2e769597.tar.bz2 | |
ar71xx: disable DDR flush for ethernet on AR934x, it is no longer necessary
SVN-Revision: 30409
Diffstat (limited to 'target/linux/ar71xx/patches-3.2')
| -rw-r--r-- | target/linux/ar71xx/patches-3.2/710-ar934x_no_ddr_flush.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.2/710-ar934x_no_ddr_flush.patch b/target/linux/ar71xx/patches-3.2/710-ar934x_no_ddr_flush.patch new file mode 100644 index 0000000..64ffebf --- /dev/null +++ b/target/linux/ar71xx/patches-3.2/710-ar934x_no_ddr_flush.patch @@ -0,0 +1,49 @@ +--- a/arch/mips/ath79/dev-eth.c ++++ b/arch/mips/ath79/dev-eth.c +@@ -331,6 +331,10 @@ static void ar934x_set_speed_ge1(int spe + /* TODO */ + } + ++static void ath79_ddr_no_flush(void) ++{ ++} ++ + static void ath79_ddr_flush_ge0(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); +@@ -371,16 +375,6 @@ static void ar933x_ddr_flush_ge1(void) + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); + } + +-static void ar934x_ddr_flush_ge0(void) +-{ +- ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE0); +-} +- +-static void ar934x_ddr_flush_ge1(void) +-{ +- ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE1); +-} +- + static struct resource ath79_eth0_resources[] = { + { + .name = "mac_base", +@@ -817,17 +811,16 @@ void __init ath79_register_eth(unsigned + if (id == 0) { + pdata->reset_bit = AR934X_RESET_GE0_MAC | + AR934X_RESET_GE0_MDIO; +- pdata->ddr_flush =ar934x_ddr_flush_ge0; + pdata->set_speed = ar934x_set_speed_ge0; + } else { + pdata->reset_bit = AR934X_RESET_GE1_MAC | + AR934X_RESET_GE1_MDIO; +- pdata->ddr_flush = ar934x_ddr_flush_ge1; + pdata->set_speed = ar934x_set_speed_ge1; + + pdata->switch_data = &ath79_switch_data; + } + ++ pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + |