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authorGabor Juhos <juhosg@openwrt.org>2013-03-04 11:48:15 +0000
committerGabor Juhos <juhosg@openwrt.org>2013-03-04 11:48:15 +0000
commit1d55249d7cf3811b02cd9221b5ae93df14a2ff9a (patch)
tree1e562a1548e9d6f3b10ad54792f652091e4174f1 /target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
parent64a9fe2894ab05e504cfcb824701e59d484f5f53 (diff)
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ar71xx: use backported QCA955x patches
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35878
Diffstat (limited to 'target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch')
-rw-r--r--target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch65
1 files changed, 65 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
new file mode 100644
index 0000000..15b7c75
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch
@@ -0,0 +1,65 @@
+From 281db30007b5836ce8acf5a45160fde6b176eda4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 15 Feb 2013 13:38:24 +0000
+Subject: [PATCH] MIPS: ath79: add USB controller registration code for the
+ QCA955X SoCs
+
+commit 82c46840ae6bd8a147c59cd51f636d913989324a upstream.
+
+Register platfom devices for the built-in USB
+controllers of the SoCs.
+
+Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
+Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
+Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4952/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c | 15 +++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++
+ 2 files changed, 18 insertions(+)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void
+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+
++static void __init qca955x_usb_setup(void)
++{
++ ath79_usb_register("ehci-platform", 0,
++ QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
++ ATH79_IP3_IRQ(0),
++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++
++ ath79_usb_register("ehci-platform", 1,
++ QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
++ ATH79_IP3_IRQ(1),
++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ void __init ath79_register_usb(void)
+ {
+ if (soc_is_ar71xx())
+@@ -222,6 +235,8 @@ void __init ath79_register_usb(void)
+ ar933x_usb_setup();
+ else if (soc_is_ar934x())
+ ar934x_usb_setup();
++ else if (soc_is_qca955x())
++ qca955x_usb_setup();
+ else
+ BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -109,6 +109,9 @@
+
+ #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE 0x20000
++#define QCA955X_EHCI0_BASE 0x1b000000
++#define QCA955X_EHCI1_BASE 0x1b400000
++#define QCA955X_EHCI_SIZE 0x1000
+
+ /*
+ * DDR_CTRL block