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authorGabor Juhos <juhosg@openwrt.org>2013-02-21 17:47:15 +0000
committerGabor Juhos <juhosg@openwrt.org>2013-02-21 17:47:15 +0000
commitcf2324fd6b6752ce511b612fc192ab9f0b6a32cb (patch)
tree4f94e8ab5c7b998cb84115489594f670957f3d4b /target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
parent9cc3a60b5a6988759532b63a6fb513484b8ec9f9 (diff)
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ar71xx: add support for 3.8
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35728
Diffstat (limited to 'target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch')
-rw-r--r--target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch94
1 files changed, 94 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch b/target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
new file mode 100644
index 0000000..4861db0
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
@@ -0,0 +1,94 @@
+From c3a8b5fa196cedc4b940c1e5ec482dd875aa3180 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 13:38:06 +0200
+Subject: [PATCH 06/34] MIPS: ath79: move global PCI defines into a common header
+
+The constants will be used by a subsequent patch.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 ++++++++++++++++++++++++
+ arch/mips/pci/pci-ar71xx.c | 16 ----------------
+ arch/mips/pci/pci-ar724x.c | 8 --------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -41,11 +41,35 @@
+ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE 0x100
+
++#define AR71XX_PCI_MEM_BASE 0x10000000
++#define AR71XX_PCI_MEM_SIZE 0x07000000
++
++#define AR71XX_PCI_WIN0_OFFS 0x10000000
++#define AR71XX_PCI_WIN1_OFFS 0x11000000
++#define AR71XX_PCI_WIN2_OFFS 0x12000000
++#define AR71XX_PCI_WIN3_OFFS 0x13000000
++#define AR71XX_PCI_WIN4_OFFS 0x14000000
++#define AR71XX_PCI_WIN5_OFFS 0x15000000
++#define AR71XX_PCI_WIN6_OFFS 0x16000000
++#define AR71XX_PCI_WIN7_OFFS 0x07000000
++
++#define AR71XX_PCI_CFG_BASE \
++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE 0x100
++
+ #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE 0x100
+ #define AR7240_OHCI_BASE 0x1b000000
+ #define AR7240_OHCI_SIZE 0x1000
+
++#define AR724X_PCI_MEM_BASE 0x10000000
++#define AR724X_PCI_MEM_SIZE 0x04000000
++
++#define AR724X_PCI_CFG_BASE 0x14000000
++#define AR724X_PCI_CFG_SIZE 0x1000
++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE 0x100
++
+ #define AR724X_EHCI_BASE 0x1b000000
+ #define AR724X_EHCI_SIZE 0x1000
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -25,22 +25,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+
+-#define AR71XX_PCI_MEM_BASE 0x10000000
+-#define AR71XX_PCI_MEM_SIZE 0x07000000
+-
+-#define AR71XX_PCI_WIN0_OFFS 0x10000000
+-#define AR71XX_PCI_WIN1_OFFS 0x11000000
+-#define AR71XX_PCI_WIN2_OFFS 0x12000000
+-#define AR71XX_PCI_WIN3_OFFS 0x13000000
+-#define AR71XX_PCI_WIN4_OFFS 0x14000000
+-#define AR71XX_PCI_WIN5_OFFS 0x15000000
+-#define AR71XX_PCI_WIN6_OFFS 0x16000000
+-#define AR71XX_PCI_WIN7_OFFS 0x07000000
+-
+-#define AR71XX_PCI_CFG_BASE \
+- (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+-#define AR71XX_PCI_CFG_SIZE 0x100
+-
+ #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA 0x04
+ #define AR71XX_PCI_REG_CRP_RDDATA 0x08
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -17,14 +17,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+
+-#define AR724X_PCI_CFG_BASE 0x14000000
+-#define AR724X_PCI_CFG_SIZE 0x1000
+-#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
+-#define AR724X_PCI_CTRL_SIZE 0x100
+-
+-#define AR724X_PCI_MEM_BASE 0x10000000
+-#define AR724X_PCI_MEM_SIZE 0x04000000
+-
+ #define AR724X_PCI_REG_RESET 0x18
+ #define AR724X_PCI_REG_INT_STATUS 0x4c
+ #define AR724X_PCI_REG_INT_MASK 0x50