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authorGabor Juhos <juhosg@openwrt.org>2012-03-13 17:29:31 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-03-13 17:29:31 +0000
commit17d3131d3c298d1f0061e371418014d5e92f5a31 (patch)
tree8090af5607bece74861efbca4592403b287b3c88 /target/linux/ar71xx
parent07486c4d963f33b61a64f30939f04f4f2074e9ca (diff)
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ar71xx: fix a typo in ar71xx_regs.h
SVN-Revision: 30921
Diffstat (limited to 'target/linux/ar71xx')
-rw-r--r--target/linux/ar71xx/patches-3.2/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h11
-rw-r--r--target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h11
2 files changed, 22 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.2/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h b/target/linux/ar71xx/patches-3.2/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h
new file mode 100644
index 0000000..9069edd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h
@@ -0,0 +1,11 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -313,7 +313,7 @@
+ #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+ #define AR934X_RESET_HOST_DMA_INT BIT(10)
+ #define AR934X_RESET_GE0_MAC BIT(9)
+-#define AR934X_RESET_ETH_SIWTCH BIT(8)
++#define AR934X_RESET_ETH_SWITCH BIT(8)
+ #define AR934X_RESET_PCIE_PHY BIT(7)
+ #define AR934X_RESET_PCIE BIT(6)
+ #define AR934X_RESET_USB_HOST BIT(5)
diff --git a/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h b/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h
new file mode 100644
index 0000000..9069edd
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h
@@ -0,0 +1,11 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -313,7 +313,7 @@
+ #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+ #define AR934X_RESET_HOST_DMA_INT BIT(10)
+ #define AR934X_RESET_GE0_MAC BIT(9)
+-#define AR934X_RESET_ETH_SIWTCH BIT(8)
++#define AR934X_RESET_ETH_SWITCH BIT(8)
+ #define AR934X_RESET_PCIE_PHY BIT(7)
+ #define AR934X_RESET_PCIE BIT(6)
+ #define AR934X_RESET_USB_HOST BIT(5)