diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2012-09-10 14:38:01 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-09-10 14:38:01 +0000 |
| commit | 4ee5b528defa065df78e0fd0ed5c8de1a11c3047 (patch) | |
| tree | 7046581ca75c34c560381a7a25c5f133fd207092 /target/linux/ar71xx | |
| parent | 2e0e38ad69c719afd06858daba2f46724c989e1f (diff) | |
| download | mtk-20170518-4ee5b528defa065df78e0fd0ed5c8de1a11c3047.zip mtk-20170518-4ee5b528defa065df78e0fd0ed5c8de1a11c3047.tar.gz mtk-20170518-4ee5b528defa065df78e0fd0ed5c8de1a11c3047.tar.bz2 | |
ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x
SVN-Revision: 33362
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch index 289ec6d..bb0924c 100644 --- a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch +++ b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch @@ -38,7 +38,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> + QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ath79_ref_clk.rate / ref_div; -+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll /= (1 << out_div); + + pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); @@ -52,7 +52,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> + QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ath79_ref_clk.rate / ref_div; -+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); |