diff options
author | Felix Fietkau <nbd@openwrt.org> | 2010-09-28 22:55:14 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2010-09-28 22:55:14 +0000 |
commit | 8511c6b16c6c7df587bc2f7f58e935c12918e51c (patch) | |
tree | 70120ea85a750c4713355706b375633a825463d8 /target/linux/ar71xx | |
parent | 8314ce02cc405e7625201e866675bc2e10820770 (diff) | |
download | mtk-20170518-8511c6b16c6c7df587bc2f7f58e935c12918e51c.zip mtk-20170518-8511c6b16c6c7df587bc2f7f58e935c12918e51c.tar.gz mtk-20170518-8511c6b16c6c7df587bc2f7f58e935c12918e51c.tar.bz2 |
AP96: Fix LAN/WAN setup
LAN (eth0) is behind a switch and the fixed speed/duplex was
supposed to be for it, not WAN (eth1).
Signed-off-by: Jouni Malinen <jouni.malinen@atheros.com>
SVN-Revision: 23147
Diffstat (limited to 'target/linux/ar71xx')
-rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c index 6a7b6ff..c5b2d3a 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c @@ -134,22 +134,26 @@ static struct gpio_button ap96_gpio_buttons[] __initdata = { } }; +#define AP96_WAN_PHYMASK 0x10 +#define AP96_LAN_PHYMASK 0x0f + static void __init ap96_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - ar71xx_add_device_mdio(0xfffffffe); + ar71xx_add_device_mdio(~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art, 0); ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; - ar71xx_eth0_data.phy_mask = 0x1; + ar71xx_eth0_data.phy_mask = AP96_LAN_PHYMASK; + ar71xx_eth0_data.speed = SPEED_1000; + ar71xx_eth0_data.duplex = DUPLEX_FULL; ar71xx_add_device_eth(0); ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art, 1); ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; - ar71xx_eth1_data.speed = SPEED_1000; - ar71xx_eth1_data.duplex = DUPLEX_FULL; + ar71xx_eth1_data.phy_mask = AP96_WAN_PHYMASK; ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; |