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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-12-09 08:11:49 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-12-09 08:11:49 +0000 |
| commit | a2cda74350e3fe7d984af8217f5b949422b62673 (patch) | |
| tree | 8323a631ec4b53c1e4e99f78e0d50b4382e55a0e /target/linux/ar71xx | |
| parent | 0de40f55dc5e818f91e2266790ca410502e9cee7 (diff) | |
| download | mtk-20170518-a2cda74350e3fe7d984af8217f5b949422b62673.zip mtk-20170518-a2cda74350e3fe7d984af8217f5b949422b62673.tar.gz mtk-20170518-a2cda74350e3fe7d984af8217f5b949422b62673.tar.bz2 | |
preliminary 2.6.28 support
SVN-Revision: 13559
Diffstat (limited to 'target/linux/ar71xx')
29 files changed, 1595 insertions, 0 deletions
diff --git a/target/linux/ar71xx/config-2.6.28 b/target/linux/ar71xx/config-2.6.28 new file mode 100644 index 0000000..b6133a9 --- /dev/null +++ b/target/linux/ar71xx/config-2.6.28 @@ -0,0 +1,265 @@ +CONFIG_32BIT=y +# CONFIG_64BIT is not set +# CONFIG_8139TOO is not set +CONFIG_ADM6996_PHY=y +CONFIG_AG71XX=y +# CONFIG_AR71XX_EARLY_SERIAL is not set +CONFIG_AR71XX_MACH_AP83=y +CONFIG_AR71XX_MACH_AW_NR580=y +CONFIG_AR71XX_MACH_GENERIC=y +CONFIG_AR71XX_MACH_RB_4XX=y +CONFIG_AR71XX_MACH_TEW_632BRP=y +CONFIG_AR71XX_MACH_WP543=y +CONFIG_AR71XX_WDT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ATHEROS_AR71XX=y +CONFIG_BASE_SMALL=0 +# CONFIG_BCM47XX is not set +CONFIG_BITREVERSE=y +# CONFIG_BROADCOM_PHY is not set +CONFIG_CEVT_R4K=y +CONFIG_CLASSIC_RCU=y +CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit" +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR2=y +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_VR41XX is not set +CONFIG_CRYPTO_RNG=m +CONFIG_CSRC_R4K=y +CONFIG_DEVPORT=y +# CONFIG_DM9000 is not set +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +# CONFIG_FIXED_PHY is not set +# CONFIG_FREEZER is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GPIOLIB=y +# CONFIG_GPIO_MAX7301 is not set +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_AOUT is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_IDE=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=m +# CONFIG_I2C is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +CONFIG_ICPLUS_PHY=y +# CONFIG_IDE is not set +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_SOURCE="../../root" +CONFIG_IRQ_CPU=y +# CONFIG_ISDN is not set +CONFIG_KMOD=y +# CONFIG_LEDS_ALIX is not set +CONFIG_LEDS_GPIO=m +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_M25PXX_USE_FAST_READ is not set +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_EMMA is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_TMIO is not set +CONFIG_MICREL_PHY=y +# CONFIG_MIKROTIK_RB532 is not set +CONFIG_MIPS=y +# CONFIG_MIPS_COBALT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MACHINE=y +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_CONCAT=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_M25P80=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_RB4XX=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_ONENAND is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_PARTS_READONLY=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +CONFIG_MYLOADER=y +# CONFIG_NATSEMI is not set +CONFIG_NF_CT_ACCT=y +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NO_IOPORT is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PAGE_SIZE_16KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_PHYLIB=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_R6040 is not set +# CONFIG_REALTEK_PHY is not set +CONFIG_RFKILL_LEDS=y +CONFIG_RTC_LIB=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SMSC_PHY is not set +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPI=y +CONFIG_SPI_AR71XX=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_MASTER=y +# CONFIG_SPI_SPIDEV is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_STAGING is not set +CONFIG_STAGING_EXCLUDE_BUILD=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +# CONFIG_TC35815 is not set +CONFIG_TICK_ONESHOT=y +CONFIG_TRAD_SIGNALS=y +CONFIG_USB=m +CONFIG_USB_EHCI_AR71XX=y +CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_NET_SMSC95XX is not set +CONFIG_USB_OHCI_AR71XX=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_SEVSEG is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TMC is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIA_RHINE is not set +CONFIG_VIDEO_MEDIA=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_COMMON=m +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h new file mode 100644 index 0000000..8a99d56 --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h @@ -0,0 +1,34 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_FW_MYLOADER_H +#define _ASM_MIPS_FW_MYLOADER_H + +#include <linux/myloader.h> + +struct myloader_info { + uint32_t vid; + uint32_t did; + uint32_t svid; + uint32_t sdid; + uint8_t macs[MYLO_ETHADDR_COUNT][6]; +}; + +#ifdef CONFIG_MYLOADER +extern struct myloader_info *myloader_get_info(void) __init; +#else +static inline struct myloader_info *myloader_get_info(void) +{ + return NULL; +} +#endif /* CONFIG_MYLOADER */ + +#endif /* _ASM_MIPS_FW_MYLOADER_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h new file mode 100644 index 0000000..42db7cc --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -0,0 +1,424 @@ +/* + * Atheros AR71xx SoC specific definitions + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_H +#define __ASM_MACH_AR71XX_H + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/bitops.h> + +#ifndef __ASSEMBLER__ + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x08000000 +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x01000000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x01000000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x01000000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x01000000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x10000 +#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x10000 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x10000 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x10000 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x10000 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x10000 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x10000 +#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) +#define AR71XX_SLIC_SIZE 0x10000 +#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) +#define AR71XX_DMA_SIZE 0x10000 +#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) +#define AR71XX_STEREO_SIZE 0x10000 + +#define AR71XX_CPU_IRQ_BASE 0 +#define AR71XX_MISC_IRQ_BASE 8 +#define AR71XX_MISC_IRQ_COUNT 8 +#define AR71XX_GPIO_IRQ_BASE 16 +#define AR71XX_GPIO_IRQ_COUNT 16 +#define AR71XX_PCI_IRQ_BASE 32 +#define AR71XX_PCI_IRQ_COUNT 4 + +#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2) +#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) +#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) +#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) +#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) +#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) + +#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) +#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) +#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) +#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) +#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) +#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) +#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) +#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) + +#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) + +#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) +#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) +#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) +#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3) + +extern u32 ar71xx_ahb_freq; +extern u32 ar71xx_cpu_freq; +extern u32 ar71xx_ddr_freq; + +enum ar71xx_soc_type { + AR71XX_SOC_UNKNOWN, + AR71XX_SOC_AR7130, + AR71XX_SOC_AR7141, + AR71XX_SOC_AR7161, + AR71XX_SOC_AR9130, + AR71XX_SOC_AR9132 +}; + +extern enum ar71xx_soc_type ar71xx_soc; + +extern unsigned long ar71xx_mach_type; + +#define AR71XX_MACH_GENERIC 0 +#define AR71XX_MACH_WP543 1 /* Compex WP543 */ +#define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */ +#define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */ +#define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */ +#define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */ +#define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */ +#define AR71XX_MACH_AP83 7 /* Atheros AP83 */ +#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */ + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR91XX_PLL_REG_CPU_CONFIG 0x00 +#define AR91XX_PLL_REG_ETH_CONFIG 0x04 +#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR91XX_PLL_DIV_SHIFT 0 +#define AR91XX_PLL_DIV_MASK 0x3ff +#define AR91XX_DDR_DIV_SHIFT 22 +#define AR91XX_DDR_DIV_MASK 0x3 +#define AR91XX_AHB_DIV_SHIFT 19 +#define AR91XX_AHB_DIV_MASK 0x1 + +#define AR91XX_ETH0_PLL_SHIFT 20 +#define AR91XX_ETH1_PLL_SHIFT 22 + +extern void __iomem *ar71xx_pll_base; + +static inline void ar71xx_pll_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ar71xx_pll_base + reg); +} + +static inline u32 ar71xx_pll_rr(unsigned reg) +{ + return __raw_readl(ar71xx_pll_base + reg); +} + +/* + * USB_CONFIG block + */ +#define USB_CTRL_REG_FLADJ 0x00 +#define USB_CTRL_REG_CONFIG 0x04 + +extern void __iomem *ar71xx_usb_ctrl_base; + +static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ar71xx_usb_ctrl_base + reg); +} + +static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) +{ + return __raw_readl(ar71xx_usb_ctrl_base + reg); +} + +extern void ar71xx_add_device_usb(void) __init; + +/* + * GPIO block + */ +#define GPIO_REG_OE 0x00 +#define GPIO_REG_IN 0x04 +#define GPIO_REG_OUT 0x08 +#define GPIO_REG_SET 0x0c +#define GPIO_REG_CLEAR 0x10 +#define GPIO_REG_INT_MODE 0x14 +#define GPIO_REG_INT_TYPE 0x18 +#define GPIO_REG_INT_POLARITY 0x1c +#define GPIO_REG_INT_PENDING 0x20 +#define GPIO_REG_INT_ENABLE 0x24 +#define GPIO_REG_FUNC 0x28 + +#define GPIO_FUNC_STEREO_EN BIT(17) +#define GPIO_FUNC_SLIC_EN BIT(16) +#define GPIO_FUNC_SPI_CS1_EN BIT(15) +#define GPIO_FUNC_SPI_CS0_EN BIT(14) +#define GPIO_FUNC_SPI_EN BIT(13) +#define GPIO_FUNC_UART_EN BIT(8) +#define GPIO_FUNC_USB_OC_EN BIT(4) +#define GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR71XX_GPIO_COUNT 16 +#define AR91XX_GPIO_COUNT 22 + +extern void __iomem *ar71xx_gpio_base; + +static inline void ar71xx_gpio_wr(unsigned reg, u32 value) +{ + __raw_writel(value, ar71xx_gpio_base + reg); +} + +static inline u32 ar71xx_gpio_rr(unsigned reg) +{ + return __raw_readl(ar71xx_gpio_base + reg); +} + +extern void ar71xx_gpio_init(void) __init; +extern void ar71xx_gpio_function_enable(u32 mask); +extern void ar71xx_gpio_function_disable(u32 mask); + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR91XX_DDR_REG_FLUSH_GE0 0x7c +#define AR91XX_DDR_REG_FLUSH_GE1 0x80 +#define AR91XX_DDR_REG_FLUSH_USB 0x84 +#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 + +#define PCI_WIN0_OFFS 0x10000000 +#define PCI_WIN1_OFFS 0x11000000 +#define PCI_WIN2_OFFS 0x12000000 +#define PCI_WIN3_OFFS 0x13000000 +#define PCI_WIN4_OFFS 0x14000000 +#define PCI_WIN5_OFFS 0x15000000 +#define PCI_WIN6_OFFS 0x16000000 +#define PCI_WIN7_OFFS 0x07000000 + +extern void __iomem *ar71xx_ddr_base; + +static inline void ar71xx_ddr_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ar71xx_ddr_base + reg); +} + +static inline u32 ar71xx_ddr_rr(unsigned reg) +{ + return __raw_readl(ar71xx_ddr_base + reg); +} + +extern void ar71xx_ddr_flush(u32 reg); + +/* + * PCI block + */ +#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define PCI_REG_CRP_AD_CBE 0x00 +#define PCI_REG_CRP_WRDATA 0x04 +#define PCI_REG_CRP_RDDATA 0x08 +#define PCI_REG_CFG_AD 0x0c +#define PCI_REG_CFG_CBE 0x10 +#define PCI_REG_CFG_WRDATA 0x14 +#define PCI_REG_CFG_RDDATA 0x18 +#define PCI_REG_PCI_ERR 0x1c +#define PCI_REG_PCI_ERR_ADDR 0x20 +#define PCI_REG_AHB_ERR 0x24 +#define PCI_REG_AHB_ERR_ADDR 0x28 + +#define PCI_CRP_CMD_WRITE 0x00010000 +#define PCI_CRP_CMD_READ 0x00000000 +#define PCI_CFG_CMD_READ 0x0000000a +#define PCI_CFG_CMD_WRITE 0x0000000b + +#define PCI_IDSEL_ADL_START 17 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR91XX_RESET_REG_RESET_MODULE 0x1c +#define AR91XX_RESET_REG_PERF_CTRL 0x20 +#define AR91XX_RESET_REG_PERFC0 0x24 +#define AR91XX_RESET_REG_PERFC1 0x28 + +#define WDOG_CTRL_LAST_RESET BIT(31) +#define WDOG_CTRL_ACTION_MASK 3 +#define WDOG_CTRL_ACTION_NONE 0 /* no action */ +#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ +#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ +#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ + +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define PCI_INT_CORE BIT(4) +#define PCI_INT_DEV2 BIT(2) +#define PCI_INT_DEV1 BIT(1) +#define PCI_INT_DEV0 BIT(0) + +#define RESET_MODULE_EXTERNAL BIT(28) +#define RESET_MODULE_FULL_CHIP BIT(24) +#define RESET_MODULE_CPU_NMI BIT(21) +#define RESET_MODULE_CPU_COLD BIT(20) +#define RESET_MODULE_DMA BIT(19) +#define RESET_MODULE_SLIC BIT(18) +#define RESET_MODULE_STEREO BIT(17) +#define RESET_MODULE_DDR BIT(16) +#define RESET_MODULE_GE1_MAC BIT(13) +#define RESET_MODULE_GE1_PHY BIT(12) +#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) +#define RESET_MODULE_GE0_MAC BIT(9) +#define RESET_MODULE_GE0_PHY BIT(8) +#define RESET_MODULE_USB_OHCI_DLL BIT(6) +#define RESET_MODULE_USB_HOST BIT(5) +#define RESET_MODULE_USB_PHY BIT(4) +#define RESET_MODULE_PCI_BUS BIT(1) +#define RESET_MODULE_PCI_CORE BIT(0) + +#define REV_ID_MASK 0xff +#define REV_ID_CHIP_MASK 0xf3 +#define REV_ID_CHIP_AR7130 0xa0 +#define REV_ID_CHIP_AR7141 0xa1 +#define REV_ID_CHIP_AR7161 0xa2 +#define REV_ID_CHIP_AR9130 0xb0 +#define REV_ID_CHIP_AR9132 0xb1 + +#define REV_ID_REVISION_MASK 0x3 +#define REV_ID_REVISION_SHIFT 2 + +extern void __iomem *ar71xx_reset_base; + +static inline void ar71xx_reset_wr(unsigned reg, u32 val) +{ + __raw_writel(val, ar71xx_reset_base + reg); +} + +static inline u32 ar71xx_reset_rr(unsigned reg) +{ + return __raw_readl(ar71xx_reset_base + reg); +} + +extern void ar71xx_device_stop(u32 mask); +extern void ar71xx_device_start(u32 mask); + +/* + * SPI block + */ +#define SPI_REG_FS 0x00 /* Function Select */ +#define SPI_REG_CTRL 0x04 /* SPI Control */ +#define SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define SPI_CTRL_DIV_MASK 0x3f + +#define SPI_IOC_DO BIT(0) /* Data Out pin */ +#define SPI_IOC_CLK BIT(8) /* CLK pin */ +#define SPI_IOC_CS(n) BIT(16 + (n)) +#define SPI_IOC_CS0 SPI_IOC_CS(0) +#define SPI_IOC_CS1 SPI_IOC_CS(1) +#define SPI_IOC_CS2 SPI_IOC_CS(2) +#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) + +/* + * MII_CTRL block + */ +#define MII_REG_MII0_CTRL 0x00 +#define MII_REG_MII1_CTRL 0x04 + +#define MII0_CTRL_IF_GMII 0 +#define MII0_CTRL_IF_MII 1 +#define MII0_CTRL_IF_RGMII 2 +#define MII0_CTRL_IF_RMII 3 + +#define MII1_CTRL_IF_RGMII 0 +#define MII1_CTRL_IF_RMII 1 + +#endif /* __ASSEMBLER__ */ + +#endif /* __ASM_MACH_AR71XX_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h new file mode 100644 index 0000000..d3560e5 --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Atheros AR71xx specific CPU feature overrides + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h new file mode 100644 index 0000000..6354d68 --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h @@ -0,0 +1,53 @@ +/* + * Atheros AR71xx GPIO API definitions + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __ASM_MACH_AR71XX_GPIO_H +#define __ASM_MACH_AR71XX_GPIO_H + +#define ARCH_NR_GPIOS 64 +#include <asm-generic/gpio.h> + +#include <asm/mach-ar71xx/ar71xx.h> + +extern unsigned long ar71xx_gpio_count; +extern void __ar71xx_gpio_set_value(unsigned gpio, int value); +extern int __ar71xx_gpio_get_value(unsigned gpio); + +static inline int gpio_to_irq(unsigned gpio) +{ + return AR71XX_GPIO_IRQ(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - AR71XX_GPIO_IRQ_BASE; +} + +static inline int gpio_get_value(unsigned gpio) +{ + if (gpio < ar71xx_gpio_count) + return __ar71xx_gpio_get_value(gpio); + + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (gpio < ar71xx_gpio_count) + __ar71xx_gpio_set_value(gpio, value); + else + __gpio_set_value(gpio, value); +} + +#define gpio_cansleep __gpio_cansleep + +#endif /* __ASM_MACH_AR71XX_GPIO_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h new file mode 100644 index 0000000..fe6cfeb --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef __ASM_MACH_AR71XX_IRQ_H +#define __ASM_MACH_AR71XX_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 36 + +#include_next <irq.h> + +#endif /* __ASM_MACH_AR71XX_IRQ_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h new file mode 100644 index 0000000..126d5b3 --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h + * Copyright (C) 2003, 2004 Ralf Baechle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H +#define __ASM_MACH_AR71XX_MANGLE_PORT_H + +#define __swizzle_addr_b(port) ((port) ^ 3) +#define __swizzle_addr_w(port) ((port) ^ 2) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +#if defined(CONFIG_SWAP_IO_SPACE) + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) + +#else + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le64(x) + +#endif + +#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h new file mode 100644 index 0000000..9cf536d --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h @@ -0,0 +1,28 @@ +/* + * Atheros AR71xx SoC specific PCI definitions + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_PCI_H +#define __ASM_MACH_AR71XX_PCI_H + +struct ar71xx_pci_irq { + int irq; + u8 slot; + u8 pin; +}; + +extern int (*ar71xx_pci_be_handler)(int is_fixup); +extern int (*ar71xx_pci_bios_init)(unsigned nr_irqs, + struct ar71xx_pci_irq *map) __initdata; + +extern int ar71xx_pci_init(unsigned nr_irqs, + struct ar71xx_pci_irq *map) __init; + +#endif /* __ASM_MACH_AR71XX_PCI_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h new file mode 100644 index 0000000..750418a --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h @@ -0,0 +1,77 @@ +/* + * Atheros AR71xx SoC specific platform definitions + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_PLATFORM_H +#define __ASM_MACH_AR71XX_PLATFORM_H + +#include <linux/if_ether.h> +#include <linux/skbuff.h> +#include <linux/phy.h> +#include <linux/spi/spi.h> +#include <linux/leds.h> +#include <linux/gpio_buttons.h> + +struct ag71xx_platform_data { + phy_interface_t phy_if_mode; + u32 phy_mask; + int speed; + int duplex; + u32 reset_bit; + u32 mii_if; + u8 mac_addr[ETH_ALEN]; + + u8 has_gbit:1; + u8 is_ar91xx:1; + + void (* ddr_flush)(void); + void (* set_pll)(u32 pll); +}; + +struct ag71xx_mdio_platform_data { + u32 phy_mask; +}; + +struct ar71xx_ehci_platform_data { + u8 is_ar91xx; +}; + +struct ar71xx_spi_platform_data { + unsigned bus_num; + unsigned num_chipselect; + u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); +}; + +#define AR71XX_SPI_CS_INACTIVE 0 +#define AR71XX_SPI_CS_ACTIVE 1 + +extern void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, + struct spi_board_info const *info, + unsigned n) __init; + +extern void ar71xx_set_mac_base(unsigned char *mac) __init; +extern void ar71xx_parse_mac_addr(char *mac_str) __init; + +extern struct ag71xx_platform_data ar71xx_eth0_data; +extern struct ag71xx_platform_data ar71xx_eth1_data; +extern void ar71xx_add_device_eth(unsigned int id) __init; + +extern void ar71xx_add_device_mdio(u32 phy_mask) __init; + +extern void ar71xx_add_device_leds_gpio(int id, + unsigned num_leds, + struct gpio_led *leds) __init; + +extern void ar71xx_add_device_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_button *buttons) __init; + +#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h new file mode 100644 index 0000000..1ca6ffd --- /dev/null +++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MACH_AR71XX_WAR_H +#define __ASM_MACH_AR71XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_AR71XX_WAR_H */ diff --git a/target/linux/ar71xx/patches-2.6.28/001-ar71xx_core.patch b/target/linux/ar71xx/patches-2.6.28/001-ar71xx_core.patch new file mode 100644 index 0000000..3b01aea --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/001-ar71xx_core.patch @@ -0,0 +1,50 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -586,6 +586,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/ + core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ + core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ + ++# ++# Atheros AR71xx ++# ++core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ ++cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx ++load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 ++ + # temporary until string.h is fixed + cflags-y += -ffreestanding + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -22,6 +22,23 @@ choice + config MACH_ALCHEMY + bool "Alchemy processor based machines" + ++config ATHEROS_AR71XX ++ bool "Atheros AR71xx based boards" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select HW_HAS_PCI ++ select IRQ_CPU ++ select ARCH_REQUIRE_GPIOLIB ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_HAS_EARLY_PRINTK ++ select MIPS_MACHINE ++ help ++ Support for Atheros AR71xx based boards. ++ + config BASLER_EXCITE + bool "Basler eXcite smart camera" + select CEVT_R4K +@@ -598,6 +615,7 @@ config WR_PPMC + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ar71xx/Kconfig" + source "arch/mips/basler/excite/Kconfig" + source "arch/mips/emma/Kconfig" + source "arch/mips/jazz/Kconfig" diff --git a/target/linux/ar71xx/patches-2.6.28/002-ar71xx_pci.patch b/target/linux/ar71xx/patches-2.6.28/002-ar71xx_pci.patch new file mode 100644 index 0000000..8e022af --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/002-ar71xx_pci.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o + obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o + obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o + obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o ++obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o + + # + # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-2.6.28/003-ar71xx_usb_host.patch b/target/linux/ar71xx/patches-2.6.28/003-ar71xx_usb_host.patch new file mode 100644 index 0000000..8392f48 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/003-ar71xx_usb_host.patch @@ -0,0 +1,56 @@ +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -81,6 +81,12 @@ config USB_EHCI_BIG_ENDIAN_DESC + depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX) + default y + ++config USB_EHCI_AR71XX ++ bool "USB EHCI support for AR71xx" ++ depends on USB_EHCI_HCD && ATHEROS_AR71XX ++ help ++ Support for Atheros AR71xx built-in EHCI controller ++ + config USB_EHCI_FSL + bool "Support for Freescale on-chip EHCI USB controller" + depends on USB_EHCI_HCD && FSL_SOC +@@ -140,6 +146,12 @@ config USB_OHCI_HCD + To compile this driver as a module, choose M here: the + module will be called ohci-hcd. + ++config USB_OHCI_AR71XX ++ bool "USB OHCI support for Atheros AR71xx" ++ depends on USB_OHCI_HCD && ATHEROS_AR71XX ++ help ++ Support for Atheros AR71xx built-in OHCI controller ++ + config USB_OHCI_HCD_PPC_SOC + bool "OHCI support for on-chip PPC USB controller" + depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1034,6 +1034,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ixp4xx_ehci_driver + #endif + ++#ifdef CONFIG_USB_EHCI_AR71XX ++#include "ehci-ar71xx.c" ++#define PLATFORM_DRIVER ehci_ar71xx_driver ++#endif ++ + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) + #error "missing bus glue for ehci-hcd" +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1080,6 +1080,11 @@ MODULE_LICENSE ("GPL"); + #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver + #endif + ++#ifdef CONFIG_USB_OHCI_AR71XX ++#include "ohci-ar71xx.c" ++#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver ++#endif ++ + #if !defined(PCI_DRIVER) && \ + !defined(PLATFORM_DRIVER) && \ + !defined(OF_PLATFORM_DRIVER) && \ diff --git a/target/linux/ar71xx/patches-2.6.28/004-ar71xx_spi_controller.patch b/target/linux/ar71xx/patches-2.6.28/004-ar71xx_spi_controller.patch new file mode 100644 index 0000000..9c196e0 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/004-ar71xx_spi_controller.patch @@ -0,0 +1,26 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -53,6 +53,13 @@ if SPI_MASTER + + comment "SPI Master Controller Drivers" + ++config SPI_AR71XX ++ tristate "Atheros AR71xx SPI Controller" ++ depends on SPI_MASTER && ATHEROS_AR71XX ++ select SPI_BITBANG ++ help ++ This is the SPI contoller driver for Atheros AR71xx. ++ + config SPI_ATMEL + tristate "Atmel SPI Controller" + depends on (ARCH_AT91 || AVR32) +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -11,6 +11,7 @@ endif + obj-$(CONFIG_SPI_MASTER) += spi.o + + # SPI master controller drivers (bus) ++obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o + obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o + obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o + obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o diff --git a/target/linux/ar71xx/patches-2.6.28/005-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-2.6.28/005-ar71xx_mac_driver.patch new file mode 100644 index 0000000..59b9a57 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/005-ar71xx_mac_driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -2039,6 +2039,8 @@ config ACENIC_OMIT_TIGON_I + + The safe and default value for this is N. + ++source drivers/net/ag71xx/Kconfig ++ + config DL2K + tristate "DL2000/TC902x-based Gigabit Ethernet support" + depends on PCI +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -2,6 +2,7 @@ + # Makefile for the Linux network (ethercard) device drivers. + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_E1000) += e1000/ + obj-$(CONFIG_E1000E) += e1000e/ + obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/ diff --git a/target/linux/ar71xx/patches-2.6.28/006-ar71xx_wdt_driver.patch b/target/linux/ar71xx/patches-2.6.28/006-ar71xx_wdt_driver.patch new file mode 100644 index 0000000..bf0ffcd --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/006-ar71xx_wdt_driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -747,6 +747,13 @@ config TXX9_WDT + help + Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. + ++config AR71XX_WDT ++ tristate "Atheros AR71xx Watchdog Timer" ++ depends on ATHEROS_AR71XX ++ help ++ Hardware driver for the built-in watchdog timer on the Atheros ++ AR71xx SoCs. ++ + # PARISC Architecture + + # POWERPC Architecture +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -106,6 +106,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o ++obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o + + # PARISC Architecture + diff --git a/target/linux/ar71xx/patches-2.6.28/100-mtd_m25p80_add_pm25lv_flash_support.patch b/target/linux/ar71xx/patches-2.6.28/100-mtd_m25p80_add_pm25lv_flash_support.patch new file mode 100644 index 0000000..2fac990 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/100-mtd_m25p80_add_pm25lv_flash_support.patch @@ -0,0 +1,13 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -500,6 +500,10 @@ static struct flash_info __devinitdata m + { "at26df161a", 0x1f4601, 0, 64 * 1024, 32, SECT_4K, }, + { "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, }, + ++ /* PMC -- pm25x "blocks" are 32K, sectors are 4K */ ++ { "pm25lv512", 0, 32 * 1024, 2, SECT_4K }, ++ { "pm25lv010", 0, 32 * 1024, 4, SECT_4K }, ++ + /* Spansion -- single (large) sector size only, at least + * for the chips listed here (without boot sectors). + */ diff --git a/target/linux/ar71xx/patches-2.6.28/101-ksz8041_phy_driver.patch b/target/linux/ar71xx/patches-2.6.28/101-ksz8041_phy_driver.patch new file mode 100644 index 0000000..78b9b33 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/101-ksz8041_phy_driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -83,6 +83,11 @@ config MVSWITCH_PHY + ---help--- + Currently supports the Marvell 88E6060 switch. + ++config MICREL_PHY ++ tristate "Drivers for Micrel/Kendin PHYs" ++ ---help--- ++ Currently has a driver for the KSZ8041 ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_MICREL_PHY) += micrel.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_OF_GPIO) += mdio-ofgpio.o diff --git a/target/linux/ar71xx/patches-2.6.28/102-mtd_m25p80_add_myloader_parser.patch b/target/linux/ar71xx/patches-2.6.28/102-mtd_m25p80_add_myloader_parser.patch new file mode 100644 index 0000000..0eb74e9 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/102-mtd_m25p80_add_myloader_parser.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -707,12 +707,17 @@ static int __devinit m25p_probe(struct s + struct mtd_partition *parts = NULL; + int nr_parts = 0; + ++ static const char *part_probes[] = { + #ifdef CONFIG_MTD_CMDLINE_PARTS +- static const char *part_probes[] = { "cmdlinepart", NULL, }; ++ "cmdlinepart", ++#endif ++#ifdef CONFIG_MTD_MYLOADER_PARTS ++ "MyLoader", ++#endif ++ NULL, }; + + nr_parts = parse_mtd_partitions(&flash->mtd, + part_probes, &parts, 0); +-#endif + + if (nr_parts <= 0 && data && data->parts) { + parts = data->parts; diff --git a/target/linux/ar71xx/patches-2.6.28/103-mtd_m25p80_add_en25p32_support.patch b/target/linux/ar71xx/patches-2.6.28/103-mtd_m25p80_add_en25p32_support.patch new file mode 100644 index 0000000..97c2a8f --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/103-mtd_m25p80_add_en25p32_support.patch @@ -0,0 +1,12 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -500,6 +500,9 @@ static struct flash_info __devinitdata m + { "at26df161a", 0x1f4601, 0, 64 * 1024, 32, SECT_4K, }, + { "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, }, + ++ /* EON -- en25px */ ++ { "en25p32", 0x1c2016, 64 * 1024, 64, }, ++ + /* PMC -- pm25x "blocks" are 32K, sectors are 4K */ + { "pm25lv512", 0, 32 * 1024, 2, SECT_4K }, + { "pm25lv010", 0, 32 * 1024, 4, SECT_4K }, diff --git a/target/linux/ar71xx/patches-2.6.28/104-mtd_m25p80_add_redboot_parser.patch b/target/linux/ar71xx/patches-2.6.28/104-mtd_m25p80_add_redboot_parser.patch new file mode 100644 index 0000000..6b3089c --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/104-mtd_m25p80_add_redboot_parser.patch @@ -0,0 +1,12 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -717,6 +717,9 @@ static int __devinit m25p_probe(struct s + #ifdef CONFIG_MTD_MYLOADER_PARTS + "MyLoader", + #endif ++#ifdef CONFIG_MTD_REDBOOT_PARTS ++ "RedBoot", ++#endif + NULL, }; + + nr_parts = parse_mtd_partitions(&flash->mtd, diff --git a/target/linux/ar71xx/patches-2.6.28/140-redboot_partition_scan.patch b/target/linux/ar71xx/patches-2.6.28/140-redboot_partition_scan.patch new file mode 100644 index 0000000..289d4eb --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/140-redboot_partition_scan.patch @@ -0,0 +1,54 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; + } + } else { + offset = directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + offset += master->erasesize; + if (offset == master->size) + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; +- + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); + +@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; diff --git a/target/linux/ar71xx/patches-2.6.28/200-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-2.6.28/200-rb4xx_nand_driver.patch new file mode 100644 index 0000000..9e4477d --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/200-rb4xx_nand_driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -420,4 +420,8 @@ config MTD_NAND_SH_FLCTL + Several Renesas SuperH CPU has FLCTL. This option enables support + for NAND Flash using FLCTL. This driver support SH7723. + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && ATHEROS_AR71XX ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-2.6.28/300-mips_fw_myloader.patch b/target/linux/ar71xx/patches-2.6.28/300-mips_fw_myloader.patch new file mode 100644 index 0000000..511fbbf --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/300-mips_fw_myloader.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -160,6 +160,7 @@ endif + # + libs-$(CONFIG_ARC) += arch/mips/fw/arc/ + libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ ++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ + libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ + libs-y += arch/mips/fw/lib/ + libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -778,6 +778,9 @@ config MIPS_NILE4 + config MIPS_DISABLE_OBSOLETE_IDE + bool + ++config MYLOADER ++ bool ++ + config SYNC_R4K + bool + diff --git a/target/linux/ar71xx/patches-2.6.28/800-ag71xx_remove_netif_schedule.patch b/target/linux/ar71xx/patches-2.6.28/800-ag71xx_remove_netif_schedule.patch new file mode 100644 index 0000000..d278d4d --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/800-ag71xx_remove_netif_schedule.patch @@ -0,0 +1,16 @@ +--- a/drivers/net/ag71xx/ag71xx_phy.c ++++ b/drivers/net/ag71xx/ag71xx_phy.c +@@ -138,12 +138,8 @@ static void ag71xx_phy_link_adjust(struc + } + } + +- if (phydev->link != ag->link) { +- if (phydev->link) +- netif_schedule(dev); +- ++ if (phydev->link != ag->link) + status_change = 1; +- } + + ag->link = phydev->link; + ag->duplex = phydev->duplex; diff --git a/target/linux/ar71xx/patches-2.6.28/801-ag71xx_rename_mii_bus_dev_to_mii_bus_parent.patch b/target/linux/ar71xx/patches-2.6.28/801-ag71xx_rename_mii_bus_dev_to_mii_bus_parent.patch new file mode 100644 index 0000000..d9bd0b9 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/801-ag71xx_rename_mii_bus_dev_to_mii_bus_parent.patch @@ -0,0 +1,11 @@ +--- a/drivers/net/ag71xx/ag71xx_mdio.c ++++ b/drivers/net/ag71xx/ag71xx_mdio.c +@@ -160,7 +160,7 @@ static int __init ag71xx_mdio_probe(stru + am->mii_bus.reset = ag71xx_mdio_reset; + am->mii_bus.irq = am->mii_irq; + am->mii_bus.priv = am; +- am->mii_bus.dev = &pdev->dev; ++ am->mii_bus.parent = &pdev->dev; + snprintf(am->mii_bus.id, MII_BUS_ID_SIZE, "%x", 0); + + pdata = pdev->dev.platform_data; diff --git a/target/linux/ar71xx/patches-2.6.28/802-ag71xx_mdio_dynamic_mdio_bus.patch b/target/linux/ar71xx/patches-2.6.28/802-ag71xx_mdio_dynamic_mdio_bus.patch new file mode 100644 index 0000000..eb3514c --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/802-ag71xx_mdio_dynamic_mdio_bus.patch @@ -0,0 +1,90 @@ +--- a/drivers/net/ag71xx/ag71xx_mdio.c ++++ b/drivers/net/ag71xx/ag71xx_mdio.c +@@ -57,7 +57,7 @@ static int ag71xx_mdio_mii_read(struct a + while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { + if (i-- == 0) { + printk(KERN_ERR "%s: mii_read timed out\n", +- am->mii_bus.name); ++ am->mii_bus->name); + ret = 0xffff; + goto out; + } +@@ -88,7 +88,7 @@ static void ag71xx_mdio_mii_write(struct + while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { + if (i-- == 0) { + printk(KERN_ERR "%s: mii_write timed out\n", +- am->mii_bus.name); ++ am->mii_bus->name); + break; + } + udelay(AG71XX_MDIO_DELAY); +@@ -154,23 +154,27 @@ static int __init ag71xx_mdio_probe(stru + goto err_free_mdio; + } + +- am->mii_bus.name = "ag71xx_mdio"; +- am->mii_bus.read = ag71xx_mdio_read; +- am->mii_bus.write = ag71xx_mdio_write; +- am->mii_bus.reset = ag71xx_mdio_reset; +- am->mii_bus.irq = am->mii_irq; +- am->mii_bus.priv = am; +- am->mii_bus.parent = &pdev->dev; +- snprintf(am->mii_bus.id, MII_BUS_ID_SIZE, "%x", 0); ++ am->mii_bus = mdiobus_alloc(); ++ if (am->mii_bus == NULL) ++ goto err_iounmap; ++ ++ am->mii_bus->name = "ag71xx_mdio"; ++ am->mii_bus->read = ag71xx_mdio_read; ++ am->mii_bus->write = ag71xx_mdio_write; ++ am->mii_bus->reset = ag71xx_mdio_reset; ++ am->mii_bus->irq = am->mii_irq; ++ am->mii_bus->priv = am; ++ am->mii_bus->parent = &pdev->dev; ++ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + + pdata = pdev->dev.platform_data; + if (pdata) +- am->mii_bus.phy_mask = pdata->phy_mask; ++ am->mii_bus->phy_mask = pdata->phy_mask; + + for (i = 0; i < PHY_MAX_ADDR; i++) + am->mii_irq[i] = PHY_POLL; + +- err = mdiobus_register(&am->mii_bus); ++ err = mdiobus_register(am->mii_bus); + if (err) + goto err_iounmap; + +@@ -194,7 +198,8 @@ static int __exit ag71xx_mdio_remove(str + + if (am) { + ag71xx_mdio_bus = NULL; +- mdiobus_unregister(&am->mii_bus); ++ mdiobus_unregister(am->mii_bus); ++ mdiobus_free(am->mii_bus); + iounmap(am->mdio_base); + kfree(am); + platform_set_drvdata(pdev, NULL); +--- a/drivers/net/ag71xx/ag71xx.h ++++ b/drivers/net/ag71xx/ag71xx.h +@@ -101,7 +101,7 @@ struct ag71xx_ring { + }; + + struct ag71xx_mdio { +- struct mii_bus mii_bus; ++ struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + void __iomem *mdio_base; + }; +--- a/drivers/net/ag71xx/ag71xx_main.c ++++ b/drivers/net/ag71xx/ag71xx_main.c +@@ -807,7 +807,7 @@ static int __init ag71xx_probe(struct pl + ag = netdev_priv(dev); + ag->pdev = pdev; + ag->dev = dev; +- ag->mii_bus = &ag71xx_mdio_bus->mii_bus; ++ ag->mii_bus = ag71xx_mdio_bus->mii_bus; + ag->msg_enable = netif_msg_init(ag71xx_debug, + AG71XX_DEFAULT_MSG_ENABLE); + spin_lock_init(&ag->lock); diff --git a/target/linux/ar71xx/patches-2.6.28/901-get_c0_compare_irq_function.patch b/target/linux/ar71xx/patches-2.6.28/901-get_c0_compare_irq_function.patch new file mode 100644 index 0000000..ec3924f --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/901-get_c0_compare_irq_function.patch @@ -0,0 +1,29 @@ +--- a/arch/mips/kernel/traps.c ++++ b/arch/mips/kernel/traps.c +@@ -47,6 +47,7 @@ + #include <asm/mmu_context.h> + #include <asm/types.h> + #include <asm/stacktrace.h> ++#include <asm/time.h> + + extern void check_wait(void); + extern asmlinkage void r4k_wait(void); +@@ -1514,6 +1515,8 @@ void __cpuinit per_cpu_trap_init(void) + */ + if (cpu_has_mips_r2) { + cp0_compare_irq = (read_c0_intctl() >> 29) & 7; ++ if (get_c0_compare_irq) ++ cp0_compare_irq = get_c0_compare_irq(); + cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; + if (cp0_perfcount_irq == cp0_compare_irq) + cp0_perfcount_irq = -1; +--- a/arch/mips/include/asm/time.h ++++ b/arch/mips/include/asm/time.h +@@ -53,6 +53,7 @@ extern int (*perf_irq)(void); + #ifdef CONFIG_CEVT_R4K + extern int mips_clockevent_init(void); + extern unsigned int __weak get_c0_compare_int(void); ++extern unsigned int __weak get_c0_compare_irq(void); + #else + static inline int mips_clockevent_init(void) + { diff --git a/target/linux/ar71xx/patches-2.6.28/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.28/902-mips_clocksource_init_war.patch new file mode 100644 index 0000000..03a66ff --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.28/902-mips_clocksource_init_war.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -15,6 +15,22 @@ + #include <asm/cevt-r4k.h> + + /* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ ++/* + * The SMTC Kernel for the 34K, 1004K, et. al. replaces several + * of these routines with SMTC-specific variants. + */ +@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } +@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void) + return (read_c0_cause() >> cp0_compare_irq) & 0x100; + } + +-/* +- * Compare interrupt can be routed and latched outside the core, +- * so a single execution hazard barrier may not be enough to give +- * it time to clear as seen in the Cause register. 4 time the +- * pipeline depth seems reasonably conservative, and empirically +- * works better in configurations with high CPU/bus clock ratios. +- */ +- +-#define compare_change_hazard() \ +- do { \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- } while (0) +- + int c0_compare_int_usable(void) + { + unsigned int delta; |