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authorChuanhong Guo <gch981213@gmail.com>2018-08-07 12:02:07 +0800
committerMathias Kresin <dev@kresin.me>2018-08-09 18:44:57 +0200
commit387736af41444945da6a5e51748e91011569c03e (patch)
treeb4e09e1c1aef9b377510f7812de0c56cf7a70c71 /target/linux/ath79/dts/ar7100.dtsi
parent23519edbcaa9cfd24b5a6fff44770f0fa9e13f3c (diff)
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ath79: ag71xx: remove PHY reset
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/ath79/dts/ar7100.dtsi')
-rw-r--r--target/linux/ath79/dts/ar7100.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ath79/dts/ar7100.dtsi b/target/linux/ath79/dts/ar7100.dtsi
index 9957b8d..8994a7d 100644
--- a/target/linux/ath79/dts/ar7100.dtsi
+++ b/target/linux/ath79/dts/ar7100.dtsi
@@ -180,8 +180,8 @@
pll-handle = <&pll>;
phy-mode = "rgmii";
- resets = <&rst 8>, <&rst 9>;
- reset-names = "phy", "mac";
+ resets = <&rst 9>;
+ reset-names = "mac";
};
&mdio1 {
@@ -199,6 +199,6 @@
phy-mode = "rgmii";
- resets = <&rst 12>, <&rst 13>;
- reset-names = "phy", "mac";
+ resets = <&rst 13>;
+ reset-names = "mac";
};