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authorFelix Fietkau <nbd@openwrt.org>2014-06-10 09:06:25 +0000
committerFelix Fietkau <nbd@openwrt.org>2014-06-10 09:06:25 +0000
commit75b4c400c790d2832370a040f94eef75d214e6f5 (patch)
tree0408d86f6c76b1a8ba51d307b9a8de20c8996a6e /target/linux/atheros/patches-3.10/105-ar2315_pci.patch
parente49636472d539f14a455f541115faddc39b4fde4 (diff)
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atheros: fix too short msleep
Use msleep(20) instead of msleep(10) to make code closer to reality since msleep can sleep for up to 20ms even we request shorter delay. All updated calls are located in PCI initialization routine which is called only once upon device boot. So there should be no performance issues caused by more longer delay. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41096
Diffstat (limited to 'target/linux/atheros/patches-3.10/105-ar2315_pci.patch')
-rw-r--r--target/linux/atheros/patches-3.10/105-ar2315_pci.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
index 7a9714f..7108d6c 100644
--- a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
+++ b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
@@ -198,11 +198,11 @@
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
+
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
-+ msleep(10);
++ msleep(20);
+
+ reg &= ~AR2315_RESET_PCIDMA;
+ ar231x_write_reg(AR2315_RESET, reg);
-+ msleep(10);
++ msleep(20);
+
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);