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| author | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:01:04 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:01:04 +0000 |
| commit | 892ef42a7701a50dd05168575f6b13650a1bc9a1 (patch) | |
| tree | 83329867de519de92560c71221db59024f917c85 /target/linux/atheros/patches-3.18/105-ar2315_pci.patch | |
| parent | cd4462326c2870d40d6aca47f5fa93d318718c87 (diff) | |
| download | mtk-20170518-892ef42a7701a50dd05168575f6b13650a1bc9a1.zip mtk-20170518-892ef42a7701a50dd05168575f6b13650a1bc9a1.tar.gz mtk-20170518-892ef42a7701a50dd05168575f6b13650a1bc9a1.tar.bz2 | |
atheros: v3.18: remap main SoC MMR memory
Honestly remap main SoC MMR mem and use accessor functions to
interact with registers. Now registers defined relatively to base
address (e.g. SDRAM controller base address).
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 44723
Diffstat (limited to 'target/linux/atheros/patches-3.18/105-ar2315_pci.patch')
| -rw-r--r-- | target/linux/atheros/patches-3.18/105-ar2315_pci.patch | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/target/linux/atheros/patches-3.18/105-ar2315_pci.patch b/target/linux/atheros/patches-3.18/105-ar2315_pci.patch index 267053c..6665a11 100644 --- a/target/linux/atheros/patches-3.18/105-ar2315_pci.patch +++ b/target/linux/atheros/patches-3.18/105-ar2315_pci.patch @@ -520,7 +520,7 @@ + default y --- a/arch/mips/ath25/ar2315.c +++ b/arch/mips/ath25/ar2315.c -@@ -116,6 +116,10 @@ static void ar2315_irq_dispatch(void) +@@ -137,6 +137,10 @@ static void ar2315_irq_dispatch(void) do_IRQ(AR2315_IRQ_WLAN0_INTRS); else if (pending & CAUSEF_IP4) do_IRQ(AR2315_IRQ_ENET0_INTRS); @@ -531,7 +531,7 @@ else if (pending & CAUSEF_IP2) do_IRQ(AR2315_IRQ_MISC_INTRS); else if (pending & CAUSEF_IP7) -@@ -423,8 +427,60 @@ void __init ar2315_plat_mem_setup(void) +@@ -450,8 +454,60 @@ void __init ar2315_plat_mem_setup(void) _machine_restart = ar2315_restart; } @@ -566,25 +566,25 @@ +#ifdef CONFIG_PCI_AR2315 + if (ath25_soc == ATH25_SOC_AR2315) { + /* Reset PCI DMA logic */ -+ ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA); + msleep(20); -+ ar231x_mask_reg(AR2315_RESET, AR2315_RESET_PCIDMA, 0); ++ ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0); + msleep(20); + + /* Configure endians */ -+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB | -+ AR2315_CONFIG_PCIAHB_BRIDGE); ++ ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB | ++ AR2315_CONFIG_PCIAHB_BRIDGE); + + /* Configure as PCI host with DMA */ -+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << -+ AR2315_PCICLK_DIV_S)); -+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); -+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | -+ AR2315_IF_MASK, AR2315_IF_PCI | -+ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << -+ AR2315_IF_PCI_CLK_SHIFT)); ++ ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << ++ AR2315_PCICLK_DIV_S)); ++ ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | ++ AR2315_IF_MASK, AR2315_IF_PCI | ++ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << ++ AR2315_IF_PCI_CLK_SHIFT)); + + platform_device_register_simple("ar2315-pci", -1, + ar2315_pci_res, |