brcm2708: update linux 4.4 patches to latest version

As usual these patches were extracted from the raspberry pi repo:
https://github.com/raspberrypi/linux/tree/rpi-4.4.y

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 188 insertions, 0 deletions

diff --git a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch
new file mode 100644
index 0000000..ca360ea
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch
@@ -0,0 +1,188 @@
+From 4da1c0d401cb719b7347117c226f4d4d95797972 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 14:20:15 +0000
+Subject: [PATCH 261/304] clk: bcm2835: expose raw clock-registers via debugfs
+
+For debugging purposes under some circumstance
+it helps to be able to see the actual clock registers.
+
+E.g: when looking at the clock divider it is helpful to
+see what the actual clock divider is.
+
+This patch exposes all the clock registers specific to each
+clock/pll/pll-divider via debugfs.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Acked-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 96bf9c69d5729781018a00f08e2ae395ec3346b4)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 101 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 101 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -37,6 +37,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/clkdev.h>
+ #include <linux/clk/bcm2835.h>
++#include <linux/debugfs.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+@@ -313,6 +314,27 @@ static inline u32 cprman_read(struct bcm
+ 	return readl(cprman->regs + reg);
+ }
+ 
++static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
++				  struct debugfs_reg32 *regs, size_t nregs,
++				  struct dentry *dentry)
++{
++	struct dentry *regdump;
++	struct debugfs_regset32 *regset;
++
++	regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
++	if (!regset)
++		return -ENOMEM;
++
++	regset->regs = regs;
++	regset->nregs = nregs;
++	regset->base = cprman->regs + base;
++
++	regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
++					  regset);
++
++	return regdump ? 0 : -ENOMEM;
++}
++
+ /*
+  * These are fixed clocks. They're probably not all root clocks and it may
+  * be possible to turn them on and off but until this is mapped out better
+@@ -1040,6 +1062,36 @@ static int bcm2835_pll_set_rate(struct c
+ 	return 0;
+ }
+ 
++static int bcm2835_pll_debug_init(struct clk_hw *hw,
++				  struct dentry *dentry)
++{
++	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
++	struct bcm2835_cprman *cprman = pll->cprman;
++	const struct bcm2835_pll_data *data = pll->data;
++	struct debugfs_reg32 *regs;
++
++	regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
++	if (!regs)
++		return -ENOMEM;
++
++	regs[0].name = "cm_ctrl";
++	regs[0].offset = data->cm_ctrl_reg;
++	regs[1].name = "a2w_ctrl";
++	regs[1].offset = data->a2w_ctrl_reg;
++	regs[2].name = "frac";
++	regs[2].offset = data->frac_reg;
++	regs[3].name = "ana0";
++	regs[3].offset = data->ana_reg_base + 0 * 4;
++	regs[4].name = "ana1";
++	regs[4].offset = data->ana_reg_base + 1 * 4;
++	regs[5].name = "ana2";
++	regs[5].offset = data->ana_reg_base + 2 * 4;
++	regs[6].name = "ana3";
++	regs[6].offset = data->ana_reg_base + 3 * 4;
++
++	return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
++}
++
+ static const struct clk_ops bcm2835_pll_clk_ops = {
+ 	.is_prepared = bcm2835_pll_is_on,
+ 	.prepare = bcm2835_pll_on,
+@@ -1047,6 +1099,7 @@ static const struct clk_ops bcm2835_pll_
+ 	.recalc_rate = bcm2835_pll_get_rate,
+ 	.set_rate = bcm2835_pll_set_rate,
+ 	.round_rate = bcm2835_pll_round_rate,
++	.debug_init = bcm2835_pll_debug_init,
+ };
+ 
+ struct bcm2835_pll_divider {
+@@ -1147,6 +1200,26 @@ static int bcm2835_pll_divider_set_rate(
+ 	return 0;
+ }
+ 
++static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
++					  struct dentry *dentry)
++{
++	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
++	struct bcm2835_cprman *cprman = divider->cprman;
++	const struct bcm2835_pll_divider_data *data = divider->data;
++	struct debugfs_reg32 *regs;
++
++	regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
++	if (!regs)
++		return -ENOMEM;
++
++	regs[0].name = "cm";
++	regs[0].offset = data->cm_reg;
++	regs[1].name = "a2w";
++	regs[1].offset = data->a2w_reg;
++
++	return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
++}
++
+ static const struct clk_ops bcm2835_pll_divider_clk_ops = {
+ 	.is_prepared = bcm2835_pll_divider_is_on,
+ 	.prepare = bcm2835_pll_divider_on,
+@@ -1154,6 +1227,7 @@ static const struct clk_ops bcm2835_pll_
+ 	.recalc_rate = bcm2835_pll_divider_get_rate,
+ 	.set_rate = bcm2835_pll_divider_set_rate,
+ 	.round_rate = bcm2835_pll_divider_round_rate,
++	.debug_init = bcm2835_pll_divider_debug_init,
+ };
+ 
+ /*
+@@ -1395,6 +1469,31 @@ static u8 bcm2835_clock_get_parent(struc
+ 	return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
+ }
+ 
++static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
++	{
++		.name = "ctl",
++		.offset = 0,
++	},
++	{
++		.name = "div",
++		.offset = 4,
++	},
++};
++
++static int bcm2835_clock_debug_init(struct clk_hw *hw,
++				    struct dentry *dentry)
++{
++	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
++	struct bcm2835_cprman *cprman = clock->cprman;
++	const struct bcm2835_clock_data *data = clock->data;
++
++	return bcm2835_debugfs_regset(
++		cprman, data->ctl_reg,
++		bcm2835_debugfs_clock_reg32,
++		ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
++		dentry);
++}
++
+ static const struct clk_ops bcm2835_clock_clk_ops = {
+ 	.is_prepared = bcm2835_clock_is_on,
+ 	.prepare = bcm2835_clock_on,
+@@ -1404,6 +1503,7 @@ static const struct clk_ops bcm2835_cloc
+ 	.determine_rate = bcm2835_clock_determine_rate,
+ 	.set_parent = bcm2835_clock_set_parent,
+ 	.get_parent = bcm2835_clock_get_parent,
++	.debug_init = bcm2835_clock_debug_init,
+ };
+ 
+ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
+@@ -1422,6 +1522,7 @@ static const struct clk_ops bcm2835_vpu_
+ 	.determine_rate = bcm2835_clock_determine_rate,
+ 	.set_parent = bcm2835_clock_set_parent,
+ 	.get_parent = bcm2835_clock_get_parent,
++	.debug_init = bcm2835_clock_debug_init,
+ };
+ 
+ static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,