diff options
| author | Etienne Haarsma <bladeoner112@gmail.com> | 2018-04-28 21:51:24 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-04-30 08:00:27 +0200 |
| commit | 81573ea259247f1c6c1a7a490de174d0a6c48a64 (patch) | |
| tree | 9dc8bb798d93cd52d2a47b3d699581bd2d69c78c /target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch | |
| parent | afa8873887664bbf42c8e7914dc572da2d3bcb79 (diff) | |
| download | mtk-20170518-81573ea259247f1c6c1a7a490de174d0a6c48a64.zip mtk-20170518-81573ea259247f1c6c1a7a490de174d0a6c48a64.tar.gz mtk-20170518-81573ea259247f1c6c1a7a490de174d0a6c48a64.tar.bz2 | |
kernel: bump kernel 4.4 to 4.4.129 for 17.01
* Refreshed patches
Compile-tested: ar71xx
Run-tested: ar71xx
Signed-off-by: Etienne Haarsma <bladeoner112@gmail.com>
Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch index 9c9518e..5683b04 100644 --- a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch +++ b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch @@ -26,7 +26,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> #define CM_EMMCCTL 0x1c0 #define CM_EMMCDIV 0x1c4 -@@ -1616,6 +1618,12 @@ static const struct bcm2835_clk_desc clk +@@ -1618,6 +1620,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), @@ -39,7 +39,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( -@@ -1630,6 +1638,7 @@ static const struct bcm2835_clk_desc clk +@@ -1632,6 +1640,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_ISPDIV, .int_bits = 4, .frac_bits = 8), @@ -47,7 +47,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* * Secondary SDRAM clock. Used for low-voltage modes when the PLL * in the SDRAM controller can't be used. -@@ -1661,6 +1670,36 @@ static const struct bcm2835_clk_desc clk +@@ -1663,6 +1672,36 @@ static const struct bcm2835_clk_desc clk .is_vpu_clock = true), /* clocks with per parent mux */ @@ -84,7 +84,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( -@@ -1669,6 +1708,29 @@ static const struct bcm2835_clk_desc clk +@@ -1671,6 +1710,29 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_EMMCDIV, .int_bits = 4, .frac_bits = 8), @@ -114,7 +114,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( .name = "hsm", -@@ -1690,12 +1752,26 @@ static const struct bcm2835_clk_desc clk +@@ -1692,12 +1754,26 @@ static const struct bcm2835_clk_desc clk .int_bits = 12, .frac_bits = 12, .is_mash_clock = true), @@ -141,7 +141,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( .name = "vec", -@@ -1704,6 +1780,20 @@ static const struct bcm2835_clk_desc clk +@@ -1706,6 +1782,20 @@ static const struct bcm2835_clk_desc clk .int_bits = 4, .frac_bits = 0), |