brcm2708: update linux 4.4 patches to latest version

As usual these patches were extracted and rebased from the raspberry pi repo:
https://github.com/raspberrypi/linux/tree/rpi-4.4.y

- led1 can't be controlled on rpi-3 for linux 4.4, remove it.
- Fix modules.mk typos.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 40 insertions, 0 deletions

diff --git a/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch b/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch
new file mode 100644
index 0000000..a66653e
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch
@@ -0,0 +1,40 @@
+From 5c301af484ece3e61146572167bbe9418d536616 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@free-electrons.com>
+Date: Thu, 1 Dec 2016 22:00:20 +0100
+Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC
+ clock
+
+The VEC clock requires needs to be set at exactly 108MHz. Allow rate
+change propagation on PLLH_AUX to match this requirement wihtout
+impacting other IPs (PLLH is currently only used by the HDMI encoder,
+which cannot be enabled when the VEC encoder is enabled).
+
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index 5f0e2f3..d023e4a 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1920,7 +1920,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
+ 		.ctl_reg = CM_VECCTL,
+ 		.div_reg = CM_VECDIV,
+ 		.int_bits = 4,
+-		.frac_bits = 0),
++		.frac_bits = 0,
++		/*
++		 * Allow rate change propagation only on PLLH_AUX which is
++		 * assigned index 7 in the parent array.
++		 */
++		.set_rate_parent = BIT(7)),
+ 
+ 	/* dsi clocks */
+ 	[BCM2835_CLOCK_DSI0E]	= REGISTER_PER_CLK(
+-- 
+2.1.4
+