brcm47xx-2.6: add a few nops here, some irq saving there, blast the full cache on page icache flushes i really hate the broadcom cpu bugs, but it's much more stable now. PS: A /* Ouch */ in the original source showed me the way ;)

SVN-Revision: 8165

1 files changed, 300 insertions, 31 deletions

diff --git a/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch b/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch
index a353185..ebc40f9 100644
--- a/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx-2.6/patches-2.6.22/150-cpu_fixes.patch
@@ -1,7 +1,7 @@
-Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
+Index: linux-2.6.22/arch/mips/kernel/genex.S
 ===================================================================
---- linux-2.6.22-rc6.orig/arch/mips/kernel/genex.S	2007-07-04 01:52:47.812492000 +0200
-+++ linux-2.6.22-rc6/arch/mips/kernel/genex.S	2007-07-04 01:53:01.585352750 +0200
+--- linux-2.6.22.orig/arch/mips/kernel/genex.S	2007-07-26 06:29:25.057170943 +0200
++++ linux-2.6.22/arch/mips/kernel/genex.S	2007-07-26 06:29:40.890073208 +0200
 @@ -51,6 +51,10 @@
  NESTED(except_vec3_generic, 0, sp)
  	.set	push
@@ -13,10 +13,10 @@ Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
  #if R5432_CP0_INTERRUPT_WAR
  	mfc0	k0, CP0_INDEX
  #endif
-Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
+Index: linux-2.6.22/arch/mips/mm/c-r4k.c
 ===================================================================
---- linux-2.6.22-rc6.orig/arch/mips/mm/c-r4k.c	2007-07-04 01:53:01.545350250 +0200
-+++ linux-2.6.22-rc6/arch/mips/mm/c-r4k.c	2007-07-04 02:17:11.435962750 +0200
+--- linux-2.6.22.orig/arch/mips/mm/c-r4k.c	2007-07-26 06:29:40.826069560 +0200
++++ linux-2.6.22/arch/mips/mm/c-r4k.c	2007-07-26 06:32:45.956619550 +0200
 @@ -29,6 +29,9 @@
  #include <asm/cacheflush.h> /* for run_uncached() */
  
@@ -27,7 +27,19 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
-@@ -93,6 +96,9 @@
+@@ -85,14 +88,21 @@
+ 
+ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	R4600_HIT_CACHEOP_WAR_IMPL;
+ 	blast_dcache32_page(addr);
++	local_irq_restore(flags);
+ }
+ 
+ static void __init r4k_blast_dcache_page_setup(void)
  {
  	unsigned long  dc_lsize = cpu_dcache_line_size();
  
@@ -37,7 +49,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache_page = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -107,6 +113,9 @@
+@@ -107,6 +117,9 @@
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -47,7 +59,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache_page_indexed = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -121,6 +130,9 @@
+@@ -121,6 +134,9 @@
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -57,26 +69,274 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -538,6 +550,9 @@
- 		r4k_blast_icache();
- 	else
- 		protected_blast_icache_range(start, end);
+@@ -202,8 +218,12 @@
+ 
+ static void (* r4k_blast_icache_page)(unsigned long addr);
+ 
++static void r4k_flush_cache_all(void);
+ static void __init r4k_blast_icache_page_setup(void)
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_blast_icache_page = (void *)r4k_flush_cache_all;
++#else
+ 	unsigned long ic_lsize = cpu_icache_line_size();
+ 
+ 	if (ic_lsize == 0)
+@@ -214,6 +234,7 @@
+ 		r4k_blast_icache_page = blast_icache32_page;
+ 	else if (ic_lsize == 64)
+ 		r4k_blast_icache_page = blast_icache64_page;
++#endif
+ }
+ 
+ 
+@@ -221,6 +242,9 @@
+ 
+ static void __init r4k_blast_icache_page_indexed_setup(void)
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_blast_icache_page_indexed = (void *)r4k_flush_cache_all;
++#else
+ 	unsigned long ic_lsize = cpu_icache_line_size();
+ 
+ 	if (ic_lsize == 0)
+@@ -239,6 +263,7 @@
+ 				blast_icache32_page_indexed;
+ 	} else if (ic_lsize == 64)
+ 		r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
++#endif
+ }
+ 
+ static void (* r4k_blast_icache)(void);
+@@ -322,12 +347,17 @@
+  */
+ static inline void local_r4k_flush_cache_all(void * args)
+ {
++	unsigned long flags;
 +
-+	if (bcm4710)
-+		r4k_flush_cache_all();
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_all(void)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
+@@ -335,6 +365,9 @@
+ 
+ static inline void local_r4k___flush_cache_all(void * args)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
+ 	r4k_blast_icache();
+ 
+@@ -348,6 +381,7 @@
+ 	case CPU_R14000:
+ 		r4k_blast_scache();
+ 	}
++	local_irq_restore(flags);
  }
  
+ static void r4k___flush_cache_all(void)
+@@ -358,17 +392,21 @@
+ static inline void local_r4k_flush_cache_range(void * args)
+ {
+ 	struct vm_area_struct *vma = args;
++	unsigned long flags;
+ 
+ 	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
+ 		return;
+ 
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_range(struct vm_area_struct *vma,
+ 	unsigned long start, unsigned long end)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+@@ -377,6 +415,7 @@
+ static inline void local_r4k_flush_cache_mm(void * args)
+ {
+ 	struct mm_struct *mm = args;
++	unsigned long flags;
+ 
+ 	if (!cpu_context(smp_processor_id(), mm))
+ 		return;
+@@ -395,12 +434,15 @@
+ 		return;
+ 	}
+ 
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_mm(struct mm_struct *mm)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
+@@ -420,6 +462,7 @@
+ 	unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
+ 	int exec = vma->vm_flags & VM_EXEC;
+ 	struct mm_struct *mm = vma->vm_mm;
++	unsigned long flags;
+ 	pgd_t *pgdp;
+ 	pud_t *pudp;
+ 	pmd_t *pmdp;
+@@ -451,8 +494,9 @@
+ 	 * for every cache flush operation.  So we do indexed flushes
+ 	 * in that case, which doesn't overly flush the cache too much.
+ 	 */
++	local_irq_save(flags);
+ 	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
+-		if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
++		if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
+ 			r4k_blast_dcache_page(addr);
+ 			if (exec && !cpu_icache_snoops_remote_store)
+ 				r4k_blast_scache_page(addr);
+@@ -460,14 +504,14 @@
+ 		if (exec)
+ 			r4k_blast_icache_page(addr);
+ 
+-		return;
++		goto done;
+ 	}
+ 
+ 	/*
+ 	 * Do indexed flush, too much work to get the (possible) TLB refills
+ 	 * to work correctly.
+ 	 */
+-	if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
++	if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
+ 		r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
+ 					      paddr : addr);
+ 		if (exec && !cpu_icache_snoops_remote_store) {
+@@ -483,6 +527,8 @@
+ 		} else
+ 			r4k_blast_icache_page_indexed(addr);
+ 	}
++done:
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_page(struct vm_area_struct *vma,
+@@ -499,7 +545,11 @@
+ 
+ static inline void local_r4k_flush_data_cache_page(void * addr)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	r4k_blast_dcache_page((unsigned long) addr);
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_data_cache_page(unsigned long addr)
+@@ -542,6 +592,9 @@
+ 
  static void r4k_flush_icache_range(unsigned long start, unsigned long end)
-@@ -618,6 +633,8 @@
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_flush_cache_all();
++#else
+ 	struct flush_icache_range_args args;
+ 
+ 	args.start = start;
+@@ -549,12 +602,15 @@
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+ 	instruction_hazard();
++#endif
+ }
+ 
+ #ifdef CONFIG_DMA_NONCOHERENT
+ 
+ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+ {
++	unsigned long flags;
++
+ 	/* Catch bad driver code */
+ 	BUG_ON(size == 0);
+ 
+@@ -571,18 +627,21 @@
+ 	 * subset property so we have to flush the primary caches
+ 	 * explicitly
+ 	 */
++	local_irq_save(flags);
+ 	if (size >= dcache_size) {
+ 		r4k_blast_dcache();
+ 	} else {
+ 		R4600_HIT_CACHEOP_WAR_IMPL;
+ 		blast_dcache_range(addr, addr + size);
+ 	}
+-
+ 	bc_wback_inv(addr, size);
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
+ {
++	unsigned long flags;
++
+ 	/* Catch bad driver code */
+ 	BUG_ON(size == 0);
+ 
+@@ -594,6 +653,7 @@
+ 		return;
+ 	}
+ 
++	local_irq_save(flags);
+ 	if (size >= dcache_size) {
+ 		r4k_blast_dcache();
+ 	} else {
+@@ -602,6 +662,7 @@
+ 	}
+ 
+ 	bc_inv(addr, size);
++	local_irq_restore(flags);
+ }
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+@@ -616,8 +677,12 @@
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 	unsigned long sc_lsize = cpu_scache_line_size();
  	unsigned long addr = (unsigned long) arg;
++	unsigned long flags;
  
++	local_irq_save(flags);
  	R4600_HIT_CACHEOP_WAR_IMPL;
 +	BCM4710_PROTECTED_FILL_TLB(addr);
 +	BCM4710_PROTECTED_FILL_TLB(addr + 4);
  	if (dc_lsize)
  		protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  	if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1144,6 +1161,17 @@
+@@ -644,6 +709,7 @@
+ 	}
+ 	if (MIPS_CACHE_SYNC_WAR)
+ 		__asm__ __volatile__ ("sync");
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_sigtramp(unsigned long addr)
+@@ -1144,6 +1210,17 @@
  	 * silly idea of putting something else there ...
  	 */
  	switch (current_cpu_data.cputype) {
@@ -94,7 +354,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	case CPU_R4000PC:
  	case CPU_R4000SC:
  	case CPU_R4000MC:
-@@ -1174,6 +1202,15 @@
+@@ -1174,6 +1251,15 @@
  	/* Default cache error handler for R4000 and R5000 family */
  	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
  
@@ -110,7 +370,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	probe_pcache();
  	setup_scache();
  
-@@ -1219,5 +1256,13 @@
+@@ -1219,5 +1305,13 @@
  	build_clear_page();
  	build_copy_page();
  	local_r4k___flush_cache_all(NULL);
@@ -124,10 +384,10 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
  	coherency_setup();
 +#endif
  }
-Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
+Index: linux-2.6.22/arch/mips/mm/tlbex.c
 ===================================================================
---- linux-2.6.22-rc6.orig/arch/mips/mm/tlbex.c	2007-07-04 01:53:01.193328250 +0200
-+++ linux-2.6.22-rc6/arch/mips/mm/tlbex.c	2007-07-04 02:17:26.112880000 +0200
+--- linux-2.6.22.orig/arch/mips/mm/tlbex.c	2007-07-26 06:29:40.582055658 +0200
++++ linux-2.6.22/arch/mips/mm/tlbex.c	2007-07-26 06:32:45.964620005 +0200
 @@ -1229,6 +1229,10 @@
  #endif
  }
@@ -139,22 +399,31 @@ Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
  static void __init build_r4000_tlb_refill_handler(void)
  {
  	u32 *p = tlb_handler;
-@@ -1243,6 +1247,11 @@
+@@ -1243,6 +1247,10 @@
  	memset(relocs, 0, sizeof(relocs));
  	memset(final_handler, 0, sizeof(final_handler));
  
 +#ifdef CONFIG_BCM947XX
-+	if (current_cpu_data.cputype == CPU_BCM3302)
-+		i_nop(&p);
++	i_nop(&p);
 +#endif
 +
  	/*
  	 * create the plain linear handler
  	 */
-Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
+@@ -1736,6 +1744,9 @@
+ 	memset(labels, 0, sizeof(labels));
+ 	memset(relocs, 0, sizeof(relocs));
+ 
++#ifdef CONFIG_BCM947XX
++	i_nop(&p);
++#endif
+ 	if (bcm1250_m3_war()) {
+ 		i_MFC0(&p, K0, C0_BADVADDR);
+ 		i_MFC0(&p, K1, C0_ENTRYHI);
+Index: linux-2.6.22/include/asm-mips/r4kcache.h
 ===================================================================
---- linux-2.6.22-rc6.orig/include/asm-mips/r4kcache.h	2007-07-04 01:52:47.840493750 +0200
-+++ linux-2.6.22-rc6/include/asm-mips/r4kcache.h	2007-07-04 01:53:01.673358250 +0200
+--- linux-2.6.22.orig/include/asm-mips/r4kcache.h	2007-07-26 06:29:25.085172538 +0200
++++ linux-2.6.22/include/asm-mips/r4kcache.h	2007-07-26 06:29:40.938075943 +0200
 @@ -17,6 +17,20 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
@@ -357,10 +626,10 @@ Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.22-rc6/include/asm-mips/stackframe.h
+Index: linux-2.6.22/include/asm-mips/stackframe.h
 ===================================================================
---- linux-2.6.22-rc6.orig/include/asm-mips/stackframe.h	2007-07-04 01:52:47.852494500 +0200
-+++ linux-2.6.22-rc6/include/asm-mips/stackframe.h	2007-07-04 01:53:01.697359750 +0200
+--- linux-2.6.22.orig/include/asm-mips/stackframe.h	2007-07-26 06:29:25.093172994 +0200
++++ linux-2.6.22/include/asm-mips/stackframe.h	2007-07-26 06:29:40.962077312 +0200
 @@ -350,6 +350,10 @@
  		.macro	RESTORE_SP_AND_RET
  		LONG_L	sp, PT_R29(sp)