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authorPeter Denison <openwrt@marshadder.org>2008-04-25 20:49:40 +0000
committerPeter Denison <openwrt@marshadder.org>2008-04-25 20:49:40 +0000
commitb6b6155ec81c704cd70157753b38f90fd506e708 (patch)
tree0e3521dc9f267b5f130bb1ac1bcdae91c4be11cb /target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
parent5f13c4844e0784ff40c1d15f5077d945ebf17f9b (diff)
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First step to upgrade of brcm47xx to kernel version 2.6.25
SVN-Revision: 10939
Diffstat (limited to 'target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch')
-rw-r--r--target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch97
1 files changed, 97 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch b/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
new file mode 100644
index 0000000..eea4e26
--- /dev/null
+++ b/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
@@ -0,0 +1,97 @@
+Index: linux-2.6.23/arch/mips/Kconfig
+===================================================================
+--- linux-2.6.23.orig/arch/mips/Kconfig 2007-10-13 02:23:41.484492317 +0200
++++ linux-2.6.23/arch/mips/Kconfig 2007-10-13 02:47:02.784347843 +0200
+@@ -192,7 +192,6 @@
+ select I8259
+ select MIPS_BOARDS_GEN
+ select MIPS_BONITO64
+- select MIPS_CPU_SCACHE
+ select PCI_GT64XXX_PCI0
+ select MIPS_MSC
+ select SWAP_IO_SPACE
+@@ -1281,13 +1280,6 @@
+ bool
+ select BOARD_SCACHE
+
+-#
+-# Support for a MIPS32 / MIPS64 style S-caches
+-#
+-config MIPS_CPU_SCACHE
+- bool
+- select BOARD_SCACHE
+-
+ config R5000_CPU_SCACHE
+ bool
+ select BOARD_SCACHE
+Index: linux-2.6.23/arch/mips/kernel/cpu-probe.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/cpu-probe.c 2007-10-13 02:23:11.210767122 +0200
++++ linux-2.6.23/arch/mips/kernel/cpu-probe.c 2007-10-13 02:47:02.788348072 +0200
+@@ -701,6 +701,8 @@
+ break;
+ case PRID_IMP_25KF:
+ c->cputype = CPU_25KF;
++ /* Probe for L2 cache */
++ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ break;
+ case PRID_IMP_34K:
+ c->cputype = CPU_34K;
+Index: linux-2.6.23/arch/mips/mm/c-r4k.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/c-r4k.c 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/mm/c-r4k.c 2007-10-13 02:47:02.792348301 +0200
+@@ -1086,7 +1086,6 @@
+
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+-extern int mips_sc_init(void);
+
+ static void __init setup_scache(void)
+ {
+@@ -1140,29 +1139,17 @@
+ #endif
+
+ default:
+- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+- c->isa_level == MIPS_CPU_ISA_M32R2 ||
+- c->isa_level == MIPS_CPU_ISA_M64R1 ||
+- c->isa_level == MIPS_CPU_ISA_M64R2) {
+-#ifdef CONFIG_MIPS_CPU_SCACHE
+- if (mips_sc_init ()) {
+- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+- scache_size >> 10,
+- way_string[c->scache.ways], c->scache.linesz);
+- }
+-#else
+- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+-#endif
+- return;
+- }
+ sc_present = 0;
+ }
+
+ if (!sc_present)
+ return;
+
++ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++ c->isa_level == MIPS_CPU_ISA_M64R1) &&
++ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
++ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
++
+ /* compute a couple of other cache variables */
+ c->scache.waysize = scache_size / c->scache.ways;
+
+Index: linux-2.6.23/arch/mips/mm/Makefile
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/Makefile 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/mm/Makefile 2007-10-13 02:47:23.393522295 +0200
+@@ -31,6 +31,5 @@
+ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
+ obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
+ obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
+-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
+
+ EXTRA_CFLAGS += -Werror