brcm47xx: remove 2.6.25 support

SVN-Revision: 15448

23 files changed, 0 insertions, 3175 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.25/100-board_support.patch b/target/linux/brcm47xx/patches-2.6.25/100-board_support.patch
deleted file mode 100644
index b48215d..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/100-board_support.patch
+++ /dev/null
@@ -1,46 +0,0 @@
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -50,8 +50,10 @@ config BCM47XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 	select SSB
-+	select SSB_SERIAL
- 	select SSB_DRIVER_MIPS
- 	select SSB_DRIVER_EXTIF
-+	select SSB_DRIVER_PCICORE
- 	select SSB_PCICORE_HOSTMODE if PCI
- 	select GENERIC_GPIO
- 	select SYS_HAS_EARLY_PRINTK
-@@ -790,6 +792,7 @@ config CSRC_SB1250
- 
- config CFE
- 	bool
-+	# Common Firmware Environment
- 
- config DMA_COHERENT
- 	bool
---- a/include/asm-mips/bootinfo.h
-+++ b/include/asm-mips/bootinfo.h
-@@ -94,6 +94,12 @@
- #define MACH_MSP7120_FPGA       5	/* PMC-Sierra MSP7120 Emulation */
- #define MACH_MSP_OTHER        255	/* PMC-Sierra unknown board type */
- 
-+/*
-+ * Valid machtype for group Broadcom
-+ */
-+#define MACH_GROUP_BRCM		23	/* Broadcom			*/
-+#define MACH_BCM47XX		1	/* Broadcom BCM47xx		*/
-+
- #define CL_SIZE			COMMAND_LINE_SIZE
- 
- extern char *system_type;
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -2001,6 +2001,7 @@
- #define PCI_DEVICE_ID_TIGON3_5906M	0x1713
- #define PCI_DEVICE_ID_BCM4401		0x4401
- #define PCI_DEVICE_ID_BCM4401B0		0x4402
-+#define PCI_DEVICE_ID_BCM4713		0x4713
- 
- #define PCI_VENDOR_ID_TOPIC		0x151f
- #define PCI_DEVICE_ID_TOPIC_TP560	0x0000
diff --git a/target/linux/brcm47xx/patches-2.6.25/110-flash_map.patch b/target/linux/brcm47xx/patches-2.6.25/110-flash_map.patch
deleted file mode 100644
index 6d3161c..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/110-flash_map.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -337,6 +337,12 @@ config MTD_CFI_FLAGADM
- 	  Mapping for the Flaga digital module. If you don't have one, ignore
- 	  this setting.
- 
-+config MTD_BCM47XX
-+	tristate "BCM47xx flash device"
-+	depends on MIPS && MTD_CFI && BCM47XX
-+	help
-+	  Support for the flash chips on the BCM947xx board.
-+
- config MTD_WALNUT
- 	tristate "Flash device mapped on IBM 405GP Walnut"
- 	depends on MTD_JEDECPROBE && WALNUT && !PPC_MERGE
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcm
- obj-$(CONFIG_MTD_PCMCIA)	+= pcmciamtd.o
- obj-$(CONFIG_MTD_RPXLITE)	+= rpxlite.o
- obj-$(CONFIG_MTD_TQM8XXL)	+= tqm8xxl.o
-+obj-$(CONFIG_MTD_BCM47XX)	+= bcm47xx-flash.o
- obj-$(CONFIG_MTD_SA1100)	+= sa1100-flash.o
- obj-$(CONFIG_MTD_IPAQ)		+= ipaq-flash.o
- obj-$(CONFIG_MTD_SBC_GXX)	+= sbc_gxx.o
diff --git a/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch b/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
deleted file mode 100644
index 941b649..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
+++ /dev/null
@@ -1,89 +0,0 @@
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -228,7 +228,6 @@ config MIPS_MALTA
- 	select I8259
- 	select MIPS_BOARDS_GEN
- 	select MIPS_BONITO64
--	select MIPS_CPU_SCACHE
- 	select PCI_GT64XXX_PCI0
- 	select MIPS_MSC
- 	select SWAP_IO_SPACE
-@@ -1421,13 +1420,6 @@ config IP22_CPU_SCACHE
- 	bool
- 	select BOARD_SCACHE
- 
--#
--# Support for a MIPS32 / MIPS64 style S-caches
--#
--config MIPS_CPU_SCACHE
--	bool
--	select BOARD_SCACHE
--
- config R5000_CPU_SCACHE
- 	bool
- 	select BOARD_SCACHE
---- a/arch/mips/kernel/cpu-probe.c
-+++ b/arch/mips/kernel/cpu-probe.c
-@@ -704,6 +704,8 @@ static inline void cpu_probe_mips(struct
- 		break;
- 	case PRID_IMP_25KF:
- 		c->cputype = CPU_25KF;
-+		/* Probe for L2 cache */
-+		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
- 		break;
- 	case PRID_IMP_34K:
- 		c->cputype = CPU_34K;
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -1103,7 +1103,6 @@ static void __init loongson2_sc_init(voi
- 
- extern int r5k_sc_init(void);
- extern int rm7k_sc_init(void);
--extern int mips_sc_init(void);
- 
- static void __cpuinit setup_scache(void)
- {
-@@ -1157,29 +1156,17 @@ static void __cpuinit setup_scache(void)
- #endif
- 
- 	default:
--		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
--		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
--		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
--		    c->isa_level == MIPS_CPU_ISA_M64R2) {
--#ifdef CONFIG_MIPS_CPU_SCACHE
--			if (mips_sc_init ()) {
--				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
--				printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
--				       scache_size >> 10,
--				       way_string[c->scache.ways], c->scache.linesz);
--			}
--#else
--			if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
--				panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
--#endif
--			return;
--		}
- 		sc_present = 0;
- 	}
- 
- 	if (!sc_present)
- 		return;
- 
-+	if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
-+	     c->isa_level == MIPS_CPU_ISA_M64R1) &&
-+	    !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
-+		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-+
- 	/* compute a couple of other cache variables */
- 	c->scache.waysize = scache_size / c->scache.ways;
- 
---- a/arch/mips/mm/Makefile
-+++ b/arch/mips/mm/Makefile
-@@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_VR41XX)	+= c-r4k.o cex-
- obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
- obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
- obj-$(CONFIG_RM7000_CPU_SCACHE)	+= sc-rm7k.o
--obj-$(CONFIG_MIPS_CPU_SCACHE)	+= sc-mips.o
- 
- EXTRA_CFLAGS += -Werror
diff --git a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
deleted file mode 100644
index 58dafe5..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
+++ /dev/null
@@ -1,365 +0,0 @@
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
- NESTED(except_vec3_generic, 0, sp)
- 	.set	push
- 	.set	noat
-+#ifdef CONFIG_BCM47XX
-+	nop
-+	nop
-+#endif
- #if R5432_CP0_INTERRUPT_WAR
- 	mfc0	k0, CP0_INDEX
- #endif
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -33,6 +33,9 @@
- #include <asm/cacheflush.h> /* for run_uncached() */
- 
- 
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
-  * Special Variant of smp_call_function for use by cache functions:
-  *
-@@ -97,6 +100,9 @@ static void __cpuinit r4k_blast_dcache_p
- {
- 	unsigned long  dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page = blast_dcache_page;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_page = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -111,6 +117,9 @@ static void __cpuinit r4k_blast_dcache_p
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_page_indexed = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -125,6 +134,9 @@ static void __cpuinit r4k_blast_dcache_s
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache = blast_dcache;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -630,6 +642,8 @@ static void local_r4k_flush_cache_sigtra
- 	unsigned long addr = (unsigned long) arg;
- 
- 	R4600_HIT_CACHEOP_WAR_IMPL;
-+	BCM4710_PROTECTED_FILL_TLB(addr);
-+	BCM4710_PROTECTED_FILL_TLB(addr + 4);
- 	if (dc_lsize)
- 		protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- 	if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1215,6 +1229,17 @@ static void __cpuinit coherency_setup(vo
- 	 * silly idea of putting something else there ...
- 	 */
- 	switch (current_cpu_type()) {
-+	case CPU_BCM3302:
-+		{
-+			u32 cm;
-+			cm = read_c0_diag();
-+			/* Enable icache */
-+			cm |= (1 << 31);
-+			/* Enable dcache */
-+			cm |= (1 << 30);
-+			write_c0_diag(cm);
-+		}
-+		break;
- 	case CPU_R4000PC:
- 	case CPU_R4000SC:
- 	case CPU_R4000MC:
-@@ -1254,6 +1279,15 @@ void __cpuinit r4k_cache_init(void)
- 		break;
- 	}
- 
-+	/* Check if special workarounds are required */
-+#ifdef CONFIG_BCM47XX
-+	if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
-+		printk("Enabling BCM4710A0 cache workarounds.\n");
-+		bcm4710 = 1;
-+	} else
-+#endif
-+		bcm4710 = 0;
-+
- 	probe_pcache();
- 	setup_scache();
- 
-@@ -1303,5 +1337,13 @@ void __cpuinit r4k_cache_init(void)
- 	build_clear_page();
- 	build_copy_page();
- 	local_r4k___flush_cache_all(NULL);
-+#ifdef CONFIG_BCM47XX
-+	{
-+		static void (*_coherency_setup)(void);
-+		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+		_coherency_setup();
-+	}
-+#else
- 	coherency_setup();
-+#endif
- }
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -677,6 +677,9 @@ static void __cpuinit build_r4000_tlb_re
- 		/* No need for uasm_i_nop */
- 	}
- 
-+#ifdef CONFIG_BCM47XX
-+	uasm_i_nop(&p);
-+#endif
- #ifdef CONFIG_64BIT
- 	build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-@@ -1084,6 +1087,9 @@ build_r4000_tlbchange_handler_head(u32 *
- 				   struct uasm_reloc **r, unsigned int pte,
- 				   unsigned int ptr)
- {
-+#ifdef CONFIG_BCM47XX
-+	uasm_i_nop(p);
-+#endif
- #ifdef CONFIG_64BIT
- 	build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
- #else
---- a/include/asm-mips/r4kcache.h
-+++ b/include/asm-mips/r4kcache.h
-@@ -17,6 +17,20 @@
- #include <asm/cpu-features.h>
- #include <asm/mipsmtregs.h>
- 
-+#ifdef CONFIG_BCM47XX
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
-  * This macro return a properly sign-extended address suitable as base address
-  * for indexed cache operations.  Two issues here:
-@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Index_Writeback_Inv_D, addr);
- 	__dflush_epilogue
- }
-@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
- static inline void flush_dcache_line(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Writeback_Inv_D, addr);
- 	__dflush_epilogue
- }
-@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- 	__dflush_prologue
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Invalidate_D, addr);
- 	__dflush_epilogue
- }
-@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
-  */
- static inline void protected_flush_icache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	protected_cache_op(Hit_Invalidate_I, addr);
- }
- 
-@@ -219,6 +237,7 @@ static inline void protected_flush_icach
-  */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
- 
-@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
- 		: "r" (base),						\
- 		  "i" (op));
- 
-+static inline void blast_dcache(void)
-+{
-+	unsigned long start = KSEG0;
-+	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+	unsigned long end = (start + dcache_size);
-+
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Index_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+
-+	BCM4710_FILL_TLB(start);
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Hit_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+	unsigned long ws_end = current_cpu_data.dcache.ways <<
-+	                       current_cpu_data.dcache.waybit;
-+	unsigned long ws, addr;
-+	for (ws = 0; ws < ws_end; ws += ws_inc) {
-+		start = page + ws;
-+		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+			BCM4710_DUMMY_RREG();
-+			cache_op(Index_Writeback_Inv_D, addr);
-+		}
-+	}
-+}
-+
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
- static inline void blast_##pfx##cache##lsize(void)			\
- {									\
- 	unsigned long start = INDEX_BASE;				\
-@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
- 									\
- 	__##pfx##flush_prologue						\
- 									\
-+	war								\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
- 		for (addr = start; addr < end; addr += lsize * 32)	\
- 			cache##lsize##_unroll32(addr|ws, indexop);	\
-@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
- 									\
- 	__##pfx##flush_prologue						\
- 									\
-+	war								\
- 	do {								\
- 		cache##lsize##_unroll32(start, hitop);			\
- 		start += lsize * 32;					\
-@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
- 	                       current_cpu_data.desc.waybit;		\
- 	unsigned long ws, addr;						\
- 									\
-+	war								\
-+									\
- 	__##pfx##flush_prologue						\
- 									\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
-@@ -393,35 +460,37 @@ static inline void blast_##pfx##cache##l
- 	__##pfx##flush_epilogue						\
- }
- 
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
- 
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
- static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
- 						    unsigned long end)	\
- {									\
- 	unsigned long lsize = cpu_##desc##_line_size();			\
- 	unsigned long addr = start & ~(lsize - 1);			\
- 	unsigned long aend = (end - 1) & ~(lsize - 1);			\
-+	war								\
- 									\
- 	__##pfx##flush_prologue						\
- 									\
- 	while (1) {							\
-+		war2						\
- 		prot##cache_op(hitop, addr);				\
- 		if (addr == aend)					\
- 			break;						\
-@@ -431,13 +500,13 @@ static inline void prot##blast_##pfx##ca
- 	__##pfx##flush_epilogue						\
- }
- 
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
- 
- #endif /* _ASM_R4KCACHE_H */
---- a/include/asm-mips/stackframe.h
-+++ b/include/asm-mips/stackframe.h
-@@ -359,6 +359,10 @@
- 		.macro	RESTORE_SP_AND_RET
- 		LONG_L	sp, PT_R29(sp)
- 		.set	mips3
-+#ifdef CONFIG_BCM47XX
-+		nop
-+		nop
-+#endif
- 		eret
- 		.set	mips0
- 		.endm
diff --git a/target/linux/brcm47xx/patches-2.6.25/160-kmap_coherent.patch b/target/linux/brcm47xx/patches-2.6.25/160-kmap_coherent.patch
deleted file mode 100644
index 5fe38aa..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/160-kmap_coherent.patch
+++ /dev/null
@@ -1,77 +0,0 @@
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -211,7 +211,7 @@ void copy_user_highpage(struct page *to,
- 	void *vfrom, *vto;
- 
- 	vto = kmap_atomic(to, KM_USER1);
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapped(from) && !Page_dcache_dirty(from)) {
- 		vfrom = kmap_coherent(from, vaddr);
- 		copy_page(vto, vfrom);
-@@ -235,7 +235,7 @@ void copy_to_user_page(struct vm_area_st
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapped(page) && !Page_dcache_dirty(page)) {
- 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(vto, src, len);
-@@ -255,7 +255,7 @@ void copy_from_user_page(struct vm_area_
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapped(page) && !Page_dcache_dirty(page)) {
- 		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(dst, vfrom, len);
---- /dev/null
-+++ b/include/asm-mips/mach-bcm47xx/cpu-feature-overrides.h
-@@ -0,0 +1,13 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
-+ */
-+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
-+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
-+
-+#define cpu_use_kmap_coherent	0
-+
-+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
---- a/include/asm-mips/cpu-features.h
-+++ b/include/asm-mips/cpu-features.h
-@@ -101,6 +101,9 @@
- #ifndef cpu_has_pindexed_dcache
- #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
- #endif
-+#ifndef cpu_use_kmap_coherent
-+#define cpu_use_kmap_coherent 1
-+#endif
- 
- /*
-  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -484,7 +484,7 @@ static inline void local_r4k_flush_cache
- 		 * Use kmap_coherent or kmap_atomic to do flushes for
- 		 * another ASID than the current one.
- 		 */
--		if (cpu_has_dc_aliases)
-+		if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
- 			vaddr = kmap_coherent(page, addr);
- 		else
- 			vaddr = kmap_atomic(page, KM_USER0);
-@@ -505,7 +505,7 @@ static inline void local_r4k_flush_cache
- 	}
- 
- 	if (vaddr) {
--		if (cpu_has_dc_aliases)
-+		if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
- 			kunmap_coherent();
- 		else
- 			kunmap_atomic(vaddr, KM_USER0);
diff --git a/target/linux/brcm47xx/patches-2.6.25/210-b44_phy_fix.patch b/target/linux/brcm47xx/patches-2.6.25/210-b44_phy_fix.patch
deleted file mode 100644
index 6669fba..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/210-b44_phy_fix.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/net/b44.c
-+++ b/drivers/net/b44.c
-@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
- 		}
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
-@@ -384,7 +384,7 @@ static void b44_set_flow_ctrl(struct b44
- 	__b44_set_flow_ctrl(bp, pause_enab);
- }
- 
--#ifdef SSB_DRIVER_MIPS
-+#ifdef CONFIG_SSB_DRIVER_MIPS
- extern char *nvram_get(char *name);
- static void b44_wap54g10_workaround(struct b44 *bp)
- {
-@@ -2211,6 +2211,10 @@ static int __devinit b44_init_one(struct
- 	 */
- 	b44_chip_reset(bp, B44_CHIP_RESET_FULL);
- 
-+	/* do a phy reset to test if there is an active phy */
-+	if (b44_phy_reset(bp) < 0)
-+		bp->phy_addr = B44_PHY_ADDR_NO_PHY;
-+
- 	printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
- 	       dev->name, print_mac(mac, dev->dev_addr));
- 
diff --git a/target/linux/brcm47xx/patches-2.6.25/211-b44_bcm4713_phy.patch b/target/linux/brcm47xx/patches-2.6.25/211-b44_bcm4713_phy.patch
deleted file mode 100644
index 13f93bd..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/211-b44_bcm4713_phy.patch
+++ /dev/null
@@ -1,14 +0,0 @@
---- a/drivers/net/b44.c
-+++ b/drivers/net/b44.c
-@@ -2094,6 +2094,11 @@ static int __devinit b44_get_invariants(
- 		return -EINVAL;
- 	}
- 
-+	if (bp->sdev->id.coreid == 0x806 && bp->sdev->id.revision == 0x0) {
-+		bp->phy_addr = B44_PHY_ADDR_NO_PHY;
-+		bp->dma_offset = 0;
-+	}
-+
- 	memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
- 
- 	bp->imask = IMASK_DEF;
diff --git a/target/linux/brcm47xx/patches-2.6.25/212-b44_alignment_fix.patch b/target/linux/brcm47xx/patches-2.6.25/212-b44_alignment_fix.patch
deleted file mode 100644
index d65c37e..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/212-b44_alignment_fix.patch
+++ /dev/null
@@ -1,48 +0,0 @@
---- a/drivers/net/b44.c
-+++ b/drivers/net/b44.c
-@@ -73,8 +73,8 @@
- 	  (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
- #define NEXT_TX(N)		(((N) + 1) & (B44_TX_RING_SIZE - 1))
- 
--#define RX_PKT_OFFSET		30
--#define RX_PKT_BUF_SZ		(1536 + RX_PKT_OFFSET + 64)
-+#define RX_PKT_OFFSET		(RX_HEADER_LEN + 2)
-+#define RX_PKT_BUF_SZ		(1536 + RX_PKT_OFFSET)
- 
- /* minimum number of free TX descriptors required to wake up TX process */
- #define B44_TX_WAKEUP_THRESH		(B44_TX_RING_SIZE / 4)
-@@ -682,7 +682,6 @@ static int b44_alloc_rx_skb(struct b44 *
- 	}
- 
- 	rh = (struct rx_header *) skb->data;
--	skb_reserve(skb, RX_PKT_OFFSET);
- 
- 	rh->len = 0;
- 	rh->flags = 0;
-@@ -693,13 +692,13 @@ static int b44_alloc_rx_skb(struct b44 *
- 	if (src_map != NULL)
- 		src_map->skb = NULL;
- 
--	ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
-+	ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
- 	if (dest_idx == (B44_RX_RING_SIZE - 1))
- 		ctrl |= DESC_CTRL_EOT;
- 
- 	dp = &bp->rx_ring[dest_idx];
- 	dp->ctrl = cpu_to_le32(ctrl);
--	dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
-+	dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
- 
- 	if (bp->flags & B44_FLAG_RX_RING_HACK)
- 		b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
-@@ -809,8 +808,8 @@ static int b44_rx(struct b44 *bp, int bu
- 			dma_unmap_single(bp->sdev->dma_dev, map,
- 					 skb_size, DMA_FROM_DEVICE);
- 			/* Leave out rx_header */
--                	skb_put(skb, len + RX_PKT_OFFSET);
--            	        skb_pull(skb, RX_PKT_OFFSET);
-+			skb_put(skb, len + RX_PKT_OFFSET);
-+			skb_pull(skb, RX_PKT_OFFSET);
- 		} else {
- 			struct sk_buff *copy_skb;
- 
diff --git a/target/linux/brcm47xx/patches-2.6.25/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.25/220-bcm5354.patch
deleted file mode 100644
index 6a4341f..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/220-bcm5354.patch
+++ /dev/null
@@ -1,42 +0,0 @@
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -270,6 +270,8 @@ void ssb_chipco_resume(struct ssb_chipco
- void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
-                              u32 *plltype, u32 *n, u32 *m)
- {
-+	if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
-+		return;
- 	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
- 	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
- 	switch (*plltype) {
-@@ -293,6 +295,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
- void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
- 				 u32 *plltype, u32 *n, u32 *m)
- {
-+	if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
-+		return;
- 	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
- 	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
- 	switch (*plltype) {
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -161,6 +161,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
- 
- 	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
- 		rate = 200000000;
-+	} else if (bus->chip_id == 0x5354) {
-+		rate = 240000000;
- 	} else {
- 		rate = ssb_calc_clock_rate(pll_type, n, m);
- 	}
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -867,6 +867,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
- 
- 	if (bus->chip_id == 0x5365) {
- 		rate = 100000000;
-+	} else if (bus->chip_id == 0x5354) {
-+		rate = 120000000;
- 	} else {
- 		rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
- 		if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
diff --git a/target/linux/brcm47xx/patches-2.6.25/250-ohci-ssb-usb2.patch b/target/linux/brcm47xx/patches-2.6.25/250-ohci-ssb-usb2.patch
deleted file mode 100644
index 856651b..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/250-ohci-ssb-usb2.patch
+++ /dev/null
@@ -1,72 +0,0 @@
---- a/drivers/usb/host/ohci-ssb.c
-+++ b/drivers/usb/host/ohci-ssb.c
-@@ -142,10 +142,59 @@ static int ssb_ohci_attach(struct ssb_de
- 	int err = -ENOMEM;
- 	u32 tmp, flags = 0;
- 
--	if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
-+	/*
-+	 * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
-+	 *
-+	 * The USB core requires a special bit to be set during core
-+	 * reset to enable host (OHCI) mode. Resetting the SB core in
-+	 * pcibios_enable_device() is a hack for compatibility with
-+	 * vanilla usb-ohci so that it does not have to know about
-+	 * SB. A driver that wants to use the USB core in device mode
-+	 * should know about SB and should reset the bit back to 0
-+	 * after calling pcibios_enable_device().
-+	 */
-+
-+	if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
- 		flags |= SSB_OHCI_TMSLOW_HOSTMODE;
-+		ssb_device_enable(dev, flags);
-+	}
-+
-+	/*
-+	 * USB 2.0 special considerations:
-+	 *
-+	 * 1. Since the core supports both OHCI and EHCI functions, it must
-+	 *    only be reset once.
-+	 * 
-+	 * 2. In addition to the standard SB reset sequence, the Host Control
-+	 *    Register must be programmed to bring the USB core and various
-+	 *    phy components out of reset. 
-+	 */
-+
-+	else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
-+#warning FIX ME need test for core being up & exit
-+		ssb_device_enable(dev, 0);
-+		ssb_write32(dev, 0x200, 0x7ff);
-+		udelay(1);
-+		if (dev->id.revision == 1) { // bug in rev 1
-+
-+			/* Change Flush control reg */
-+			tmp = ssb_read32(dev, 0x400);
-+			tmp &= ~8;
-+			ssb_write32(dev, 0x400, tmp);
-+			tmp = ssb_read32(dev, 0x400);
-+			printk("USB20H fcr: 0x%0x\n", tmp);
-+
-+			/* Change Shim control reg */
-+			tmp = ssb_read32(dev, 0x304);
-+			tmp &= ~0x100;
-+			ssb_write32(dev, 0x304, tmp);
-+			tmp = ssb_read32(dev, 0x304);
-+			printk("USB20H shim: 0x%0x\n", tmp);
-+		}
-+	}
-+	else
-+		ssb_device_enable(dev, 0);
- 
--	ssb_device_enable(dev, flags);
- 
- 	hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
- 			dev->dev->bus_id);
-@@ -236,6 +285,7 @@ static int ssb_ohci_resume(struct ssb_de
- static const struct ssb_device_id ssb_ohci_table[] = {
- 	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
- 	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
-+	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
- 	SSB_DEVTABLE_END
- };
- MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
diff --git a/target/linux/brcm47xx/patches-2.6.25/260-ohci-set-dma-mask.patch b/target/linux/brcm47xx/patches-2.6.25/260-ohci-set-dma-mask.patch
deleted file mode 100644
index afeec9c..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/260-ohci-set-dma-mask.patch
+++ /dev/null
@@ -1,14 +0,0 @@
---- a/drivers/usb/host/ohci-ssb.c
-+++ b/drivers/usb/host/ohci-ssb.c
-@@ -195,6 +195,11 @@ static int ssb_ohci_attach(struct ssb_de
- 	else
- 		ssb_device_enable(dev, 0);
- 
-+ /*
-+  * Set dma mask - 32 bit mask is just an assumption
-+  */
-+ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
-+   return -EOPNOTSUPP;
- 
- 	hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
- 			dev->dev->bus_id);
diff --git a/target/linux/brcm47xx/patches-2.6.25/300-fork_cacheflush.patch b/target/linux/brcm47xx/patches-2.6.25/300-fork_cacheflush.patch
deleted file mode 100644
index f5b5d77..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/300-fork_cacheflush.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/include/asm-mips/cacheflush.h
-+++ b/include/asm-mips/cacheflush.h
-@@ -32,7 +32,7 @@
- extern void (*flush_cache_all)(void);
- extern void (*__flush_cache_all)(void);
- extern void (*flush_cache_mm)(struct mm_struct *mm);
--#define flush_cache_dup_mm(mm)	do { (void) (mm); } while (0)
-+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
- extern void (*flush_cache_range)(struct vm_area_struct *vma,
- 	unsigned long start, unsigned long end);
- extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
diff --git a/target/linux/brcm47xx/patches-2.6.25/310-no_highpage.patch b/target/linux/brcm47xx/patches-2.6.25/310-no_highpage.patch
deleted file mode 100644
index 505e8aa..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/310-no_highpage.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -205,32 +205,6 @@ void kunmap_coherent(void)
- 	preempt_check_resched();
- }
- 
--void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma)
--{
--	void *vfrom, *vto;
--
--	vto = kmap_atomic(to, KM_USER1);
--	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
--	    page_mapped(from) && !Page_dcache_dirty(from)) {
--		vfrom = kmap_coherent(from, vaddr);
--		copy_page(vto, vfrom);
--		kunmap_coherent();
--	} else {
--		vfrom = kmap_atomic(from, KM_USER0);
--		copy_page(vto, vfrom);
--		kunmap_atomic(vfrom, KM_USER0);
--	}
--	if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
--	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
--		flush_data_cache_page((unsigned long)vto);
--	kunmap_atomic(vto, KM_USER1);
--	/* Make sure this page is cleared on other CPU's too before using it */
--	smp_wmb();
--}
--
--EXPORT_SYMBOL(copy_user_highpage);
--
- void copy_to_user_page(struct vm_area_struct *vma,
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
---- a/include/asm-mips/page.h
-+++ b/include/asm-mips/page.h
-@@ -32,6 +32,7 @@
- #ifndef __ASSEMBLY__
- 
- #include <linux/pfn.h>
-+#include <asm/cpu-features.h>
- #include <asm/io.h>
- 
- /*
-@@ -64,13 +65,16 @@ static inline void clear_user_page(void 
- 		flush_data_cache_page((unsigned long)addr);
- }
- 
--extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
--	struct page *to);
--struct vm_area_struct;
--extern void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma);
-+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-+	struct page *to)
-+{
-+	extern void (*flush_data_cache_page)(unsigned long addr);
- 
--#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-+	copy_page(vto, vfrom);
-+	if (!cpu_has_ic_fills_f_dc ||
-+	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-+		flush_data_cache_page((unsigned long)vto);
-+}
- 
- /*
-  * These are used to make use of C type-checking..
diff --git a/target/linux/brcm47xx/patches-2.6.25/400-arch-bcm47xx.patch b/target/linux/brcm47xx/patches-2.6.25/400-arch-bcm47xx.patch
deleted file mode 100644
index 7153871..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/400-arch-bcm47xx.patch
+++ /dev/null
@@ -1,372 +0,0 @@
---- a/arch/mips/bcm47xx/irq.c
-+++ b/arch/mips/bcm47xx/irq.c
-@@ -1,5 +1,6 @@
- /*
-  *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
-+ *  Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
-  *
-  *  This program is free software; you can redistribute  it and/or modify it
-  *  under  the terms of  the GNU General  Public License as published by the
-@@ -23,10 +24,19 @@
-  */
- 
- #include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/irq.h>
-+#include <linux/pci.h>
-+#include <linux/ssb/ssb.h>
-+
- #include <asm/irq_cpu.h>
- 
-+
-+extern struct ssb_bus ssb_bcm47xx;
-+
-+
- void plat_irq_dispatch(void)
- {
- 	u32 cause;
-@@ -53,3 +63,19 @@ void __init arch_init_irq(void)
- {
- 	mips_cpu_irq_init();
- }
-+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	int res;
-+
-+	res = ssb_pcibios_map_irq(dev, slot, pin);
-+	if (res < 0) {
-+		printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
-+		       dev->dev.bus_id);
-+		return 0;
-+	}
-+	/* IRQ-0 and IRQ-1 are software interrupts. */
-+	WARN_ON((res == 0) || (res == 1));
-+
-+	return res;
-+}
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -2,7 +2,7 @@
-  *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
-  *  Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
-  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-- *  Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
-+ *  Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
-  *
-  *  This program is free software; you can redistribute  it and/or modify it
-  *  under  the terms of  the GNU General  Public License as published by the
-@@ -25,23 +25,52 @@
-  *  675 Mass Ave, Cambridge, MA 02139, USA.
-  */
- 
-+#include <linux/init.h>
- #include <linux/types.h>
--#include <linux/ssb/ssb.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_reg.h>
-+#include <linux/serial_8250.h>
- #include <asm/bootinfo.h>
--#include <asm/reboot.h>
- #include <asm/time.h>
--#include <bcm47xx.h>
-+#include <asm/reboot.h>
- #include <asm/fw/cfe/cfe_api.h>
-+#include <linux/pm.h>
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_embedded.h>
-+
-+#include "include/nvram.h"
- 
- struct ssb_bus ssb_bcm47xx;
- EXPORT_SYMBOL(ssb_bcm47xx);
- 
-+extern void bcm47xx_pci_init(void);
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	int err;
-+
-+	err = ssb_pcibios_plat_dev_init(dev);
-+	if (err) {
-+		printk(KERN_ALERT "PCI: Failed to init device %s\n",
-+		       pci_name(dev));
-+	}
-+
-+	return err;
-+}
-+
- static void bcm47xx_machine_restart(char *command)
- {
- 	printk(KERN_ALERT "Please stand by while rebooting the system...\n");
- 	local_irq_disable();
-+	/* CFE has a reboot callback, but that does not work.
-+	 * Oopses with: Reserved instruction in kernel code.
-+	 */
-+
- 	/* Set the watchdog timer to reset immediately */
--	ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
-+	if (ssb_watchdog_timer_set(&ssb_bcm47xx, 1))
-+		printk(KERN_EMERG "SSB watchdog-triggered reboot failed!\n");
- 	while (1)
- 		cpu_relax();
- }
-@@ -50,12 +79,13 @@ static void bcm47xx_machine_halt(void)
- {
- 	/* Disable interrupts and watchdog and spin forever */
- 	local_irq_disable();
--	ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
-+	if (ssb_watchdog_timer_set(&ssb_bcm47xx, 0))
-+		printk(KERN_EMERG "Failed to disable SSB watchdog!\n");
- 	while (1)
- 		cpu_relax();
- }
- 
--static void str2eaddr(char *str, char *dest)
-+static void e_aton(char *str, char *dest)
- {
- 	int i = 0;
- 
-@@ -72,52 +102,141 @@ static void str2eaddr(char *str, char *d
- 	}
- }
- 
--static int bcm47xx_get_invariants(struct ssb_bus *bus,
--				   struct ssb_init_invariants *iv)
-+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
- {
--	char buf[100];
-+	char *s;
- 
--	/* Fill boardinfo structure */
--	memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
-+	memset(sprom, 0xFF, sizeof(struct ssb_sprom));
- 
--	if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
--		iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
--	if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
--		iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
--	if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
--		iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
--
--	/* Fill sprom structure */
--	memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
--	iv->sprom.revision = 3;
--
--	if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
--		str2eaddr(buf, iv->sprom.et0mac);
--	if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
--		str2eaddr(buf, iv->sprom.et1mac);
--	if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
--		iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
--	if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
--		iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
--	if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
--		iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
--	if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
--		iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
-+	sprom->revision = 1;
-+	if ((s = nvram_get("il0macaddr")))
-+		e_aton(s, sprom->il0mac);
-+	if ((s = nvram_get("et0macaddr")))
-+		e_aton(s, sprom->et0mac);
-+	if ((s = nvram_get("et1macaddr")))
-+		e_aton(s, sprom->et1mac);
-+	if ((s = nvram_get("et0phyaddr")))
-+		sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("et1phyaddr")))
-+		sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("et0mdcport")))
-+		sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
-+	if ((s = nvram_get("et1mdcport")))
-+		sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
-+	if ((s = nvram_get("pa0b0")))
-+		sprom->pa0b0 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa0b1")))
-+		sprom->pa0b1 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa0b2")))
-+		sprom->pa0b2 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa1b0")))
-+		sprom->pa1b0 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa1b1")))
-+		sprom->pa1b1 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa1b2")))
-+		sprom->pa1b2 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("wl0gpio0")))
-+		sprom->gpio0 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("wl0gpio1")))
-+		sprom->gpio1 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("wl0gpio2")))
-+		sprom->gpio2 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("wl0gpio3")))
-+		sprom->gpio3 = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa0maxpwr")))
-+		sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa1maxpwr")))
-+		sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa0itssit")))
-+		sprom->itssi_bg = simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("pa1itssit")))
-+		sprom->itssi_a = simple_strtoul(s, NULL, 0);
-+	sprom->boardflags_lo = 0;
-+	if ((s = nvram_get("boardflags")))
-+		sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
-+	sprom->boardflags_hi = 0;
-+	if ((s = nvram_get("boardflags2")))
-+		sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
-+}
-+
-+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
-+{
-+	char *s;
-+
-+	iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
-+	if ((s = nvram_get("boardtype")))
-+		iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("boardrev")))
-+		iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
-+
-+	bcm47xx_fill_sprom(&iv->sprom);
-+
-+	if ((s = nvram_get("cardbus")))
-+		iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
- 
- 	return 0;
- }
- 
- void __init plat_mem_setup(void)
- {
--	int err;
-+	int i, err;
-+	char *s;
-+	struct ssb_mipscore *mcore;
-+
-+	err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
-+	if (err) {
-+		const char *msg = "Failed to initialize SSB bus (err %d)\n";
-+		printk(msg, err); /* Make sure the message gets out of the box. */
-+		panic(msg, err);
-+	}
-+	mcore = &ssb_bcm47xx.mipscore;
-+
-+	s = nvram_get("kernel_args");
-+	if (s && !strncmp(s, "console=ttyS1", 13)) {
-+		struct ssb_serial_port port;
-+
-+		printk("Swapping serial ports!\n");
-+		/* swap serial ports */
-+		memcpy(&port, &mcore->serial_ports[0], sizeof(port));
-+		memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
-+		memcpy(&mcore->serial_ports[1], &port, sizeof(port));
-+	}
- 
--	err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
--				      bcm47xx_get_invariants);
--	if (err)
--		panic("Failed to initialize SSB bus (err %d)\n", err);
-+	for (i = 0; i < mcore->nr_serial_ports; i++) {
-+		struct ssb_serial_port *port = &(mcore->serial_ports[i]);
-+		struct uart_port s;
-+
-+		memset(&s, 0, sizeof(s));
-+		s.line = i;
-+		s.membase = port->regs;
-+		s.irq = port->irq + 2;
-+		s.uartclk = port->baud_base;
-+		s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
-+		s.iotype = SERIAL_IO_MEM;
-+		s.regshift = port->reg_shift;
-+
-+		early_serial_setup(&s);
-+	}
-+	printk("Serial init done.\n");
- 
- 	_machine_restart = bcm47xx_machine_restart;
- 	_machine_halt = bcm47xx_machine_halt;
- 	pm_power_off = bcm47xx_machine_halt;
- }
- 
-+static int __init bcm47xx_register_gpiodev(void)
-+{
-+	static struct resource res = {
-+		.start = 0xFFFFFFFF,
-+	};
-+	struct platform_device *pdev;
-+
-+	pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
-+	if (!pdev) {
-+		printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+device_initcall(bcm47xx_register_gpiodev);
---- a/arch/mips/bcm47xx/time.c
-+++ b/arch/mips/bcm47xx/time.c
-@@ -22,11 +22,17 @@
-  *  675 Mass Ave, Cambridge, MA 02139, USA.
-  */
- 
--
- #include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/serial_reg.h>
-+#include <linux/interrupt.h>
- #include <linux/ssb/ssb.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
- #include <asm/time.h>
--#include <bcm47xx.h>
-+
-+extern struct ssb_bus ssb_bcm47xx;
- 
- void __init plat_time_init(void)
- {
---- a/arch/mips/bcm47xx/nvram.c
-+++ b/arch/mips/bcm47xx/nvram.c
-@@ -24,10 +24,10 @@
- #include <asm/io.h>
- #include <asm/uaccess.h>
- 
--#include <nvram.h>
-+#include "include/nvram.h"
- 
- #define MB * 1048576
--extern struct ssb_bus ssb;
-+extern struct ssb_bus ssb_bcm47xx;
- 
- static char nvram_buf[NVRAM_SPACE];
- static int cfe_env;
-@@ -36,7 +36,7 @@ extern char *cfe_env_get(char *nv_buf, c
- /* Probe for NVRAM header */
- static void __init early_nvram_init(void)
- {
--	struct ssb_mipscore *mcore = &ssb.mipscore;
-+	struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
- 	struct nvram_header *header;
- 	int i;
- 	u32 base, lim, off;
---- a/arch/mips/bcm47xx/Makefile
-+++ b/arch/mips/bcm47xx/Makefile
-@@ -3,4 +3,4 @@
- # under Linux.
- #
- 
--obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
-+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -54,6 +54,7 @@ config BCM47XX
- 	select SSB_DRIVER_MIPS
- 	select SSB_DRIVER_EXTIF
- 	select SSB_DRIVER_PCICORE
-+	select SSB_B43_PCI_BRIDGE
- 	select SSB_PCICORE_HOSTMODE if PCI
- 	select GENERIC_GPIO
- 	select SYS_HAS_EARLY_PRINTK
diff --git a/target/linux/brcm47xx/patches-2.6.25/500-lzma_initramfs.patch b/target/linux/brcm47xx/patches-2.6.25/500-lzma_initramfs.patch
deleted file mode 100644
index 59f4c1f..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/500-lzma_initramfs.patch
+++ /dev/null
@@ -1,117 +0,0 @@
---- a/scripts/gen_initramfs_list.sh
-+++ b/scripts/gen_initramfs_list.sh
-@@ -287,7 +287,7 @@ if [ ! -z ${output_file} ]; then
- 	if [ "${is_cpio_compressed}" = "compressed" ]; then
- 		cat ${cpio_tfile} > ${output_file}
- 	else
--		cat ${cpio_tfile} | gzip -f -9 - > ${output_file}
-+		lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file}
- 	fi
- 	[ -z ${cpio_file} ] && rm ${cpio_tfile}
- fi
---- a/init/initramfs.c
-+++ b/init/initramfs.c
-@@ -441,6 +441,69 @@ static void __init flush_window(void)
- 	outcnt = 0;
- }
- 
-+#include <linux/LzmaDecode.h>
-+static int __init lzma_unzip(void)
-+{
-+	unsigned int i;  /* temp value */
-+	unsigned int lc; /* literal context bits */
-+	unsigned int lp; /* literal pos state bits */
-+	unsigned int pb; /* pos state bits */
-+	unsigned int osize; /* uncompressed size */
-+	unsigned char *workspace;
-+	unsigned char* outputbuffer;
-+	unsigned int outsizeProcessed = 0;
-+	int workspace_size;
-+	int res;
-+
-+	// lzma args
-+	i = get_byte();
-+	lc = i % 9, i = i / 9;
-+	lp = i % 5, pb = i / 5;
-+
-+	// skip dictionary size
-+	for (i = 0; i < 4; i++)
-+		get_byte();
-+
-+	/* read the lower half of uncompressed size in the header */
-+	osize = ((unsigned int)get_byte()) +
-+		((unsigned int)get_byte() << 8) +
-+		((unsigned int)get_byte() << 16) +
-+		((unsigned int)get_byte() << 24);
-+
-+	/* skip rest of the header (upper half of uncompressed size) */
-+	for (i = 0; i < 4; i++)
-+		get_byte();
-+
-+	workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100;
-+	printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n",
-+	lc,lp,pb,osize);
-+	outputbuffer = kmalloc(osize, GFP_KERNEL);
-+	if (outputbuffer == 0) {
-+		printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n");
-+		return -1;
-+	}
-+
-+	workspace = kmalloc(workspace_size, GFP_KERNEL);
-+	if (workspace == NULL) {
-+		printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n");
-+		return -1;
-+	}
-+
-+	res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed);
-+	if( res != 0 ) {
-+		panic( KERN_ERR "initramfs: Lzma decode failure\n");
-+		return -1;
-+	}
-+
-+	flush_buffer(outputbuffer, outsizeProcessed);
-+	inptr = insize;
-+
-+	kfree(outputbuffer);
-+	kfree(workspace);
-+	state = Reset;
-+	return 0;
-+}
-+
- static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only)
- {
- 	int written;
-@@ -475,12 +538,28 @@ static char * __init unpack_to_rootfs(ch
- 		inptr = 0;
- 		outcnt = 0;		/* bytes in output buffer */
- 		bytes_out = 0;
--		crc = (ulg)0xffffffffL; /* shift register contents */
--		makecrc();
--		gunzip();
--		if (state != Reset)
-+		if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236)))
-+		{
-+		   printk( KERN_NOTICE "detected gzip initramfs\n");
-+		   crc = (ulg)0xffffffffL; /* shift register contents */
-+		   makecrc();
-+		   gunzip();
-+		   if (state != Reset)
- 			error("junk in gzipped archive");
--		this_header = saved_offset + inptr;
-+		}
-+		else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */
-+		{
-+		   printk( KERN_NOTICE "detected lzma initramfs\n");
-+		   lzma_unzip();
-+		}
-+		else
-+		{
-+		   // skip forward ?
-+		   crc = (ulg)0xffffffffL; /* shift register contents */
-+		   makecrc();
-+		   gunzip();
-+		}
-+	        this_header = saved_offset + inptr;
- 		buf += inptr;
- 		len -= inptr;
- 	}
diff --git a/target/linux/brcm47xx/patches-2.6.25/601-mips-remove-pci-collision-check.patch b/target/linux/brcm47xx/patches-2.6.25/601-mips-remove-pci-collision-check.patch
deleted file mode 100644
index 9071b7c..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/601-mips-remove-pci-collision-check.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-The SSB pcicore driver does create some MMIO resource collisions.
-However, the pcicore PCI-fixup routine fixes these collisions afterwards.
-Remove this sanity check for now until we find a better solution.
---mb
---- a/arch/mips/pci/pci.c
-+++ b/arch/mips/pci/pci.c
-@@ -182,12 +182,10 @@ static int pcibios_enable_resources(stru
- 		if ((idx == PCI_ROM_RESOURCE) &&
- 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
- 			continue;
--		if (!r->start && r->end) {
--			printk(KERN_ERR "PCI: Device %s not available "
--			       "because of resource collisions\n",
-+		if (!r->start && r->end)
-+			printk(KERN_WARNING "PCI: Device %s resource"
-+			       "collisions detected. Ignoring...\n",
- 			       pci_name(dev));
--			return -EINVAL;
--		}
- 		if (r->flags & IORESOURCE_IO)
- 			cmd |= PCI_COMMAND_IO;
- 		if (r->flags & IORESOURCE_MEM)
diff --git a/target/linux/brcm47xx/patches-2.6.25/620-ssb-modinit-fix.patch b/target/linux/brcm47xx/patches-2.6.25/620-ssb-modinit-fix.patch
deleted file mode 100644
index af251d5..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/620-ssb-modinit-fix.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -1173,7 +1173,9 @@ static int __init ssb_modinit(void)
- /* ssb must be initialized after PCI but before the ssb drivers.
-  * That means we must use some initcall between subsys_initcall
-  * and device_initcall. */
--fs_initcall(ssb_modinit);
-+//FIXME on embedded we need to be early to make sure we can register
-+//      a new PCI bus, if needed.
-+subsys_initcall(ssb_modinit);
- 
- static void __exit ssb_modexit(void)
- {
diff --git a/target/linux/brcm47xx/patches-2.6.25/630-ssb-fix-irq-init.patch b/target/linux/brcm47xx/patches-2.6.25/630-ssb-fix-irq-init.patch
deleted file mode 100644
index 72505d3..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/630-ssb-fix-irq-init.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-Subject: [OpenWrt-Devel] [PATCH] ssb-pcicore: Fix IRQ-vector init on embedded devices
-
-On embedded devices we must not route the interrupts through
-the PCI core, if our host-bus is not PCI.
-
-Reported-by: Steve Brown <sbrown@cortland.com>
-Signed-off-by: Michael Buesch <mb@bu3sch.de>
-
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -519,6 +519,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
- 	int err = 0;
- 	u32 tmp;
- 
-+	if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
-+		/* This SSB device is not on a PCI host-bus. So the IRQs are
-+		 * not routed through the PCI core.
-+		 * So we must not enable routing through the PCI core. */
-+		goto out;
-+	}
-+
- 	if (!pdev)
- 		goto out;
- 	bus = pdev->bus;
diff --git a/target/linux/brcm47xx/patches-2.6.25/680-ssb-support-8bit-writes.patch b/target/linux/brcm47xx/patches-2.6.25/680-ssb-support-8bit-writes.patch
deleted file mode 100644
index f96b4d2..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/680-ssb-support-8bit-writes.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-Add support for 8bit reads/writes to SSB.
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -508,6 +508,14 @@ error:
- 	return err;
- }
- 
-+static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+
-+	offset += dev->core_index * SSB_CORE_SIZE;
-+	return readb(bus->mmio + offset);
-+}
-+
- static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -524,6 +532,14 @@ static u32 ssb_ssb_read32(struct ssb_dev
- 	return readl(bus->mmio + offset);
- }
- 
-+static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+
-+	offset += dev->core_index * SSB_CORE_SIZE;
-+	writeb(value, bus->mmio + offset);
-+}
-+
- static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -542,8 +558,10 @@ static void ssb_ssb_write32(struct ssb_d
- 
- /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
- static const struct ssb_bus_ops ssb_ssb_ops = {
-+	.read8		= ssb_ssb_read8,
- 	.read16		= ssb_ssb_read16,
- 	.read32		= ssb_ssb_read32,
-+	.write8		= ssb_ssb_write8,
- 	.write16	= ssb_ssb_write16,
- 	.write32	= ssb_ssb_write32,
- };
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -577,6 +577,19 @@ static inline int ssb_pci_assert_buspowe
- }
- #endif /* DEBUG */
- 
-+static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+
-+	if (unlikely(ssb_pci_assert_buspower(bus)))
-+		return 0xFF;
-+	if (unlikely(bus->mapped_device != dev)) {
-+		if (unlikely(ssb_pci_switch_core(bus, dev)))
-+			return 0xFF;
-+	}
-+	return ioread8(bus->mmio + offset);
-+}
-+
- static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -603,6 +616,19 @@ static u32 ssb_pci_read32(struct ssb_dev
- 	return ioread32(bus->mmio + offset);
- }
- 
-+static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+
-+	if (unlikely(ssb_pci_assert_buspower(bus)))
-+		return;
-+	if (unlikely(bus->mapped_device != dev)) {
-+		if (unlikely(ssb_pci_switch_core(bus, dev)))
-+			return;
-+	}
-+	iowrite8(value, bus->mmio + offset);
-+}
-+
- static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -631,8 +657,10 @@ static void ssb_pci_write32(struct ssb_d
- 
- /* Not "static", as it's used in main.c */
- const struct ssb_bus_ops ssb_pci_ops = {
-+	.read8		= ssb_pci_read8,
- 	.read16		= ssb_pci_read16,
- 	.read32		= ssb_pci_read32,
-+	.write8		= ssb_pci_write8,
- 	.write16	= ssb_pci_write16,
- 	.write32	= ssb_pci_write32,
- };
---- a/drivers/ssb/pcmcia.c
-+++ b/drivers/ssb/pcmcia.c
-@@ -172,6 +172,22 @@ static int select_core_and_segment(struc
- 	return 0;
- }
- 
-+static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+	unsigned long flags;
-+	int err;
-+	u8 value = 0xFF;
-+
-+	spin_lock_irqsave(&bus->bar_lock, flags);
-+	err = select_core_and_segment(dev, &offset);
-+	if (likely(!err))
-+		value = readb(bus->mmio + offset);
-+	spin_unlock_irqrestore(&bus->bar_lock, flags);
-+
-+	return value;
-+}
-+
- static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -206,6 +222,20 @@ static u32 ssb_pcmcia_read32(struct ssb_
- 	return (lo | (hi << 16));
- }
- 
-+static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+	struct ssb_bus *bus = dev->bus;
-+	unsigned long flags;
-+	int err;
-+
-+	spin_lock_irqsave(&bus->bar_lock, flags);
-+	err = select_core_and_segment(dev, &offset);
-+	if (likely(!err))
-+		writeb(value, bus->mmio + offset);
-+	mmiowb();
-+	spin_unlock_irqrestore(&bus->bar_lock, flags);
-+}
-+
- static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- 	struct ssb_bus *bus = dev->bus;
-@@ -238,8 +268,10 @@ static void ssb_pcmcia_write32(struct ss
- 
- /* Not "static", as it's used in main.c */
- const struct ssb_bus_ops ssb_pcmcia_ops = {
-+	.read8		= ssb_pcmcia_read8,
- 	.read16		= ssb_pcmcia_read16,
- 	.read32		= ssb_pcmcia_read32,
-+	.write8		= ssb_pcmcia_write8,
- 	.write16	= ssb_pcmcia_write16,
- 	.write32	= ssb_pcmcia_write32,
- };
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -72,8 +72,10 @@ struct ssb_device;
- /* Lowlevel read/write operations on the device MMIO.
-  * Internal, don't use that outside of ssb. */
- struct ssb_bus_ops {
-+	u8 (*read8)(struct ssb_device *dev, u16 offset);
- 	u16 (*read16)(struct ssb_device *dev, u16 offset);
- 	u32 (*read32)(struct ssb_device *dev, u16 offset);
-+	void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
- 	void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
- 	void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
- };
-@@ -348,6 +350,10 @@ void ssb_device_disable(struct ssb_devic
- 
- 
- /* Device MMIO register read/write functions. */
-+static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
-+{
-+	return dev->ops->read8(dev, offset);
-+}
- static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
- {
- 	return dev->ops->read16(dev, offset);
-@@ -356,6 +362,10 @@ static inline u32 ssb_read32(struct ssb_
- {
- 	return dev->ops->read32(dev, offset);
- }
-+static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+	dev->ops->write8(dev, offset, value);
-+}
- static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- 	dev->ops->write16(dev, offset, value);
diff --git a/target/linux/brcm47xx/patches-2.6.25/690-mips-allow-pciregister-after-boot.patch b/target/linux/brcm47xx/patches-2.6.25/690-mips-allow-pciregister-after-boot.patch
deleted file mode 100644
index 8b0445f..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/690-mips-allow-pciregister-after-boot.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-Allow registering PCI devices after early boot.
-
-This is an ugly hack and needs to be rewritten before going upstream.
---- a/arch/mips/pci/pci.c
-+++ b/arch/mips/pci/pci.c
-@@ -21,6 +21,17 @@
-  */
- int pci_probe_only;
- 
-+/*
-+ * Indicate whether PCI-bios init was already done.
-+ */
-+static int pcibios_init_done;
-+
-+/*
-+ * The currently used busnumber.
-+ */
-+static int next_busno;
-+static int need_domain_info;
-+
- #define PCI_ASSIGN_ALL_BUSSES	1
- 
- unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
-@@ -75,8 +86,32 @@ pcibios_align_resource(void *data, struc
- 	res->start = start;
- }
- 
--void __devinit register_pci_controller(struct pci_controller *hose)
-+/* Most MIPS systems have straight-forward swizzling needs.  */
-+
-+static inline u8 bridge_swizzle(u8 pin, u8 slot)
-+{
-+	return (((pin - 1) + slot) % 4) + 1;
-+}
-+
-+static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
- {
-+	u8 pin = *pinp;
-+
-+	while (dev->bus->parent) {
-+		pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
-+		/* Move up the chain of bridges. */
-+		dev = dev->bus->self;
-+        }
-+	*pinp = pin;
-+
-+	/* The slot is the slot of the last bridge. */
-+	return PCI_SLOT(dev->devfn);
-+}
-+
-+void register_pci_controller(struct pci_controller *hose)
-+{
-+	struct pci_bus *bus;
-+
- 	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
- 		goto out;
- 	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
-@@ -84,9 +119,6 @@ void __devinit register_pci_controller(s
- 		goto out;
- 	}
- 
--	*hose_tail = hose;
--	hose_tail = &hose->next;
--
- 	/*
- 	 * Do not panic here but later - this might hapen before console init.
- 	 */
-@@ -94,41 +126,47 @@ void __devinit register_pci_controller(s
- 		printk(KERN_WARNING
- 		       "registering PCI controller with io_map_base unset\n");
- 	}
--	return;
- 
--out:
--	printk(KERN_WARNING
--	       "Skipping PCI bus scan due to resource conflict\n");
--}
-+	if (pcibios_init_done) {
-+		//TODO
- 
--/* Most MIPS systems have straight-forward swizzling needs.  */
-+		printk(KERN_INFO "Registering a PCI bus after boot\n");
- 
--static inline u8 bridge_swizzle(u8 pin, u8 slot)
--{
--	return (((pin - 1) + slot) % 4) + 1;
--}
-+		if (!hose->iommu)
-+			PCI_DMA_BUS_IS_PHYS = 1;
- 
--static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
--{
--	u8 pin = *pinp;
-+		bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
-+		hose->bus = bus;
-+		need_domain_info = need_domain_info || hose->index;
-+		hose->need_domain_info = need_domain_info;
-+		if (bus) {
-+			next_busno = bus->subordinate + 1;
-+			/* Don't allow 8-bit bus number overflow inside the hose -
-+			   reserve some space for bridges. */
-+			if (next_busno > 224) {
-+				next_busno = 0;
-+				need_domain_info = 1;
-+			}
-+		}
-+		if (!pci_probe_only)
-+			pci_assign_unassigned_resources();
-+		pci_fixup_irqs(common_swizzle, pcibios_map_irq);
-+	} else {
-+		*hose_tail = hose;
-+		hose_tail = &hose->next;
-+	}
- 
--	while (dev->bus->parent) {
--		pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
--		/* Move up the chain of bridges. */
--		dev = dev->bus->self;
--        }
--	*pinp = pin;
-+	return;
- 
--	/* The slot is the slot of the last bridge. */
--	return PCI_SLOT(dev->devfn);
-+out:
-+	printk(KERN_WARNING
-+	       "Skipping PCI bus scan due to resource conflict\n");
- }
- 
- static int __init pcibios_init(void)
- {
- 	struct pci_controller *hose;
- 	struct pci_bus *bus;
--	int next_busno;
--	int need_domain_info = 0;
- 
- 	/* Scan all of the recorded PCI controllers.  */
- 	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
-@@ -157,6 +195,7 @@ static int __init pcibios_init(void)
- 	if (!pci_probe_only)
- 		pci_assign_unassigned_resources();
- 	pci_fixup_irqs(common_swizzle, pcibios_map_irq);
-+	pcibios_init_done = 1;
- 
- 	return 0;
- }
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -1191,9 +1191,7 @@ static int __init ssb_modinit(void)
- /* ssb must be initialized after PCI but before the ssb drivers.
-  * That means we must use some initcall between subsys_initcall
-  * and device_initcall. */
--//FIXME on embedded we need to be early to make sure we can register
--//      a new PCI bus, if needed.
--subsys_initcall(ssb_modinit);
-+fs_initcall(ssb_modinit);
- 
- static void __exit ssb_modexit(void)
- {
diff --git a/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch
deleted file mode 100644
index 1ed53e5..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch
+++ /dev/null
@@ -1,1231 +0,0 @@
---- a/drivers/ssb/Kconfig
-+++ b/drivers/ssb/Kconfig
-@@ -125,4 +125,13 @@ config SSB_DRIVER_EXTIF
- 
- 	  If unsure, say N
- 
-+config SSB_DRIVER_GIGE
-+	bool "SSB Broadcom Gigabit Ethernet driver"
-+	depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
-+	help
-+	  Driver for the Sonics Silicon Backplane attached
-+	  Broadcom Gigabit Ethernet.
-+
-+	  If unsure, say N
-+
- endmenu
---- a/drivers/ssb/Makefile
-+++ b/drivers/ssb/Makefile
-@@ -11,6 +11,7 @@ ssb-y					+= driver_chipcommon.o
- ssb-$(CONFIG_SSB_DRIVER_MIPS)		+= driver_mipscore.o
- ssb-$(CONFIG_SSB_DRIVER_EXTIF)		+= driver_extif.o
- ssb-$(CONFIG_SSB_DRIVER_PCICORE)	+= driver_pcicore.o
-+ssb-$(CONFIG_SSB_DRIVER_GIGE)		+= driver_gige.o
- 
- # b43 pci-ssb-bridge driver
- # Not strictly a part of SSB, but kept here for convenience
---- /dev/null
-+++ b/drivers/ssb/driver_gige.c
-@@ -0,0 +1,294 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom Gigabit Ethernet core driver
-+ *
-+ * Copyright 2008, Broadcom Corporation
-+ * Copyright 2008, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
-+#include <linux/pci_regs.h>
-+
-+
-+/*
-+MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
-+MODULE_AUTHOR("Michael Buesch");
-+MODULE_LICENSE("GPL");
-+*/
-+
-+static const struct ssb_device_id ssb_gige_tbl[] = {
-+	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
-+	SSB_DEVTABLE_END
-+};
-+/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
-+
-+
-+static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read8(dev->dev, offset);
-+}
-+
-+static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read16(dev->dev, offset);
-+}
-+
-+static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read32(dev->dev, offset);
-+}
-+
-+static inline void gige_write8(struct ssb_gige *dev,
-+			       u16 offset, u8 value)
-+{
-+	ssb_write8(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write16(struct ssb_gige *dev,
-+				u16 offset, u16 value)
-+{
-+	ssb_write16(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write32(struct ssb_gige *dev,
-+				u16 offset, u32 value)
-+{
-+	ssb_write32(dev->dev, offset, value);
-+}
-+
-+static inline
-+u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read8(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read16(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read32(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+void gige_pcicfg_write8(struct ssb_gige *dev,
-+			unsigned int offset, u8 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write16(struct ssb_gige *dev,
-+			 unsigned int offset, u16 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write32(struct ssb_gige *dev,
-+			 unsigned int offset, u32 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+				    int reg, int size, u32 *val)
-+{
-+	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+	unsigned long flags;
-+
-+	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+	if (reg >= 256)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	spin_lock_irqsave(&dev->lock, flags);
-+	switch (size) {
-+	case 1:
-+		*val = gige_pcicfg_read8(dev, reg);
-+		break;
-+	case 2:
-+		*val = gige_pcicfg_read16(dev, reg);
-+		break;
-+	case 4:
-+		*val = gige_pcicfg_read32(dev, reg);
-+		break;
-+	default:
-+		WARN_ON(1);
-+	}
-+	spin_unlock_irqrestore(&dev->lock, flags);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+				     int reg, int size, u32 val)
-+{
-+	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+	unsigned long flags;
-+
-+	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+	if (reg >= 256)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	spin_lock_irqsave(&dev->lock, flags);
-+	switch (size) {
-+	case 1:
-+		gige_pcicfg_write8(dev, reg, val);
-+		break;
-+	case 2:
-+		gige_pcicfg_write16(dev, reg, val);
-+		break;
-+	case 4:
-+		gige_pcicfg_write32(dev, reg, val);
-+		break;
-+	default:
-+		WARN_ON(1);
-+	}
-+	spin_unlock_irqrestore(&dev->lock, flags);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
-+{
-+	struct ssb_gige *dev;
-+	u32 base, tmslow, tmshigh;
-+
-+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-+	if (!dev)
-+		return -ENOMEM;
-+	dev->dev = sdev;
-+
-+	spin_lock_init(&dev->lock);
-+	dev->pci_controller.pci_ops = &dev->pci_ops;
-+	dev->pci_controller.io_resource = &dev->io_resource;
-+	dev->pci_controller.mem_resource = &dev->mem_resource;
-+	dev->pci_controller.io_map_base = 0x800;
-+	dev->pci_ops.read = ssb_gige_pci_read_config;
-+	dev->pci_ops.write = ssb_gige_pci_write_config;
-+
-+	dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
-+	dev->io_resource.start = 0x800;
-+	dev->io_resource.end = 0x8FF;
-+	dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
-+
-+	if (!ssb_device_is_enabled(sdev))
-+		ssb_device_enable(sdev, 0);
-+
-+	/* Setup BAR0. This is a 64k MMIO region. */
-+	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
-+	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
-+	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
-+
-+	dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
-+	dev->mem_resource.start = base;
-+	dev->mem_resource.end = base + 0x10000 - 1;
-+	dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+
-+	/* Enable the memory region. */
-+	gige_pcicfg_write16(dev, PCI_COMMAND,
-+			    gige_pcicfg_read16(dev, PCI_COMMAND)
-+			    | PCI_COMMAND_MEMORY);
-+
-+	/* Write flushing is controlled by the Flush Status Control register.
-+	 * We want to flush every register write with a timeout and we want
-+	 * to disable the IRQ mask while flushing to avoid concurrency.
-+	 * Note that automatic write flushing does _not_ work from
-+	 * an IRQ handler. The driver must flush manually by reading a register.
-+	 */
-+	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
-+
-+	/* Check if we have an RGMII or GMII PHY-bus.
-+	 * On RGMII do not bypass the DLLs */
-+	tmslow = ssb_read32(sdev, SSB_TMSLOW);
-+	tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
-+	if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
-+		tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
-+		tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
-+		dev->has_rgmii = 1;
-+	} else {
-+		tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
-+		tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
-+		dev->has_rgmii = 0;
-+	}
-+	tmslow |= SSB_GIGE_TMSLOW_DLLEN;
-+	ssb_write32(sdev, SSB_TMSLOW, tmslow);
-+
-+	ssb_set_drvdata(sdev, dev);
-+	register_pci_controller(&dev->pci_controller);
-+
-+	return 0;
-+}
-+
-+bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+	if (!pdev->resource[0].name)
-+		return 0;
-+	return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
-+}
-+EXPORT_SYMBOL(pdev_is_ssb_gige_core);
-+
-+int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+				   struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+	struct resource *res;
-+
-+	if (pdev->bus->ops != &dev->pci_ops) {
-+		/* The PCI device is not on this SSB GigE bridge device. */
-+		return -ENODEV;
-+	}
-+
-+	/* Fixup the PCI resources. */
-+	res = &(pdev->resource[0]);
-+	res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+	res->name = dev->mem_resource.name;
-+	res->start = dev->mem_resource.start;
-+	res->end = dev->mem_resource.end;
-+
-+	/* Fixup interrupt lines. */
-+	pdev->irq = ssb_mips_irq(sdev) + 2;
-+	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
-+
-+	return 0;
-+}
-+
-+int ssb_gige_map_irq(struct ssb_device *sdev,
-+		     const struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+
-+	if (pdev->bus->ops != &dev->pci_ops) {
-+		/* The PCI device is not on this SSB GigE bridge device. */
-+		return -ENODEV;
-+	}
-+
-+	return ssb_mips_irq(sdev) + 2;
-+}
-+
-+static struct ssb_driver ssb_gige_driver = {
-+	.name		= "BCM-GigE",
-+	.id_table	= ssb_gige_tbl,
-+	.probe		= ssb_gige_probe,
-+};
-+
-+int ssb_gige_init(void)
-+{
-+	return ssb_driver_register(&ssb_gige_driver);
-+}
---- /dev/null
-+++ b/include/linux/ssb/ssb_driver_gige.h
-@@ -0,0 +1,174 @@
-+#ifndef LINUX_SSB_DRIVER_GIGE_H_
-+#define LINUX_SSB_DRIVER_GIGE_H_
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/pci.h>
-+#include <linux/spinlock.h>
-+
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+
-+
-+#define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
-+#define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
-+#define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
-+#define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
-+#define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
-+#define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
-+#define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
-+
-+/* TM Status High flags */
-+#define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
-+/* TM Status Low flags */
-+#define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */
-+
-+/* Boardflags (low) */
-+#define SSB_GIGE_BFL_ROBOSWITCH		0x0010
-+
-+
-+#define SSB_GIGE_MEM_RES_NAME		"SSB Broadcom 47xx GigE memory"
-+#define SSB_GIGE_IO_RES_NAME		"SSB Broadcom 47xx GigE I/O"
-+
-+struct ssb_gige {
-+	struct ssb_device *dev;
-+
-+	spinlock_t lock;
-+
-+	/* True, if the device has an RGMII bus.
-+	 * False, if the device has a GMII bus. */
-+	bool has_rgmii;
-+
-+	/* The PCI controller device. */
-+	struct pci_controller pci_controller;
-+	struct pci_ops pci_ops;
-+	struct resource mem_resource;
-+	struct resource io_resource;
-+};
-+
-+/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
-+extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
-+
-+/* Convert a pci_dev pointer to a ssb_gige pointer. */
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+	if (!pdev_is_ssb_gige_core(pdev))
-+		return NULL;
-+	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
-+}
-+
-+/* Returns whether the PHY is connected by an RGMII bus. */
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	return (dev ? dev->has_rgmii : 0);
-+}
-+
-+/* Returns whether we have a Roboswitch. */
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return !!(dev->dev->bus->sprom.boardflags_lo &
-+			  SSB_GIGE_BFL_ROBOSWITCH);
-+	return 0;
-+}
-+
-+/* Returns whether we can only do one DMA at once. */
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return ((dev->dev->bus->chip_id == 0x4785) &&
-+			(dev->dev->bus->chip_rev < 2));
-+	return 0;
-+}
-+
-+/* Returns whether we must flush posted writes. */
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return (dev->dev->bus->chip_id == 0x4785);
-+	return 0;
-+}
-+
-+extern char * nvram_get(const char *name);
-+/* Get the device MAC address */
-+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
-+{
-+#ifdef CONFIG_BCM947XX
-+	char *res = nvram_get("et0macaddr");
-+	if (res)
-+		memcpy(macaddr, res, 6);
-+#endif
-+}
-+
-+extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+					  struct pci_dev *pdev);
-+extern int ssb_gige_map_irq(struct ssb_device *sdev,
-+			    const struct pci_dev *pdev);
-+
-+/* The GigE driver is not a standalone module, because we don't have support
-+ * for unregistering the driver. So we could not unload the module anyway. */
-+extern int ssb_gige_init(void);
-+static inline void ssb_gige_exit(void)
-+{
-+	/* Currently we can not unregister the GigE driver,
-+	 * because we can not unregister the PCI bridge. */
-+	BUG();
-+}
-+
-+
-+#else /* CONFIG_SSB_DRIVER_GIGE */
-+/* Gigabit Ethernet driver disabled */
-+
-+
-+static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+						 struct pci_dev *pdev)
-+{
-+	return -ENOSYS;
-+}
-+static inline int ssb_gige_map_irq(struct ssb_device *sdev,
-+				   const struct pci_dev *pdev)
-+{
-+	return -ENOSYS;
-+}
-+static inline int ssb_gige_init(void)
-+{
-+	return 0;
-+}
-+static inline void ssb_gige_exit(void)
-+{
-+}
-+
-+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+	return NULL;
-+}
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -60,78 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
- /* Core to access the external PCI config space. Can only have one. */
- static struct ssb_pcicore *extpci_core;
- 
--static u32 ssb_pcicore_pcibus_iobase = 0x100;
--static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
--
--int pcibios_plat_dev_init(struct pci_dev *d)
--{
--	struct resource *res;
--	int pos, size;
--	u32 *base;
--
--	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
--		   pci_name(d));
--
--	/* Fix up resource bases */
--	for (pos = 0; pos < 6; pos++) {
--		res = &d->resource[pos];
--		if (res->flags & IORESOURCE_IO)
--			base = &ssb_pcicore_pcibus_iobase;
--		else
--			base = &ssb_pcicore_pcibus_membase;
--		res->flags |= IORESOURCE_PCI_FIXED;
--		if (res->end) {
--			size = res->end - res->start + 1;
--			if (*base & (size - 1))
--				*base = (*base + size) & ~(size - 1);
--			res->start = *base;
--			res->end = res->start + size - 1;
--			*base += size;
--			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
--		}
--		/* Fix up PCI bridge BAR0 only */
--		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
--			break;
--	}
--	/* Fix up interrupt lines */
--	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
--	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
--
--	return 0;
--}
--
--static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
--{
--	u8 lat;
--
--	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
--		return;
--
--	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
--
--	/* Enable PCI bridge bus mastering and memory space */
--	pci_set_master(dev);
--	if (pcibios_enable_device(dev, ~0) < 0) {
--		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
--		return;
--	}
--
--	/* Enable PCI bridge BAR1 prefetch and burst */
--	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
--
--	/* Make sure our latency is high enough to handle the devices behind us */
--	lat = 168;
--	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
--		   pci_name(dev), lat);
--	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
--}
--DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
--
--int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
--{
--	return ssb_mips_irq(extpci_core->dev) + 2;
--}
--
- static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
- 			     unsigned int bus, unsigned int dev,
- 			     unsigned int func, unsigned int off)
-@@ -320,6 +248,95 @@ static struct pci_controller ssb_pcicore
- 	.mem_offset	= 0x24000000,
- };
- 
-+static u32 ssb_pcicore_pcibus_iobase = 0x100;
-+static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
-+
-+/* This function is called when doing a pci_enable_device().
-+ * We must first check if the device is a device on the PCI-core bridge. */
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+	struct resource *res;
-+	int pos, size;
-+	u32 *base;
-+
-+	if (d->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return -ENODEV;
-+	}
-+
-+	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
-+		   pci_name(d));
-+
-+	/* Fix up resource bases */
-+	for (pos = 0; pos < 6; pos++) {
-+		res = &d->resource[pos];
-+		if (res->flags & IORESOURCE_IO)
-+			base = &ssb_pcicore_pcibus_iobase;
-+		else
-+			base = &ssb_pcicore_pcibus_membase;
-+		res->flags |= IORESOURCE_PCI_FIXED;
-+		if (res->end) {
-+			size = res->end - res->start + 1;
-+			if (*base & (size - 1))
-+				*base = (*base + size) & ~(size - 1);
-+			res->start = *base;
-+			res->end = res->start + size - 1;
-+			*base += size;
-+			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-+		}
-+		/* Fix up PCI bridge BAR0 only */
-+		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-+			break;
-+	}
-+	/* Fix up interrupt lines */
-+	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-+	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
-+
-+	return 0;
-+}
-+
-+/* Early PCI fixup for a device on the PCI-core bridge. */
-+static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
-+{
-+	u8 lat;
-+
-+	if (dev->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return;
-+	}
-+	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-+		return;
-+
-+	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
-+
-+	/* Enable PCI bridge bus mastering and memory space */
-+	pci_set_master(dev);
-+	if (pcibios_enable_device(dev, ~0) < 0) {
-+		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
-+		return;
-+	}
-+
-+	/* Enable PCI bridge BAR1 prefetch and burst */
-+	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
-+
-+	/* Make sure our latency is high enough to handle the devices behind us */
-+	lat = 168;
-+	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
-+		   pci_name(dev), lat);
-+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
-+
-+/* PCI device IRQ mapping. */
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	if (dev->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return -ENODEV;
-+	}
-+	return ssb_mips_irq(extpci_core->dev) + 2;
-+}
-+
- static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
- {
- 	u32 val;
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -10,6 +10,9 @@
- 
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
-+#include <linux/ssb/ssb_driver_pci.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
- 
- #include "ssb_private.h"
- 
-@@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
- 	return res;
- }
- EXPORT_SYMBOL(ssb_gpio_polarity);
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+	struct pci_dev *pdev = (struct pci_dev *)data;
-+	struct ssb_device *dev;
-+	unsigned int i;
-+	int res;
-+
-+	for (i = 0; i < bus->nr_devices; i++) {
-+		dev = &(bus->devices[i]);
-+		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+			continue;
-+		if (!dev->dev ||
-+		    !dev->dev->driver ||
-+		    !device_is_registered(dev->dev))
-+			continue;
-+		res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
-+		if (res >= 0)
-+			return res;
-+	}
-+
-+	return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	int err;
-+
-+	err = ssb_pcicore_plat_dev_init(dev);
-+	if (!err)
-+		return 0;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+	err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
-+	if (err >= 0)
-+		return err;
-+#endif
-+	/* This is not a PCI device on any SSB device. */
-+
-+	return -ENODEV;
-+}
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+	const struct pci_dev *pdev = (const struct pci_dev *)data;
-+	struct ssb_device *dev;
-+	unsigned int i;
-+	int res;
-+
-+	for (i = 0; i < bus->nr_devices; i++) {
-+		dev = &(bus->devices[i]);
-+		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+			continue;
-+		if (!dev->dev ||
-+		    !dev->dev->driver ||
-+		    !device_is_registered(dev->dev))
-+			continue;
-+		res = ssb_gige_map_irq(dev, pdev);
-+		if (res >= 0)
-+			return res;
-+	}
-+
-+	return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	int res;
-+
-+	/* Check if this PCI device is a device on a SSB bus or device
-+	 * and return the IRQ number for it. */
-+
-+	res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
-+	if (res >= 0)
-+		return res;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+	res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
-+	if (res >= 0)
-+		return res;
-+#endif
-+	/* This is not a PCI device on any SSB device. */
-+
-+	return -ENODEV;
-+}
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -426,5 +426,12 @@ extern int ssb_bus_powerup(struct ssb_bu
- extern u32 ssb_admatch_base(u32 adm);
- extern u32 ssb_admatch_size(u32 adm);
- 
-+/* PCI device mapping and fixup routines.
-+ * Called from the architecture pcibios init code.
-+ * These are only available on SSB_EMBEDDED configurations. */
-+#ifdef CONFIG_SSB_EMBEDDED
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+#endif /* CONFIG_SSB_EMBEDDED */
- 
- #endif /* LINUX_SSB_H_ */
---- a/include/linux/ssb/ssb_driver_pci.h
-+++ b/include/linux/ssb/ssb_driver_pci.h
-@@ -1,6 +1,11 @@
- #ifndef LINUX_SSB_PCICORE_H_
- #define LINUX_SSB_PCICORE_H_
- 
-+#include <linux/types.h>
-+
-+struct pci_dev;
-+
-+
- #ifdef CONFIG_SSB_DRIVER_PCICORE
- 
- /* PCI core registers. */
-@@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
- extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
- 					  struct ssb_device *dev);
- 
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d);
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+
- 
- #else /* CONFIG_SSB_DRIVER_PCICORE */
- 
-@@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
- 	return 0;
- }
- 
-+static inline
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+	return -ENODEV;
-+}
-+static inline
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	return -ENODEV;
-+}
-+
- #endif /* CONFIG_SSB_DRIVER_PCICORE */
- #endif /* LINUX_SSB_PCICORE_H_ */
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -14,6 +14,7 @@
- #include <linux/io.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_regs.h>
-+#include <linux/ssb/ssb_driver_gige.h>
- #include <linux/dma-mapping.h>
- #include <linux/pci.h>
- 
-@@ -68,6 +69,25 @@ found:
- }
- #endif /* CONFIG_SSB_PCIHOST */
- 
-+int ssb_for_each_bus_call(unsigned long data,
-+			  int (*func)(struct ssb_bus *bus, unsigned long data))
-+{
-+	struct ssb_bus *bus;
-+	int res;
-+
-+	ssb_buses_lock();
-+	list_for_each_entry(bus, &buses, list) {
-+		res = func(bus, data);
-+		if (res >= 0) {
-+			ssb_buses_unlock();
-+			return res;
-+		}
-+	}
-+	ssb_buses_unlock();
-+
-+	return -ENODEV;
-+}
-+
- static struct ssb_device *ssb_device_get(struct ssb_device *dev)
- {
- 	if (dev)
-@@ -1181,7 +1201,14 @@ static int __init ssb_modinit(void)
- 	err = b43_pci_ssb_bridge_init();
- 	if (err) {
- 		ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
--			   "initialization failed");
-+			   "initialization failed\n");
-+		/* don't fail SSB init because of this */
-+		err = 0;
-+	}
-+	err = ssb_gige_init();
-+	if (err) {
-+		ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
-+			   "driver initialization failed\n");
- 		/* don't fail SSB init because of this */
- 		err = 0;
- 	}
-@@ -1195,6 +1222,7 @@ fs_initcall(ssb_modinit);
- 
- static void __exit ssb_modexit(void)
- {
-+	ssb_gige_exit();
- 	b43_pci_ssb_bridge_exit();
- 	bus_unregister(&ssb_bustype);
- }
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
- extern int ssb_devices_freeze(struct ssb_bus *bus);
- extern int ssb_devices_thaw(struct ssb_bus *bus);
- extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
-+int ssb_for_each_bus_call(unsigned long data,
-+			  int (*func)(struct ssb_bus *bus, unsigned long data));
- 
- /* b43_pci_bridge.c */
- #ifdef CONFIG_SSB_B43_PCI_BRIDGE
---- a/drivers/net/tg3.c
-+++ b/drivers/net/tg3.c
-@@ -38,6 +38,7 @@
- #include <linux/workqueue.h>
- #include <linux/prefetch.h>
- #include <linux/dma-mapping.h>
-+#include <linux/ssb/ssb_driver_gige.h>
- 
- #include <net/checksum.h>
- #include <net/ip.h>
-@@ -425,8 +426,9 @@ static void _tw32_flush(struct tg3 *tp, 
- static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
- {
- 	tp->write32_mbox(tp, off, val);
--	if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
--	    !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
-+	if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
-+	    (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
-+	     !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
- 		tp->read32_mbox(tp, off);
- }
- 
-@@ -706,7 +708,7 @@ static void tg3_switch_clocks(struct tg3
- 
- #define PHY_BUSY_LOOPS	5000
- 
--static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
- {
- 	u32 frame_val;
- 	unsigned int loops;
-@@ -720,7 +722,7 @@ static int tg3_readphy(struct tg3 *tp, i
- 
- 	*val = 0x0;
- 
--	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- 		      MI_COM_PHY_ADDR_MASK);
- 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- 		      MI_COM_REG_ADDR_MASK);
-@@ -755,7 +757,12 @@ static int tg3_readphy(struct tg3 *tp, i
- 	return ret;
- }
- 
--static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+{
-+	return __tg3_readphy(tp, PHY_ADDR, reg, val);
-+}
-+
-+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
- {
- 	u32 frame_val;
- 	unsigned int loops;
-@@ -771,7 +778,7 @@ static int tg3_writephy(struct tg3 *tp, 
- 		udelay(80);
- 	}
- 
--	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- 		      MI_COM_PHY_ADDR_MASK);
- 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- 		      MI_COM_REG_ADDR_MASK);
-@@ -804,6 +811,11 @@ static int tg3_writephy(struct tg3 *tp, 
- 	return ret;
- }
- 
-+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+{
-+	return __tg3_writephy(tp, PHY_ADDR, reg, val);
-+}
-+
- static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
- {
- 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-@@ -2250,6 +2262,14 @@ static int tg3_setup_copper_phy(struct t
- 			}
- 		}
- 
-+		if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
-+			current_link_up = 1;
-+			current_speed = SPEED_1000; //FIXME
-+			current_duplex = DUPLEX_FULL;
-+			tp->link_config.active_speed = current_speed;
-+			tp->link_config.active_duplex = current_duplex;
-+		}
-+
- 		if (current_link_up == 1 &&
- 		    tp->link_config.active_duplex == DUPLEX_FULL)
- 			tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
-@@ -5197,6 +5217,11 @@ static int tg3_poll_fw(struct tg3 *tp)
- 	int i;
- 	u32 val;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
- 		/* Wait up to 20ms for init done. */
- 		for (i = 0; i < 200; i++) {
-@@ -5435,6 +5460,14 @@ static int tg3_chip_reset(struct tg3 *tp
- 		tw32(0x5000, 0x400);
- 	}
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* BCM4785: In order to avoid repercussions from using potentially
-+		 * defective internal ROM, stop the Rx RISC CPU, which is not
-+		 * required. */
-+		tg3_stop_fw(tp);
-+		tg3_halt_cpu(tp, RX_CPU_BASE);
-+	}
-+
- 	tw32(GRC_MODE, tp->grc_mode);
- 
- 	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-@@ -5704,9 +5737,12 @@ static int tg3_halt_cpu(struct tg3 *tp, 
- 		return -ENODEV;
- 	}
- 
--	/* Clear firmware's nvram arbitration. */
--	if (tp->tg3_flags & TG3_FLAG_NVRAM)
--		tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+	if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
-+		/* Clear firmware's nvram arbitration. */
-+		if (tp->tg3_flags & TG3_FLAG_NVRAM)
-+			tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+	}
-+
- 	return 0;
- }
- 
-@@ -5787,6 +5823,11 @@ static int tg3_load_5701_a0_firmware_fix
- 	struct fw_info info;
- 	int err, i;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	info.text_base = TG3_FW_TEXT_ADDR;
- 	info.text_len = TG3_FW_TEXT_LEN;
- 	info.text_data = &tg3FwText[0];
-@@ -6345,6 +6386,11 @@ static int tg3_load_tso_firmware(struct 
- 	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
- 	int err, i;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
- 		return 0;
- 
-@@ -7306,6 +7352,11 @@ static void tg3_timer(unsigned long __op
- 
- 	spin_lock(&tp->lock);
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+		/* BCM4785: Flush posted writes from GbE to host memory. */
-+		tr32(HOSTCC_MODE);
-+	}
-+
- 	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
- 		/* All of this garbage is because when using non-tagged
- 		 * IRQ status the mailbox/status_block protocol the chip
-@@ -8906,6 +8957,11 @@ static int tg3_test_nvram(struct tg3 *tp
- 	__le32 *buf;
- 	int i, j, k, err = 0, size;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't have NVRAM. */
-+		return 0;
-+	}
-+
- 	if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
- 		return -EIO;
- 
-@@ -9689,7 +9745,7 @@ static int tg3_ioctl(struct net_device *
- 			return -EAGAIN;
- 
- 		spin_lock_bh(&tp->lock);
--		err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
-+		err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
- 		spin_unlock_bh(&tp->lock);
- 
- 		data->val_out = mii_regval;
-@@ -9708,7 +9764,7 @@ static int tg3_ioctl(struct net_device *
- 			return -EAGAIN;
- 
- 		spin_lock_bh(&tp->lock);
--		err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
-+		err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
- 		spin_unlock_bh(&tp->lock);
- 
- 		return err;
-@@ -10177,6 +10233,12 @@ static void __devinit tg3_get_5906_nvram
- /* Chips other than 5700/5701 use the NVRAM for fetching info. */
- static void __devinit tg3_nvram_init(struct tg3 *tp)
- {
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
-+		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
-+		return;
-+	}
-+
- 	tw32_f(GRC_EEPROM_ADDR,
- 	     (EEPROM_ADDR_FSM_RESET |
- 	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
-@@ -10317,6 +10379,9 @@ static int tg3_nvram_read(struct tg3 *tp
- {
- 	int ret;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+		return -ENODEV;
-+
- 	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
- 		return tg3_nvram_read_using_eeprom(tp, offset, val);
- 
-@@ -10563,6 +10628,9 @@ static int tg3_nvram_write_block(struct 
- {
- 	int ret;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+		return -ENODEV;
-+
- 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
- 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
- 		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -11610,7 +11678,6 @@ static int __devinit tg3_get_invariants(
- 		tp->write32 = tg3_write_flush_reg32;
- 	}
- 
--
- 	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
- 	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
- 		tp->write32_tx_mbox = tg3_write32_tx_mbox;
-@@ -11646,6 +11713,11 @@ static int __devinit tg3_get_invariants(
- 	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
- 		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+		tp->write32_tx_mbox = tg3_write_flush_reg32;
-+		tp->write32_rx_mbox = tg3_write_flush_reg32;
-+	}
-+
- 	/* Get eeprom hw config before calling tg3_set_power_state().
- 	 * In particular, the TG3_FLG2_IS_NIC flag must be
- 	 * determined before calling tg3_set_power_state() so that
-@@ -12017,6 +12089,10 @@ static int __devinit tg3_get_device_addr
- 	}
- 
- 	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
-+		if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+			ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
-+	}
-+	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
- #ifdef CONFIG_SPARC
- 		if (!tg3_get_default_macaddr_sparc(tp))
- 			return 0;
-@@ -12508,6 +12584,7 @@ static char * __devinit tg3_phy_string(s
- 	case PHY_ID_BCM5704:	return "5704";
- 	case PHY_ID_BCM5705:	return "5705";
- 	case PHY_ID_BCM5750:	return "5750";
-+	case PHY_ID_BCM5750_2:	return "5750-2";
- 	case PHY_ID_BCM5752:	return "5752";
- 	case PHY_ID_BCM5714:	return "5714";
- 	case PHY_ID_BCM5780:	return "5780";
-@@ -12695,6 +12772,13 @@ static int __devinit tg3_init_one(struct
- 		tp->msg_enable = tg3_debug;
- 	else
- 		tp->msg_enable = TG3_DEF_MSG_ENABLE;
-+	if (pdev_is_ssb_gige_core(pdev)) {
-+		tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
-+		if (ssb_gige_must_flush_posted_writes(pdev))
-+			tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
-+		if (ssb_gige_have_roboswitch(pdev))
-+			tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
-+	}
- 
- 	/* The word/byte swap controls here control register access byte
- 	 * swapping.  DMA data byte swapping is controlled in the GRC_MODE
---- a/drivers/net/tg3.h
-+++ b/drivers/net/tg3.h
-@@ -2477,6 +2477,9 @@ struct tg3 {
- #define TG3_FLG3_ENABLE_APE		0x00000002
- #define TG3_FLG3_5761_5784_AX_FIXES	0x00000004
- #define TG3_FLG3_5701_DMA_BUG		0x00000008
-+#define TG3_FLG3_IS_SSB_CORE		0x00000010
-+#define TG3_FLG3_FLUSH_POSTED_WRITES	0x00000020
-+#define TG3_FLG3_ROBOSWITCH		0x00000040
- 
- 	struct timer_list		timer;
- 	u16				timer_counter;
-@@ -2532,6 +2535,7 @@ struct tg3 {
- #define PHY_ID_BCM5714			0x60008340
- #define PHY_ID_BCM5780			0x60008350
- #define PHY_ID_BCM5755			0xbc050cc0
-+#define PHY_ID_BCM5750_2		0xbc050cd0
- #define PHY_ID_BCM5787			0xbc050ce0
- #define PHY_ID_BCM5756			0xbc050ed0
- #define PHY_ID_BCM5784			0xbc050fa0
-@@ -2568,7 +2572,7 @@ struct tg3 {
- 	 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
- 	 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
- 	 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
--	 (X) == PHY_ID_BCM8002)
-+	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
- 
- 	struct tg3_hw_stats		*hw_stats;
- 	dma_addr_t			stats_mapping;
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -212,6 +212,7 @@ void ssb_mipscore_init(struct ssb_mipsco
- 			/* fallthrough */
- 		case SSB_DEV_PCI:
- 		case SSB_DEV_ETHERNET:
-+		case SSB_DEV_ETHERNET_GBIT:
- 		case SSB_DEV_80211:
- 		case SSB_DEV_USB20_HOST:
- 			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
diff --git a/target/linux/brcm47xx/patches-2.6.25/710-add-gpio-is-valid.patch b/target/linux/brcm47xx/patches-2.6.25/710-add-gpio-is-valid.patch
deleted file mode 100644
index b06f08e..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/710-add-gpio-is-valid.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-Add gpio_is_valid() for bcm47xx
---- a/arch/mips/bcm47xx/gpio.c
-+++ b/arch/mips/bcm47xx/gpio.c
-@@ -77,3 +77,15 @@ int bcm47xx_gpio_direction_output(unsign
- }
- EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
- 
-+int bcm47xx_gpio_is_valid(int gpio)
-+{
-+	if (ssb_bcm47xx.chipco.dev) {
-+		if (gpio >= 0 && gpio < BCM47XX_CHIPCO_GPIO_LINES)
-+			return 1;
-+	} else if (ssb_bcm47xx.extif.dev) {
-+		if (gpio >= 0 && gpio < BCM47XX_EXTIF_GPIO_LINES)
-+			return 1;
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(bcm47xx_gpio_is_valid);
---- a/include/asm-mips/mach-bcm47xx/gpio.h
-+++ b/include/asm-mips/mach-bcm47xx/gpio.h
-@@ -17,6 +17,7 @@ extern int bcm47xx_gpio_get_value(unsign
- extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
- extern int bcm47xx_gpio_direction_input(unsigned gpio);
- extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
-+extern int bcm47xx_gpio_is_valid(int gpio);
- 
- static inline int gpio_request(unsigned gpio, const char *label)
- {
-@@ -52,6 +53,8 @@ static inline int gpio_direction_output(
- 	return bcm47xx_gpio_direction_output(gpio, value);
- }
- 
-+#define gpio_is_valid	bcm47xx_gpio_is_valid
-+
- 
- /* cansleep wrappers */
- #include <asm-generic/gpio.h>
diff --git a/target/linux/brcm47xx/patches-2.6.25/800-fix_cfe_detection.patch b/target/linux/brcm47xx/patches-2.6.25/800-fix_cfe_detection.patch
deleted file mode 100644
index 63a71f0..0000000
--- a/target/linux/brcm47xx/patches-2.6.25/800-fix_cfe_detection.patch
+++ /dev/null
@@ -1,108 +0,0 @@
---- a/arch/mips/bcm47xx/prom.c
-+++ b/arch/mips/bcm47xx/prom.c
-@@ -32,6 +32,7 @@
- #include <asm/fw/cfe/cfe_error.h>
- 
- static int cfe_cons_handle;
-+static void (* __prom_putchar)(char c);
- 
- const char *get_system_type(void)
- {
-@@ -40,65 +41,40 @@ const char *get_system_type(void)
- 
- void prom_putchar(char c)
- {
-+	if (__prom_putchar)
-+		__prom_putchar(c);
-+}
-+
-+void prom_putchar_cfe(char c)
-+{
- 	while (cfe_write(cfe_cons_handle, &c, 1) == 0)
- 		;
- }
- 
--static __init void prom_init_cfe(void)
-+static __init int prom_init_cfe(void)
- {
- 	uint32_t cfe_ept;
- 	uint32_t cfe_handle;
- 	uint32_t cfe_eptseal;
--	int argc = fw_arg0;
--	char **envp = (char **) fw_arg2;
--	int *prom_vec = (int *) fw_arg3;
--
--	/*
--	 * Check if a loader was used; if NOT, the 4 arguments are
--	 * what CFE gives us (handle, 0, EPT and EPTSEAL)
--	 */
--	if (argc < 0) {
--		cfe_handle = (uint32_t)argc;
--		cfe_ept = (uint32_t)envp;
--		cfe_eptseal = (uint32_t)prom_vec;
--	} else {
--		if ((int)prom_vec < 0) {
--			/*
--			 * Old loader; all it gives us is the handle,
--			 * so use the "known" entrypoint and assume
--			 * the seal.
--			 */
--			cfe_handle = (uint32_t)prom_vec;
--			cfe_ept = 0xBFC00500;
--			cfe_eptseal = CFE_EPTSEAL;
--		} else {
--			/*
--			 * Newer loaders bundle the handle/ept/eptseal
--			 * Note: prom_vec is in the loader's useg
--			 * which is still alive in the TLB.
--			 */
--			cfe_handle = prom_vec[0];
--			cfe_ept = prom_vec[2];
--			cfe_eptseal = prom_vec[3];
--		}
--	}
- 
--	if (cfe_eptseal != CFE_EPTSEAL) {
--		/* too early for panic to do any good */
--		printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
--		while (1) ;
--	}
-+	cfe_eptseal = (uint32_t) fw_arg3;
-+	cfe_handle = (uint32_t) fw_arg0;
-+	cfe_ept = (uint32_t) fw_arg2;
-+
-+	if (cfe_eptseal != CFE_EPTSEAL)
-+		return -1;
- 
- 	cfe_init(cfe_handle, cfe_ept);
-+	return 0;
- }
- 
--static __init void prom_init_console(void)
-+static __init void prom_init_console_cfe(void)
- {
- 	/* Initialize CFE console */
- 	cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
- }
- 
--static __init void prom_init_cmdline(void)
-+static __init void prom_init_cmdline_cfe(void)
- {
- 	char buf[CL_SIZE];
- 
-@@ -146,9 +122,12 @@ static __init void prom_init_mem(void)
- 
- void __init prom_init(void)
- {
--	prom_init_cfe();
--	prom_init_console();
--	prom_init_cmdline();
-+	if (prom_init_cfe() == 0) {
-+		prom_init_console_cfe();
-+		prom_init_cmdline_cfe();
-+		__prom_putchar = prom_putchar_cfe;
-+	}
-+
- 	prom_init_mem();
- }
-