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author | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
commit | e8068f0b1b4e53559ae0c58910b8905bee9b61ab (patch) | |
tree | cf44e0daeb888e0b4c69d9bf8483088a05239b96 /target/linux/brcm63xx/dts | |
parent | 443d730da80775f4e6740f947b447e0bffef3644 (diff) | |
download | mtk-20170518-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.zip mtk-20170518-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.tar.gz mtk-20170518-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.tar.bz2 |
brcm63xx: register interrupt-controllers through DT when possible
Add the required nodes for the interrupt controllers and register
them through DT when a DTB is present.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43457
Diffstat (limited to 'target/linux/brcm63xx/dts')
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6318.dtsi | 30 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm63268.dtsi | 31 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6328.dtsi | 30 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6338.dtsi | 30 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6345.dtsi | 30 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6348.dtsi | 30 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6358.dtsi | 42 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6362.dtsi | 31 | ||||
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6368.dtsi | 42 |
9 files changed, 296 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/dts/bcm6318.dtsi b/target/linux/brcm63xx/dts/bcm6318.dtsi index 370183e..723c488 100644 --- a/target/linux/brcm63xx/dts/bcm6318.dtsi +++ b/target/linux/brcm63xx/dts/bcm6318.dtsi @@ -14,6 +14,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -21,5 +29,27 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>, <26>, <27>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm63268.dtsi b/target/linux/brcm63xx/dts/bcm63268.dtsi index eafa74b..214cd62 100644 --- a/target/linux/brcm63xx/dts/bcm63268.dtsi +++ b/target/linux/brcm63xx/dts/bcm63268.dtsi @@ -20,6 +20,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -27,5 +35,28 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <44>, <45>, <46>, <47>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x20>, + <0x10000040 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6328.dtsi b/target/linux/brcm63xx/dts/bcm6328.dtsi index c9940c1..0ed186e 100644 --- a/target/linux/brcm63xx/dts/bcm6328.dtsi +++ b/target/linux/brcm63xx/dts/bcm6328.dtsi @@ -14,6 +14,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -21,5 +29,27 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>, <26>, <27>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6338.dtsi b/target/linux/brcm63xx/dts/bcm6338.dtsi index 9746e7a..b527781 100644 --- a/target/linux/brcm63xx/dts/bcm6338.dtsi +++ b/target/linux/brcm63xx/dts/bcm6338.dtsi @@ -18,6 +18,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; pflash: nor@1fc00000 { @@ -35,5 +43,27 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0xfffe000c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6345.dtsi b/target/linux/brcm63xx/dts/bcm6345.dtsi index 03e742b..16ba8bd 100644 --- a/target/linux/brcm63xx/dts/bcm6345.dtsi +++ b/target/linux/brcm63xx/dts/bcm6345.dtsi @@ -18,6 +18,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; pflash: nor@1fc00000 { @@ -35,5 +43,27 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0xfffe000c 0x9>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6348.dtsi b/target/linux/brcm63xx/dts/bcm6348.dtsi index 404ed33..06ecbaa 100644 --- a/target/linux/brcm63xx/dts/bcm6348.dtsi +++ b/target/linux/brcm63xx/dts/bcm6348.dtsi @@ -18,6 +18,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; pflash: nor@1fc00000 { @@ -35,5 +43,27 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0xfffe000c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6348-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6358.dtsi b/target/linux/brcm63xx/dts/bcm6358.dtsi index b376cf0..a4af214 100644 --- a/target/linux/brcm63xx/dts/bcm6358.dtsi +++ b/target/linux/brcm63xx/dts/bcm6358.dtsi @@ -24,6 +24,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; pflash: nor@1e000000 { @@ -41,5 +49,39 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0xfffe000c 0x8>, + <0xfffe0038 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + ext_intc0: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <25>, <26>, <27>, <28>; + }; + + ext_intc1: interrupt-controller@fffe001c { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe001c 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <20>, <21>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6362.dtsi b/target/linux/brcm63xx/dts/bcm6362.dtsi index 543d24e..36765b0 100644 --- a/target/linux/brcm63xx/dts/bcm6362.dtsi +++ b/target/linux/brcm63xx/dts/bcm6362.dtsi @@ -20,6 +20,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -27,5 +35,28 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <40>, <41>, <42>, <43>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; }; }; diff --git a/target/linux/brcm63xx/dts/bcm6368.dtsi b/target/linux/brcm63xx/dts/bcm6368.dtsi index 378f4fb..dcbbdbf 100644 --- a/target/linux/brcm63xx/dts/bcm6368.dtsi +++ b/target/linux/brcm63xx/dts/bcm6368.dtsi @@ -24,6 +24,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -31,6 +39,40 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc0: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <20>, <21>, <22>, <23>; + }; + + ext_intc1: interrupt-controller@1000001c { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x1000001c 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; }; pflash: nor@18000000 { |