prepare for SPI controller driver

SVN-Revision: 14755

3 files changed, 140 insertions, 0 deletions

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 6fa8825..be9da2e 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -290,6 +290,120 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 }
 
 /*
+ * SPI register layout is not compatible
+ * accross CPU versions but it is software
+ * compatible
+ */
+
+enum bcm63xx_regs_spi {
+	SPI_CMD,
+	SPI_INT_STATUS,
+	SPI_INT_MASK_ST,
+	SPI_INT_MASK,
+	SPI_ST,
+	SPI_CLK_CFG,
+	SPI_FILL_BYTE,
+	SPI_MSG_TAIL,
+	SPI_RX_TAIL,
+	SPI_MSG_CTL,
+	SPI_MSG_DATA,
+	SPI_RX_DATA,
+};
+
+extern const unsigned long *bcm63xx_regs_spi;
+
+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        return bcm63xx_regs_spi[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6338
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6338_SPI_CMD;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6338_SPI_INT_STATUS;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6338_SPI_MASK_INT_ST;
+	case SPI_INT_MASK:
+		return SPI_BCM_6338_SPI_INT_MASK;
+	case SPI_ST:
+		return SPI_BCM_6338_SPI_ST;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6338_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6338_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6338_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6338_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6338_SPI_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6338_SPI_MSG_DATA;
+	case SPI_RX_DATA:
+		return SPI_BCM_6338_SPI_RX_DATA;
+}
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6348_SPI_CMD;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6348_SPI_MASK_INT_ST;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6348_SPI_INT_STATUS;
+	case SPI_ST:
+		return SPI_BCM_6348_SPI_ST;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6348_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6348_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6348_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6348_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6348_SPI_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6348_SPI_MSG_DATA;
+	case SPI_BCM_6348_SPI_RX_DATA:
+		return SPI_BCM_6348_SPI_RX_DATA;
+}
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+switch (reg) {
+	case SPI_CMD:
+		return SPI_BCM_6358_SPI_CMD;
+	case SPI_INT_STATUS:
+		return SPI_BCM_6358_SPI_INT_STATUS;
+	case SPI_INT_MASK_ST:
+		return SPI_BCM_6358_SPI_MASK_INT_ST;
+	case SPI_INT_MASK:
+		return SPI_BCM_6358_SPI_INT_MASK;
+	case SPI_ST:
+		return SPI_BCM_6358_SPI_STATUS;
+	case SPI_CLK_CFG:
+		return SPI_BCM_6358_SPI_CLK_CFG;
+	case SPI_FILL_BYTE:
+		return SPI_BCM_6358_SPI_FILL_BYTE;
+	case SPI_MSG_TAIL:
+		return SPI_BCM_6358_SPI_MSG_TAIL;
+	case SPI_RX_TAIL:
+		return SPI_BCM_6358_SPI_RX_TAIL;
+	case SPI_MSG_CTL:
+		return SPI_BCM_6358_MSG_CTL;
+	case SPI_MSG_DATA:
+		return SPI_BCM_6358_SPI_MSG_DATA;
+	case SPI_RX_DATA:
+		return SPI_BCM_6358_SPI_RX_FIFO;
+}
+#endif
+#endif
+	return 0;
+}
+
+/*
  * IRQ number changes across CPU too
  */
 enum bcm63xx_irq {
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 0000000..bd47676
--- /dev/null
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,16 @@
+#ifndef BCM63XX_DEV_SPI_H
+#define BCM63XX_DEV_SPI_H
+
+#include <linux/types.h>
+
+int bcm63xx_spi_register(void);
+
+struct bcm63xx_spi_pdata {
+	unsigned int	msg_fifo_size;
+	unsigned int	rx_fifo_size;
+	int		bus_num;
+	int		num_chipselect;
+	u32		speed_hz;
+};
+
+#endif /* BCM63XX_DEV_SPI_H */
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_io.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
index 1aef06f..af98611 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
@@ -65,6 +65,12 @@
 					bcm63xx_regset_address(s) + (o))
 #define bcm_rset_writel(s,v,o)	bcm_writel((v), \
 					bcm63xx_regset_address(s) + (o))
+#define bcm_reg_spi_readb(s,o)	bcm_readb(bcm63xx_spireg(s) + (o))
+#define bcm_reg_spi_readw(s,o)	bcm_readw(bcm63xx_spireg(s) + (o))
+#define bcm_reg_spi_writeb(s,v,o)	bcm_writeb((v), \
+					bcm63xx_spireg(s) + (o))
+#define bcm_reg_spi_writew(s,v,o)	bcm_writew((v), \
+					bcm63xx_spireg(s) + (o))
 
 /*
  * helpers for frequently used register sets
@@ -89,5 +95,9 @@
 #define bcm_memc_writel(v,o)	bcm_rset_writel(RSET_MEMC, (v), (o))
 #define bcm_ddr_readl(o)	bcm_rset_readl(RSET_DDR, (o))
 #define bcm_ddr_writel(v,o)	bcm_rset_writel(RSET_DDR, (v), (o))
+#define bcm_spi_readb(o)	bcm_reg_spi_readb(RSET_SPI, (o))
+#define bcm_spi_readw(o)	bcm_reg_spi_readw(RSET_SPI, (o))
+#define bcm_spi_writeb(v,o)	bcm_reg_spi_writeb(RSET_SPI, (v), (o))
+#define bcm_spi_writew(v,o)	bcm_reg_spi_writew(RSET_SPI, (v), (o))
 
 #endif /* ! BCM63XX_IO_H_ */