New Broadcom BCM63xx codebase, huge thanks to Maxime ;)

SVN-Revision: 13001

12 files changed, 10518 insertions, 0 deletions

diff --git a/target/linux/brcm63xx/patches-2.6.27/001-add_broadcom_63xx_cpu_definitions.patch b/target/linux/brcm63xx/patches-2.6.27/001-add_broadcom_63xx_cpu_definitions.patch
new file mode 100644
index 0000000..cda9181
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/001-add_broadcom_63xx_cpu_definitions.patch
@@ -0,0 +1,110 @@
+From a9f65413f9ea81ef2208da66a3db9cb8a9020eef Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Fri, 18 Jul 2008 15:53:08 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add Broadcom 63xx CPU definitions.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/kernel/cpu-probe.c |   25 +++++++++++++++++++++++++
+ arch/mips/mm/tlbex.c         |    4 ++++
+ include/asm-mips/cpu.h       |    7 +++++++
+ 3 files changed, 36 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
+index e621fda..9775315 100644
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -153,6 +153,10 @@ void __init check_wait(void)
+ 	case CPU_25KF:
+ 	case CPU_PR4450:
+ 	case CPU_BCM3302:
++	case CPU_BCM6338:
++	case CPU_BCM6345:
++	case CPU_BCM6348:
++	case CPU_BCM6358:
+ 		cpu_wait = r4k_wait;
+ 		break;
+ 
+@@ -802,11 +806,28 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
+ 	decode_configs(c);
+ 	switch (c->processor_id & 0xff00) {
+ 	case PRID_IMP_BCM3302:
++	/* same as PRID_IMP_BCM6338 */
+ 		c->cputype = CPU_BCM3302;
+ 		break;
+ 	case PRID_IMP_BCM4710:
+ 		c->cputype = CPU_BCM4710;
+ 		break;
++	case PRID_IMP_BCM6345:
++		c->cputype = CPU_BCM6345;
++		break;
++	case PRID_IMP_BCM6348:
++		c->cputype = CPU_BCM6348;
++		break;
++	case PRID_IMP_BCM4350:
++		switch (c->processor_id & 0xf0) {
++		case PRID_REV_BCM6358:
++			c->cputype = CPU_BCM6358;
++			break;
++		default:
++			c->cputype = CPU_UNKNOWN;
++			break;
++		}
++		break;
+ 	default:
+ 		c->cputype = CPU_UNKNOWN;
+ 		break;
+@@ -892,6 +913,10 @@ static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
+ 	case CPU_SR71000:	name = "Sandcraft SR71000"; break;
+ 	case CPU_BCM3302:	name = "Broadcom BCM3302"; break;
+ 	case CPU_BCM4710:	name = "Broadcom BCM4710"; break;
++	case CPU_BCM6338:	name = "Broadcom BCM6338"; break;
++	case CPU_BCM6345:	name = "Broadcom BCM6345"; break;
++	case CPU_BCM6348:	name = "Broadcom BCM6348"; break;
++	case CPU_BCM6358:	name = "Broadcom BCM6358"; break;
+ 	case CPU_PR4450:	name = "Philips PR4450"; break;
+ 	case CPU_LOONGSON2:	name = "ICT Loongson-2"; break;
+ 	default:
+diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
+index 979cf91..f6deda3 100644
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -317,6 +317,10 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
+ 	case CPU_BCM3302:
+ 	case CPU_BCM4710:
+ 	case CPU_LOONGSON2:
++	case CPU_BCM6338:
++	case CPU_BCM6345:
++	case CPU_BCM6348:
++	case CPU_BCM6358:
+ 		if (m4kc_tlbp_war())
+ 			uasm_i_nop(p);
+ 		tlbw(p);
+diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
+index 229a786..538bcde 100644
+--- a/include/asm-mips/cpu.h
++++ b/include/asm-mips/cpu.h
+@@ -112,6 +112,12 @@
+ 
+ #define PRID_IMP_BCM4710	0x4000
+ #define PRID_IMP_BCM3302	0x9000
++#define PRID_IMP_BCM6338	0x9000
++#define PRID_IMP_BCM6345	0x8000
++#define PRID_IMP_BCM6348	0x9100
++#define PRID_IMP_BCM4350	0xA000
++#define PRID_REV_BCM6358	0x0010
++#define PRID_REV_BCM6368	0x0030
+ 
+ /*
+  * Definitions for 7:0 on legacy processors
+@@ -198,6 +204,7 @@ enum cpu_type_enum {
+ 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+ 	CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
+ 	CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
++	CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
+ 
+ 	/*
+ 	 * MIPS64 class processors
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/002-add_support_for_broadcom_63xx_cpus.patch b/target/linux/brcm63xx/patches-2.6.27/002-add_support_for_broadcom_63xx_cpus.patch
new file mode 100644
index 0000000..64c9878
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/002-add_support_for_broadcom_63xx_cpus.patch
@@ -0,0 +1,2944 @@
+From 0713aadd2a4e543b69022aa40bdec3e1dc5bc1e5 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Mon, 18 Aug 2008 13:56:57 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add support for Broadcom 63xx CPUs.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/Kconfig                                  |   16 +
+ arch/mips/Makefile                                 |    7 +
+ arch/mips/bcm63xx/Kconfig                          |    9 +
+ arch/mips/bcm63xx/Makefile                         |    2 +
+ arch/mips/bcm63xx/clk.c                            |  220 ++++++
+ arch/mips/bcm63xx/cpu.c                            |  245 +++++++
+ arch/mips/bcm63xx/cs.c                             |  144 ++++
+ arch/mips/bcm63xx/early_printk.c                   |   30 +
+ arch/mips/bcm63xx/gpio.c                           |   98 +++
+ arch/mips/bcm63xx/irq.c                            |  253 +++++++
+ arch/mips/bcm63xx/prom.c                           |   43 ++
+ arch/mips/bcm63xx/setup.c                          |  108 +++
+ arch/mips/bcm63xx/timer.c                          |  205 ++++++
+ include/asm-mips/fixmap.h                          |    4 +
+ include/asm-mips/mach-bcm63xx/bcm63xx_clk.h        |   11 +
+ include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h        |  314 +++++++++
+ include/asm-mips/mach-bcm63xx/bcm63xx_cs.h         |   10 +
+ include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h       |   14 +
+ include/asm-mips/mach-bcm63xx/bcm63xx_io.h         |   93 +++
+ include/asm-mips/mach-bcm63xx/bcm63xx_irq.h        |   15 +
+ include/asm-mips/mach-bcm63xx/bcm63xx_regs.h       |  728 ++++++++++++++++++++
+ include/asm-mips/mach-bcm63xx/bcm63xx_timer.h      |   11 +
+ .../asm-mips/mach-bcm63xx/cpu-feature-overrides.h  |   51 ++
+ include/asm-mips/mach-bcm63xx/gpio.h               |   52 ++
+ include/asm-mips/mach-bcm63xx/war.h                |   25 +
+ 25 files changed, 2708 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/Kconfig
+ create mode 100644 arch/mips/bcm63xx/Makefile
+ create mode 100644 arch/mips/bcm63xx/clk.c
+ create mode 100644 arch/mips/bcm63xx/cpu.c
+ create mode 100644 arch/mips/bcm63xx/cs.c
+ create mode 100644 arch/mips/bcm63xx/early_printk.c
+ create mode 100644 arch/mips/bcm63xx/gpio.c
+ create mode 100644 arch/mips/bcm63xx/irq.c
+ create mode 100644 arch/mips/bcm63xx/prom.c
+ create mode 100644 arch/mips/bcm63xx/setup.c
+ create mode 100644 arch/mips/bcm63xx/timer.c
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_io.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/gpio.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/war.h
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 1e06d23..88dfe21 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -59,6 +59,21 @@ config BCM47XX
+ 	help
+ 	 Support for BCM47XX based boards
+ 
++config BCM63XX
++	bool "Broadcom 63xx based boards"
++	select CEVT_R4K
++	select CSRC_R4K
++	select DMA_NONCOHERENT
++	select IRQ_CPU
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_BIG_ENDIAN
++	select SYS_HAS_EARLY_PRINTK
++	select SWAP_IO_SPACE
++	select GENERIC_GPIO
++	help
++	 Support for BCM63XX based boards
++
+ config MIPS_COBALT
+ 	bool "Cobalt Server"
+ 	select CEVT_R4K
+@@ -600,6 +615,7 @@ endchoice
+ 
+ source "arch/mips/au1000/Kconfig"
+ source "arch/mips/basler/excite/Kconfig"
++source "arch/mips/bcm63xx/Kconfig"
+ source "arch/mips/jazz/Kconfig"
+ source "arch/mips/lasat/Kconfig"
+ source "arch/mips/pmc-sierra/Kconfig"
+diff --git a/arch/mips/Makefile b/arch/mips/Makefile
+index 9aab51c..a45652e 100644
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -533,6 +533,13 @@ cflags-$(CONFIG_BCM47XX)	+= -Iinclude/asm-mips/mach-bcm47xx
+ load-$(CONFIG_BCM47XX)		:= 0xffffffff80001000
+ 
+ #
++# Broadcom BCM63XX boards
++#
++core-$(CONFIG_BCM63XX)		+= arch/mips/bcm63xx/
++cflags-$(CONFIG_BCM63XX)	+= -Iinclude/asm-mips/mach-bcm63xx/
++load-$(CONFIG_BCM63XX)		:= 0xffffffff80010000
++
++#
+ # SNI RM
+ #
+ core-$(CONFIG_SNI_RM)		+= arch/mips/sni/
+diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
+new file mode 100644
+index 0000000..e6d2699
+--- /dev/null
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -0,0 +1,9 @@
++menu "CPU support"
++	depends on BCM63XX
++
++config BCM63XX_CPU_6348
++	bool "support 6348 CPU"
++
++config BCM63XX_CPU_6358
++	bool "support 6358 CPU"
++endmenu
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+new file mode 100644
+index 0000000..4fc0a1c
+--- /dev/null
++++ b/arch/mips/bcm63xx/Makefile
+@@ -0,0 +1,2 @@
++obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
++obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
+new file mode 100644
+index 0000000..ae1f41f
+--- /dev/null
++++ b/arch/mips/bcm63xx/clk.c
+@@ -0,0 +1,220 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_clk.h>
++
++DEFINE_MUTEX(clocks_mutex);
++
++
++static void clk_enable_unlocked(struct clk *clk)
++{
++	if (clk->set && (clk->usage++) == 0)
++		clk->set(clk, 1);
++}
++
++static void clk_disable_unlocked(struct clk *clk)
++{
++	if (clk->set && (--clk->usage) == 0)
++		clk->set(clk, 0);
++}
++
++static void bcm_hwclock_set(u32 mask, int enable)
++{
++	u32 reg;
++
++	reg = bcm_perf_readl(PERF_CKCTL_REG);
++	if (enable)
++		reg |= mask;
++	else
++		reg &= ~mask;
++	bcm_perf_writel(reg, PERF_CKCTL_REG);
++}
++
++/*
++ * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
++ */
++static void enet_misc_set(struct clk *clk, int enable)
++{
++	u32 mask;
++
++	if (BCMCPU_IS_6348())
++		mask = CKCTL_6348_ENET_EN;
++	else
++		/* BCMCPU_IS_6358 */
++		mask = CKCTL_6358_EMUSB_EN;
++	bcm_hwclock_set(mask, enable);
++}
++
++static struct clk clk_enet_misc = {
++	.set	= enet_misc_set,
++};
++
++/*
++ * Ethernet MAC clocks: only revelant on 6358, silently enable misc
++ * clocks
++ */
++static void enetx_set(struct clk *clk, int enable)
++{
++	if (enable)
++		clk_enable_unlocked(&clk_enet_misc);
++	else
++		clk_disable_unlocked(&clk_enet_misc);
++
++	if (BCMCPU_IS_6358()) {
++		u32 mask;
++
++		if (clk->id == 0)
++			mask = CKCTL_6358_ENET0_EN;
++		else
++			mask = CKCTL_6358_ENET1_EN;
++		bcm_hwclock_set(mask, enable);
++	}
++}
++
++static struct clk clk_enet0 = {
++	.id	= 0,
++	.set	= enetx_set,
++};
++
++static struct clk clk_enet1 = {
++	.id	= 1,
++	.set	= enetx_set,
++};
++
++/*
++ * Ethernet PHY clock
++ */
++static void ephy_set(struct clk *clk, int enable)
++{
++	if (!BCMCPU_IS_6358())
++		return;
++	bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
++}
++
++
++static struct clk clk_ephy = {
++	.set	= ephy_set,
++};
++
++/*
++ * PCM clock
++ */
++static void pcm_set(struct clk *clk, int enable)
++{
++	if (!BCMCPU_IS_6358())
++		return;
++	bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
++}
++
++static struct clk clk_pcm = {
++	.set	= pcm_set,
++};
++
++/*
++ * USB host clock
++ */
++static void usbh_set(struct clk *clk, int enable)
++{
++	if (!BCMCPU_IS_6348())
++		return;
++	bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
++}
++
++static struct clk clk_usbh = {
++	.set	= usbh_set,
++};
++
++/*
++ * SPI clock
++ */
++static void spi_set(struct clk *clk, int enable)
++{
++	u32 mask;
++
++	if (BCMCPU_IS_6348())
++		mask = CKCTL_6348_SPI_EN;
++	else
++		/* BCMCPU_IS_6358 */
++		mask = CKCTL_6358_SPI_EN;
++	bcm_hwclock_set(mask, enable);
++}
++
++static struct clk clk_spi = {
++	.set	= spi_set,
++};
++
++/*
++ * Internal peripheral clock
++ */
++static struct clk clk_periph = {
++	.rate	= (50 * 1000 * 1000),
++};
++
++
++/*
++ * Linux clock API implementation
++ */
++int clk_enable(struct clk *clk)
++{
++	mutex_lock(&clocks_mutex);
++	clk_enable_unlocked(clk);
++	mutex_unlock(&clocks_mutex);
++	return 0;
++}
++
++EXPORT_SYMBOL(clk_enable);
++
++void clk_disable(struct clk *clk)
++{
++	mutex_lock(&clocks_mutex);
++	clk_disable_unlocked(clk);
++	mutex_unlock(&clocks_mutex);
++}
++
++EXPORT_SYMBOL(clk_disable);
++
++unsigned long clk_get_rate(struct clk *clk)
++{
++	return clk->rate;
++}
++
++EXPORT_SYMBOL(clk_get_rate);
++
++struct clk *clk_get(struct device *dev, const char *id)
++{
++	if (!strcmp(id, "enet0"))
++		return &clk_enet0;
++	if (!strcmp(id, "enet1"))
++		return &clk_enet1;
++	if (!strcmp(id, "ephy"))
++		return &clk_ephy;
++	if (!strcmp(id, "usbh"))
++		return &clk_usbh;
++	if (!strcmp(id, "spi"))
++		return &clk_spi;
++	if (!strcmp(id, "periph"))
++		return &clk_periph;
++	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
++		return &clk_pcm;
++	return ERR_PTR(-ENOENT);
++}
++
++EXPORT_SYMBOL(clk_get);
++
++void clk_put(struct clk *clk)
++{
++}
++
++EXPORT_SYMBOL(clk_put);
+diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
+new file mode 100644
+index 0000000..0a403dd
+--- /dev/null
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -0,0 +1,245 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/cpu.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_irq.h>
++
++const unsigned long *bcm63xx_regs_base;
++EXPORT_SYMBOL(bcm63xx_regs_base);
++
++const int *bcm63xx_irqs;
++EXPORT_SYMBOL(bcm63xx_irqs);
++
++static u16 bcm63xx_cpu_id;
++static u16 bcm63xx_cpu_rev;
++static unsigned int bcm63xx_cpu_freq;
++static unsigned int bcm63xx_memory_size;
++
++/*
++ * 6348 register sets and irqs
++ */
++static const unsigned long bcm96348_regs_base[] = {
++	[RSET_DSL_LMEM]		= BCM_6348_DSL_LMEM_BASE,
++	[RSET_PERF]		= BCM_6348_PERF_BASE,
++	[RSET_TIMER]		= BCM_6348_TIMER_BASE,
++	[RSET_WDT]		= BCM_6348_WDT_BASE,
++	[RSET_UART0]		= BCM_6348_UART0_BASE,
++	[RSET_GPIO]		= BCM_6348_GPIO_BASE,
++	[RSET_SPI]		= BCM_6348_SPI_BASE,
++	[RSET_OHCI0]		= BCM_6348_OHCI0_BASE,
++	[RSET_OHCI_PRIV]	= BCM_6348_OHCI_PRIV_BASE,
++	[RSET_USBH_PRIV]	= BCM_6348_USBH_PRIV_BASE,
++	[RSET_MPI]		= BCM_6348_MPI_BASE,
++	[RSET_PCMCIA]		= BCM_6348_PCMCIA_BASE,
++	[RSET_SDRAM]		= BCM_6348_SDRAM_BASE,
++	[RSET_DSL]		= BCM_6348_DSL_BASE,
++	[RSET_ENET0]		= BCM_6348_ENET0_BASE,
++	[RSET_ENET1]		= BCM_6348_ENET1_BASE,
++	[RSET_ENETDMA]		= BCM_6348_ENETDMA_BASE,
++	[RSET_MEMC]		= BCM_6348_MEMC_BASE,
++	[RSET_DDR]		= BCM_6348_DDR_BASE,
++};
++
++static const int bcm96348_irqs[] = {
++	[IRQ_TIMER]		= BCM_6348_TIMER_IRQ,
++	[IRQ_UART0]		= BCM_6348_UART0_IRQ,
++	[IRQ_DSL]		= BCM_6348_DSL_IRQ,
++	[IRQ_ENET0]		= BCM_6348_ENET0_IRQ,
++	[IRQ_ENET1]		= BCM_6348_ENET1_IRQ,
++	[IRQ_ENET_PHY]		= BCM_6348_ENET_PHY_IRQ,
++	[IRQ_OHCI0]		= BCM_6348_OHCI0_IRQ,
++	[IRQ_PCMCIA]		= BCM_6348_PCMCIA_IRQ,
++	[IRQ_ENET0_RXDMA]	= BCM_6348_ENET0_RXDMA_IRQ,
++	[IRQ_ENET0_TXDMA]	= BCM_6348_ENET0_TXDMA_IRQ,
++	[IRQ_ENET1_RXDMA]	= BCM_6348_ENET1_RXDMA_IRQ,
++	[IRQ_ENET1_TXDMA]	= BCM_6348_ENET1_TXDMA_IRQ,
++	[IRQ_PCI]		= BCM_6348_PCI_IRQ,
++};
++
++/*
++ * 6358 register sets and irqs
++ */
++static const unsigned long bcm96358_regs_base[] = {
++	[RSET_DSL_LMEM]		= BCM_6358_DSL_LMEM_BASE,
++	[RSET_PERF]		= BCM_6358_PERF_BASE,
++	[RSET_TIMER]		= BCM_6358_TIMER_BASE,
++	[RSET_WDT]		= BCM_6358_WDT_BASE,
++	[RSET_UART0]		= BCM_6358_UART0_BASE,
++	[RSET_GPIO]		= BCM_6358_GPIO_BASE,
++	[RSET_SPI]		= BCM_6358_SPI_BASE,
++	[RSET_OHCI0]		= BCM_6358_OHCI0_BASE,
++	[RSET_EHCI0]		= BCM_6358_EHCI0_BASE,
++	[RSET_OHCI_PRIV]	= BCM_6358_OHCI_PRIV_BASE,
++	[RSET_USBH_PRIV]	= BCM_6358_USBH_PRIV_BASE,
++	[RSET_MPI]		= BCM_6358_MPI_BASE,
++	[RSET_PCMCIA]		= BCM_6358_PCMCIA_BASE,
++	[RSET_SDRAM]		= BCM_6358_SDRAM_BASE,
++	[RSET_DSL]		= BCM_6358_DSL_BASE,
++	[RSET_ENET0]		= BCM_6358_ENET0_BASE,
++	[RSET_ENET1]		= BCM_6358_ENET1_BASE,
++	[RSET_ENETDMA]		= BCM_6358_ENETDMA_BASE,
++	[RSET_MEMC]		= BCM_6358_MEMC_BASE,
++	[RSET_DDR]		= BCM_6358_DDR_BASE,
++};
++
++static const int bcm96358_irqs[] = {
++	[IRQ_TIMER]		= BCM_6358_TIMER_IRQ,
++	[IRQ_UART0]		= BCM_6358_UART0_IRQ,
++	[IRQ_DSL]		= BCM_6358_DSL_IRQ,
++	[IRQ_ENET0]		= BCM_6358_ENET0_IRQ,
++	[IRQ_ENET1]		= BCM_6358_ENET1_IRQ,
++	[IRQ_ENET_PHY]		= BCM_6358_ENET_PHY_IRQ,
++	[IRQ_OHCI0]		= BCM_6358_OHCI0_IRQ,
++	[IRQ_EHCI0]		= BCM_6358_EHCI0_IRQ,
++	[IRQ_PCMCIA]		= BCM_6358_PCMCIA_IRQ,
++	[IRQ_ENET0_RXDMA]	= BCM_6358_ENET0_RXDMA_IRQ,
++	[IRQ_ENET0_TXDMA]	= BCM_6358_ENET0_TXDMA_IRQ,
++	[IRQ_ENET1_RXDMA]	= BCM_6358_ENET1_RXDMA_IRQ,
++	[IRQ_ENET1_TXDMA]	= BCM_6358_ENET1_TXDMA_IRQ,
++	[IRQ_PCI]		= BCM_6358_PCI_IRQ,
++};
++
++u16 __bcm63xx_get_cpu_id(void)
++{
++	return bcm63xx_cpu_id;
++}
++
++EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
++
++u16 bcm63xx_get_cpu_rev(void)
++{
++	return bcm63xx_cpu_rev;
++}
++
++EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
++
++unsigned int bcm63xx_get_cpu_freq(void)
++{
++	return bcm63xx_cpu_freq;
++}
++
++unsigned int bcm63xx_get_memory_size(void)
++{
++	return bcm63xx_memory_size;
++}
++
++static unsigned int detect_cpu_clock(void)
++{
++	unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
++
++	/*
++	 * frequency depends on PLL configuration:
++	 */
++	if (BCMCPU_IS_6348()) {
++		/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
++		tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
++		n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
++		n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
++		m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
++		n1 += 1;
++		n2 += 2;
++		m1 += 1;
++	}
++
++	if (BCMCPU_IS_6358()) {
++		/* 16MHz * N1 * N2 / M1_CPU */
++		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
++		n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
++		n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
++		m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
++	}
++
++	return (16 * 1000000 * n1 * n2) / m1;
++}
++
++/*
++ * attempt to detect the amount of memory installed
++ */
++static unsigned int detect_memory_size(void)
++{
++	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
++	u32 val;
++
++	if (BCMCPU_IS_6348()) {
++		val = bcm_sdram_readl(SDRAM_CFG_REG);
++		rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
++		cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
++		is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
++		banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
++	}
++
++	if (BCMCPU_IS_6358()) {
++		val = bcm_memc_readl(MEMC_CFG_REG);
++		rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
++		cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
++		is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
++		banks = 2;
++	}
++
++	/* 0 => 11 address bits ... 2 => 13 address bits */
++	rows += 11;
++
++	/* 0 => 8 address bits ... 2 => 10 address bits */
++	cols += 8;
++
++	return 1 << (cols + rows + (is_32bits + 1) + banks);
++}
++
++void __init bcm63xx_cpu_init(void)
++{
++	unsigned int tmp, expected_cpu_id;
++	struct cpuinfo_mips *c = &current_cpu_data;
++
++	/* soc registers location depends on cpu type */
++	expected_cpu_id = 0;
++
++	switch (c->cputype) {
++	case CPU_BCM6348:
++		expected_cpu_id = BCM6348_CPU_ID;
++		bcm63xx_regs_base = bcm96348_regs_base;
++		bcm63xx_irqs = bcm96348_irqs;
++		break;
++	case CPU_BCM6358:
++		expected_cpu_id = BCM6358_CPU_ID;
++		bcm63xx_regs_base = bcm96358_regs_base;
++		bcm63xx_irqs = bcm96358_irqs;
++		break;
++	}
++
++	/* really early to panic, but delaying panic would not help
++	 * since we will never get any working console */
++	if (!expected_cpu_id)
++		panic("unsupported Broadcom CPU");
++
++	/*
++	 * bcm63xx_regs_base is set, we can access soc registers
++	 */
++
++	/* double check CPU type */
++	tmp = bcm_perf_readl(PERF_REV_REG);
++	bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
++	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
++
++	if (bcm63xx_cpu_id != expected_cpu_id)
++		panic("bcm63xx CPU id mismatch");
++
++	bcm63xx_cpu_freq = detect_cpu_clock();
++	bcm63xx_memory_size = detect_memory_size();
++
++	printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
++	       bcm63xx_cpu_id, bcm63xx_cpu_rev);
++	printk(KERN_INFO "CPU frequency is %u MHz\n",
++	       bcm63xx_cpu_freq);
++	printk(KERN_INFO "%uMB of RAM installed\n",
++	       bcm63xx_memory_size >> 20);
++}
+diff --git a/arch/mips/bcm63xx/cs.c b/arch/mips/bcm63xx/cs.c
+new file mode 100644
+index 0000000..50d8190
+--- /dev/null
++++ b/arch/mips/bcm63xx/cs.c
+@@ -0,0 +1,144 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/log2.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_cs.h>
++
++static DEFINE_SPINLOCK(bcm63xx_cs_lock);
++
++/*
++ * check if given chip select exists
++ */
++static int is_valid_cs(unsigned int cs)
++{
++	if (cs > 6)
++		return 0;
++	return 1;
++}
++
++/*
++ * Configure chipselect base address and size (bytes).
++ * Size must be a power of two between 8k and 256M.
++ */
++int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
++{
++	unsigned long flags;
++	u32 val;
++
++	if (!is_valid_cs(cs))
++		return -EINVAL;
++
++	/* sanity check on size */
++	if (size != roundup_pow_of_two(size))
++		return -EINVAL;
++
++	if (size < 8 * 1024 || size > 256 * 1024 * 1024)
++		return -EINVAL;
++
++	val = (base & MPI_CSBASE_BASE_MASK);
++	/* 8k => 0 - 256M => 15 */
++	val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
++
++	spin_lock_irqsave(&bcm63xx_cs_lock, flags);
++	bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
++	spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_set_cs_base);
++
++/*
++ * configure chipselect timing (ns)
++ */
++int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
++			   unsigned int setup, unsigned int hold)
++{
++	unsigned long flags;
++	u32 val;
++
++	if (!is_valid_cs(cs))
++		return -EINVAL;
++
++	spin_lock_irqsave(&bcm63xx_cs_lock, flags);
++	val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
++	val &= ~(MPI_CSCTL_WAIT_MASK);
++	val &= ~(MPI_CSCTL_SETUP_MASK);
++	val &= ~(MPI_CSCTL_HOLD_MASK);
++	val |= wait << MPI_CSCTL_WAIT_SHIFT;
++	val |= setup << MPI_CSCTL_SETUP_SHIFT;
++	val |= hold << MPI_CSCTL_HOLD_SHIFT;
++	bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
++	spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_set_cs_timing);
++
++/*
++ * configure other chipselect parameter (data bus size, ...)
++ */
++int bcm63xx_set_cs_param(unsigned int cs, u32 params)
++{
++	unsigned long flags;
++	u32 val;
++
++	if (!is_valid_cs(cs))
++		return -EINVAL;
++
++	/* none of this fields apply to pcmcia */
++	if (cs == MPI_CS_PCMCIA_COMMON ||
++	    cs == MPI_CS_PCMCIA_ATTR ||
++	    cs == MPI_CS_PCMCIA_IO)
++		return -EINVAL;
++
++	spin_lock_irqsave(&bcm63xx_cs_lock, flags);
++	val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
++	val &= ~(MPI_CSCTL_DATA16_MASK);
++	val &= ~(MPI_CSCTL_SYNCMODE_MASK);
++	val &= ~(MPI_CSCTL_TSIZE_MASK);
++	val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
++	val |= params;
++	bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
++	spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_set_cs_param);
++
++/*
++ * set cs status (enable/disable)
++ */
++int bcm63xx_set_cs_status(unsigned int cs, int enable)
++{
++	unsigned long flags;
++	u32 val;
++
++	if (!is_valid_cs(cs))
++		return -EINVAL;
++
++	spin_lock_irqsave(&bcm63xx_cs_lock, flags);
++	val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
++	if (enable)
++		val |= MPI_CSCTL_ENABLE_MASK;
++	else
++		val &= ~MPI_CSCTL_ENABLE_MASK;
++	bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
++	spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_set_cs_status);
+diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
+new file mode 100644
+index 0000000..bf353c9
+--- /dev/null
++++ b/arch/mips/bcm63xx/early_printk.c
+@@ -0,0 +1,30 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++static void __init wait_xfered(void)
++{
++	unsigned int val;
++
++	/* wait for any previous char to be transmitted */
++	do {
++		val = bcm_uart0_readl(UART_IR_REG);
++		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
++			break;
++	} while (1);
++}
++
++void __init prom_putchar(char c)
++{
++	wait_xfered();
++	bcm_uart0_writel(c, UART_FIFO_REG);
++	wait_xfered();
++}
+diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
+new file mode 100644
+index 0000000..2c203a6
+--- /dev/null
++++ b/arch/mips/bcm63xx/gpio.c
+@@ -0,0 +1,98 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_gpio.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
++
++void bcm63xx_gpio_set_dataout(int gpio, int val)
++{
++	u32 reg;
++	u32 mask;
++	u32 tmp;
++	unsigned long flags;
++
++	if (gpio >= BCM63XX_GPIO_COUNT)
++		BUG();
++
++	if (gpio < 32) {
++		reg = GPIO_DATA_LO_REG;
++		mask = 1 << gpio;
++	} else {
++		reg = GPIO_DATA_HI_REG;
++		mask = 1 << (gpio - 32);
++	}
++
++	spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
++	tmp = bcm_gpio_readl(reg);
++	if (val)
++		tmp |= mask;
++	else
++		tmp &= ~mask;
++	bcm_gpio_writel(tmp, reg);
++	spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
++}
++
++EXPORT_SYMBOL(bcm63xx_gpio_set_dataout);
++
++int bcm63xx_gpio_get_datain(int gpio)
++{
++	u32 reg;
++	u32 mask;
++
++	if (gpio >= BCM63XX_GPIO_COUNT)
++		BUG();
++
++	if (gpio < 32) {
++		reg = GPIO_DATA_LO_REG;
++		mask = 1 << gpio;
++	} else {
++		reg = GPIO_DATA_HI_REG;
++		mask = 1 << (gpio - 32);
++	}
++
++	return !!(bcm_gpio_readl(reg) & mask);
++}
++
++EXPORT_SYMBOL(bcm63xx_gpio_get_datain);
++
++void bcm63xx_gpio_set_direction(int gpio, int dir)
++{
++	u32 reg;
++	u32 mask;
++	u32 tmp;
++	unsigned long flags;
++
++	if (gpio >= BCM63XX_GPIO_COUNT)
++		BUG();
++
++	if (gpio < 32) {
++		reg = GPIO_CTL_LO_REG;
++		mask = 1 << gpio;
++	} else {
++		reg = GPIO_CTL_HI_REG;
++		mask = 1 << (gpio - 32);
++	}
++
++	spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
++	tmp = bcm_gpio_readl(reg);
++	if (dir == GPIO_DIR_IN)
++		tmp &= ~mask;
++	else
++		tmp |= mask;
++	bcm_gpio_writel(tmp, reg);
++	spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
++}
++
++EXPORT_SYMBOL(bcm63xx_gpio_set_direction);
+diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
+new file mode 100644
+index 0000000..a0c5cd1
+--- /dev/null
++++ b/arch/mips/bcm63xx/irq.c
+@@ -0,0 +1,253 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <asm/irq_cpu.h>
++#include <asm/mipsregs.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_irq.h>
++
++/*
++ * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
++ * prioritize any interrupt relatively to another. the static counter
++ * will resume the loop where it ended the last time we left this
++ * function.
++ */
++static void bcm63xx_irq_dispatch_internal(void)
++{
++	u32 pending;
++	static int i;
++
++	pending = bcm_perf_readl(PERF_IRQMASK_REG) &
++		bcm_perf_readl(PERF_IRQSTAT_REG);
++
++	if (!pending)
++		return ;
++
++	while (1) {
++		int to_call = i;
++
++		i = (i + 1) & 0x1f;
++		if (pending & (1 << to_call)) {
++			do_IRQ(to_call + IRQ_INTERNAL_BASE);
++			break;
++		}
++	}
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++	u32 cause;
++
++	do {
++		cause = read_c0_cause() & read_c0_status() & ST0_IM;
++
++		if (!cause)
++			break;
++
++		if (cause & CAUSEF_IP7)
++			do_IRQ(7);
++		if (cause & CAUSEF_IP2)
++			bcm63xx_irq_dispatch_internal();
++		if (cause & CAUSEF_IP3)
++			do_IRQ(IRQ_EXT_0);
++		if (cause & CAUSEF_IP4)
++			do_IRQ(IRQ_EXT_1);
++		if (cause & CAUSEF_IP5)
++			do_IRQ(IRQ_EXT_2);
++		if (cause & CAUSEF_IP6)
++			do_IRQ(IRQ_EXT_3);
++	} while (1);
++}
++
++/*
++ * internal IRQs operations: only mask/unmask on PERF irq mask
++ * register.
++ */
++static inline void bcm63xx_internal_irq_mask(unsigned int irq)
++{
++	u32 mask;
++
++	irq -= IRQ_INTERNAL_BASE;
++	mask = bcm_perf_readl(PERF_IRQMASK_REG);
++	mask &= ~(1 << irq);
++	bcm_perf_writel(mask, PERF_IRQMASK_REG);
++}
++
++static void bcm63xx_internal_irq_unmask(unsigned int irq)
++{
++	u32 mask;
++
++	irq -= IRQ_INTERNAL_BASE;
++	mask = bcm_perf_readl(PERF_IRQMASK_REG);
++	mask |= (1 << irq);
++	bcm_perf_writel(mask, PERF_IRQMASK_REG);
++}
++
++static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
++{
++	bcm63xx_internal_irq_unmask(irq);
++	return 0;
++}
++
++/*
++ * external IRQs operations: mask/unmask and clear on PERF external
++ * irq control register.
++ */
++static void bcm63xx_external_irq_mask(unsigned int irq)
++{
++	u32 reg;
++
++	irq -= IRQ_EXT_BASE;
++	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
++	reg &= ~EXTIRQ_CFG_MASK(irq);
++	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
++}
++
++static void bcm63xx_external_irq_unmask(unsigned int irq)
++{
++	u32 reg;
++
++	irq -= IRQ_EXT_BASE;
++	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
++	reg |= EXTIRQ_CFG_MASK(irq);
++	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
++}
++
++static void bcm63xx_external_irq_clear(unsigned int irq)
++{
++	u32 reg;
++
++	irq -= IRQ_EXT_BASE;
++	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
++	reg |= EXTIRQ_CFG_CLEAR(irq);
++	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
++}
++
++static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
++{
++	set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
++	irq_enable_hazard();
++	bcm63xx_external_irq_unmask(irq);
++	return 0;
++}
++
++static void bcm63xx_external_irq_shutdown(unsigned int irq)
++{
++	bcm63xx_external_irq_mask(irq);
++	clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
++	irq_disable_hazard();
++}
++
++static int bcm63xx_external_irq_set_type(unsigned int irq,
++					 unsigned int flow_type)
++{
++	u32 reg;
++	struct irq_desc *desc = irq_desc + irq;
++
++	irq -= IRQ_EXT_BASE;
++
++	flow_type &= IRQ_TYPE_SENSE_MASK;
++
++	if (flow_type == IRQ_TYPE_NONE)
++		flow_type = IRQ_TYPE_LEVEL_LOW;
++
++	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
++	switch (flow_type) {
++	case IRQ_TYPE_EDGE_BOTH:
++		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
++		reg |= EXTIRQ_CFG_BOTHEDGE(irq);
++		break;
++
++	case IRQ_TYPE_EDGE_RISING:
++		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
++		reg |= EXTIRQ_CFG_SENSE(irq);
++		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
++		break;
++
++	case IRQ_TYPE_EDGE_FALLING:
++		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
++		reg &= ~EXTIRQ_CFG_SENSE(irq);
++		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
++		break;
++
++	case IRQ_TYPE_LEVEL_HIGH:
++		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
++		reg |= EXTIRQ_CFG_SENSE(irq);
++		break;
++
++	case IRQ_TYPE_LEVEL_LOW:
++		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
++		reg &= ~EXTIRQ_CFG_SENSE(irq);
++		break;
++
++	default:
++		printk(KERN_ERR "bogus flow type combination given !\n");
++		return -EINVAL;
++	}
++	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
++
++	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))  {
++		desc->status |= IRQ_LEVEL;
++		desc->handle_irq = handle_level_irq;
++	} else {
++		desc->handle_irq = handle_edge_irq;
++	}
++
++	return 0;
++}
++
++static struct irq_chip bcm63xx_internal_irq_chip = {
++	.name		= "bcm63xx_ipic",
++	.startup	= bcm63xx_internal_irq_startup,
++	.shutdown	= bcm63xx_internal_irq_mask,
++
++	.mask		= bcm63xx_internal_irq_mask,
++	.mask_ack	= bcm63xx_internal_irq_mask,
++	.unmask		= bcm63xx_internal_irq_unmask,
++};
++
++static struct irq_chip bcm63xx_external_irq_chip = {
++	.name		= "bcm63xx_epic",
++	.startup	= bcm63xx_external_irq_startup,
++	.shutdown	= bcm63xx_external_irq_shutdown,
++
++	.ack		= bcm63xx_external_irq_clear,
++
++	.mask		= bcm63xx_external_irq_mask,
++	.unmask		= bcm63xx_external_irq_unmask,
++
++	.set_type	= bcm63xx_external_irq_set_type,
++};
++
++static struct irqaction cpu_ip2_cascade_action = {
++	.handler	= no_action,
++	.name		= "cascade_ip2",
++};
++
++void __init arch_init_irq(void)
++{
++	int i;
++
++	mips_cpu_irq_init();
++	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
++		set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
++					 handle_level_irq);
++
++	for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
++		set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
++					 handle_edge_irq);
++
++	setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
++}
+diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
+new file mode 100644
+index 0000000..f0b49e8
+--- /dev/null
++++ b/arch/mips/bcm63xx/prom.c
+@@ -0,0 +1,43 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/bootmem.h>
++#include <asm/bootinfo.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++void __init prom_init(void)
++{
++	u32 reg, mask;
++
++	bcm63xx_cpu_init();
++
++	/* stop any running watchdog */
++	bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
++	bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
++
++	/* disable all hardware blocks clock for now */
++	if (BCMCPU_IS_6348())
++		mask = CKCTL_6348_ALL_SAFE_EN;
++	else
++		/* BCMCPU_IS_6358() */
++		mask = CKCTL_6358_ALL_SAFE_EN;
++
++	reg = bcm_perf_readl(PERF_CKCTL_REG);
++	reg &= ~mask;
++	bcm_perf_writel(reg, PERF_CKCTL_REG);
++
++	/* assign command line from kernel config */
++	strcpy(arcs_cmdline, CONFIG_CMDLINE);
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
+diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
+new file mode 100644
+index 0000000..55c51a9
+--- /dev/null
++++ b/arch/mips/bcm63xx/setup.c
+@@ -0,0 +1,108 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/bootmem.h>
++#include <linux/ioport.h>
++#include <linux/pm.h>
++#include <asm/bootinfo.h>
++#include <asm/time.h>
++#include <asm/reboot.h>
++#include <asm/cacheflush.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++
++void bcm63xx_machine_halt(void)
++{
++	printk(KERN_INFO "System halted\n");
++	while (1);
++}
++
++static void bcm6348_a1_reboot(void)
++{
++	u32 reg;
++
++	/* soft reset all blocks */
++	printk(KERN_INFO "soft-reseting all blocks ...\n");
++	reg = bcm_perf_readl(PERF_SOFTRESET_REG);
++	reg &= ~SOFTRESET_6348_ALL;
++	bcm_perf_writel(reg, PERF_SOFTRESET_REG);
++	mdelay(10);
++
++	reg = bcm_perf_readl(PERF_SOFTRESET_REG);
++	reg |= SOFTRESET_6348_ALL;
++	bcm_perf_writel(reg, PERF_SOFTRESET_REG);
++	mdelay(10);
++
++	/* Jump to the power on address. */
++	printk(KERN_INFO "jumping to reset vector.\n");
++	/* set high vectors (base at 0xbfc00000 */
++	set_c0_status(ST0_BEV | ST0_ERL);
++	/* run uncached in kseg0 */
++	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
++	__flush_cache_all();
++	/* remove all wired TLB entries */
++	write_c0_wired(0);
++	__asm__ __volatile__(
++		"jr\t%0"
++		:
++		: "r" (0xbfc00000));
++	while (1);
++}
++
++void bcm63xx_machine_reboot(void)
++{
++	u32 reg;
++
++	/* mask and clear all external irq */
++	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
++	reg &= ~EXTIRQ_CFG_MASK_ALL;
++	reg |= EXTIRQ_CFG_CLEAR_ALL;
++	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
++
++	if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
++		bcm6348_a1_reboot();
++
++	printk(KERN_INFO "triggering watchdog soft-reset...\n");
++	bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
++	while (1);
++}
++
++static void __bcm63xx_machine_reboot(char *p)
++{
++	bcm63xx_machine_reboot();
++}
++
++/*
++ * return system type in /proc/cpuinfo
++ */
++const char *get_system_type(void)
++{
++	static char buf[128];
++	sprintf(buf, "bcm963xx (0x%04x/0x%04X)",
++		bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
++	return buf;
++}
++
++void __init plat_time_init(void)
++{
++	mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
++}
++void __init plat_mem_setup(void)
++{
++	add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
++
++	_machine_halt = bcm63xx_machine_halt;
++	_machine_restart = __bcm63xx_machine_reboot;
++	pm_power_off = bcm63xx_machine_halt;
++
++	set_io_port_base(0);
++}
+diff --git a/arch/mips/bcm63xx/timer.c b/arch/mips/bcm63xx/timer.c
+new file mode 100644
+index 0000000..ba522bd
+--- /dev/null
++++ b/arch/mips/bcm63xx/timer.c
+@@ -0,0 +1,205 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_timer.h>
++#include <bcm63xx_regs.h>
++
++static DEFINE_SPINLOCK(timer_reg_lock);
++static DEFINE_SPINLOCK(timer_data_lock);
++static struct clk *periph_clk;
++
++static struct timer_data {
++	void	(*cb)(void *);
++	void	*data;
++} timer_data[BCM63XX_TIMER_COUNT];
++
++static irqreturn_t timer_interrupt(int irq, void *dev_id)
++{
++	u32 stat;
++	int i;
++
++	spin_lock(&timer_reg_lock);
++	stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
++	bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
++	spin_unlock(&timer_reg_lock);
++
++	for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
++		if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
++			continue;
++
++		spin_lock(&timer_data_lock);
++		if (!timer_data[i].cb) {
++			spin_unlock(&timer_data_lock);
++			continue;
++		}
++
++		timer_data[i].cb(timer_data[i].data);
++		spin_unlock(&timer_data_lock);
++	}
++
++	return IRQ_HANDLED;
++}
++
++int bcm63xx_timer_enable(int id)
++{
++	u32 reg;
++	unsigned long flags;
++
++	if (id >= BCM63XX_TIMER_COUNT)
++		return -EINVAL;
++
++	spin_lock_irqsave(&timer_reg_lock, flags);
++
++	reg = bcm_timer_readl(TIMER_CTLx_REG(id));
++	reg |= TIMER_CTL_ENABLE_MASK;
++	bcm_timer_writel(reg, TIMER_CTLx_REG(id));
++
++	reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
++	reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
++	bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
++
++	spin_unlock_irqrestore(&timer_reg_lock, flags);
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_enable);
++
++int bcm63xx_timer_disable(int id)
++{
++	u32 reg;
++	unsigned long flags;
++
++	if (id >= BCM63XX_TIMER_COUNT)
++		return -EINVAL;
++
++	spin_lock_irqsave(&timer_reg_lock, flags);
++
++	reg = bcm_timer_readl(TIMER_CTLx_REG(id));
++	reg &= ~TIMER_CTL_ENABLE_MASK;
++	bcm_timer_writel(reg, TIMER_CTLx_REG(id));
++
++	reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
++	reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
++	bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
++
++	spin_unlock_irqrestore(&timer_reg_lock, flags);
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_disable);
++
++int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
++{
++	unsigned long flags;
++	int ret;
++
++	if (id >= BCM63XX_TIMER_COUNT || !callback)
++		return -EINVAL;
++
++	ret = 0;
++	spin_lock_irqsave(&timer_data_lock, flags);
++	if (timer_data[id].cb) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	timer_data[id].cb = callback;
++	timer_data[id].data = data;
++
++out:
++	spin_unlock_irqrestore(&timer_data_lock, flags);
++	return ret;
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_register);
++
++void bcm63xx_timer_unregister(int id)
++{
++	unsigned long flags;
++
++	if (id >= BCM63XX_TIMER_COUNT)
++		return;
++
++	spin_lock_irqsave(&timer_data_lock, flags);
++	timer_data[id].cb = NULL;
++	spin_unlock_irqrestore(&timer_data_lock, flags);
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_unregister);
++
++unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
++{
++	return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_countdown);
++
++int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
++{
++	u32 reg, countdown;
++	unsigned long flags;
++
++	if (id >= BCM63XX_TIMER_COUNT)
++		return -EINVAL;
++
++	countdown = bcm63xx_timer_countdown(countdown_us);
++	if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
++		return -EINVAL;
++
++	spin_lock_irqsave(&timer_reg_lock, flags);
++	reg = bcm_timer_readl(TIMER_CTLx_REG(id));
++
++	if (monotonic)
++		reg &= ~TIMER_CTL_MONOTONIC_MASK;
++	else
++		reg |= TIMER_CTL_MONOTONIC_MASK;
++
++	reg &= ~TIMER_CTL_COUNTDOWN_MASK;
++	reg |= countdown;
++	bcm_timer_writel(reg, TIMER_CTLx_REG(id));
++
++	spin_unlock_irqrestore(&timer_reg_lock, flags);
++	return 0;
++}
++
++EXPORT_SYMBOL(bcm63xx_timer_set);
++
++int bcm63xx_timer_init(void)
++{
++	int ret, irq;
++	u32 reg;
++
++	reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
++	reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
++	reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
++	reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
++	bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
++
++	periph_clk = clk_get(NULL, "periph");
++	if (IS_ERR(periph_clk))
++		return -ENODEV;
++
++	irq = bcm63xx_get_irq_number(IRQ_TIMER);
++	ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
++	if (ret) {
++		printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++arch_initcall(bcm63xx_timer_init);
+diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
+index 9cc8522..884c7a9 100644
+--- a/include/asm-mips/fixmap.h
++++ b/include/asm-mips/fixmap.h
+@@ -67,11 +67,15 @@ enum fixed_addresses {
+  * the start of the fixmap, and leave one page empty
+  * at the top of mem..
+  */
++#ifdef CONFIG_BCM63XX
++#define FIXADDR_TOP     ((unsigned long)(long)(int)0xff000000)
++#else
+ #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
+ #define FIXADDR_TOP	((unsigned long)(long)(int)(0xff000000 - 0x20000))
+ #else
+ #define FIXADDR_TOP	((unsigned long)(long)(int)0xfffe0000)
+ #endif
++#endif
+ #define FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
+ #define FIXADDR_START	(FIXADDR_TOP - FIXADDR_SIZE)
+ 
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h b/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
+new file mode 100644
+index 0000000..8fcf8df
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
+@@ -0,0 +1,11 @@
++#ifndef BCM63XX_CLK_H_
++#define BCM63XX_CLK_H_
++
++struct clk {
++	void		(*set)(struct clk *, int);
++	unsigned int	rate;
++	unsigned int	usage;
++	int		id;
++};
++
++#endif /* ! BCM63XX_CLK_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+new file mode 100644
+index 0000000..29b61fd
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+@@ -0,0 +1,314 @@
++#ifndef BCM63XX_CPU_H_
++#define BCM63XX_CPU_H_
++
++#include <linux/types.h>
++#include <linux/init.h>
++
++/*
++ * Macro to fetch bcm63xx cpu id and revision, should be optimized at
++ * compile time if only one CPU support is enabled (idea stolen from
++ * arm mach-types)
++ */
++#define BCM6348_CPU_ID		0x6348
++#define BCM6358_CPU_ID		0x6358
++
++void __init bcm63xx_cpu_init(void);
++u16 __bcm63xx_get_cpu_id(void);
++u16 bcm63xx_get_cpu_rev(void);
++unsigned int bcm63xx_get_cpu_freq(void);
++
++#ifdef CONFIG_BCM63XX_CPU_6348
++# ifdef bcm63xx_get_cpu_id
++#  undef bcm63xx_get_cpu_id
++#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
++#  define BCMCPU_RUNTIME_DETECT
++# else
++#  define bcm63xx_get_cpu_id()	BCM6348_CPU_ID
++# endif
++# define BCMCPU_IS_6348()	(bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
++#else
++# define BCMCPU_IS_6348()	(0)
++#endif
++
++#ifdef CONFIG_BCM63XX_CPU_6358
++# ifdef bcm63xx_get_cpu_id
++#  undef bcm63xx_get_cpu_id
++#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
++#  define BCMCPU_RUNTIME_DETECT
++# else
++#  define bcm63xx_get_cpu_id()	BCM6358_CPU_ID
++# endif
++# define BCMCPU_IS_6358()	(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
++#else
++# define BCMCPU_IS_6358()	(0)
++#endif
++
++#ifndef bcm63xx_get_cpu_id
++#error "No CPU support configured"
++#endif
++
++/*
++ * While registers sets are (mostly) the same across 63xx CPU, base
++ * address of these sets do change.
++ */
++enum bcm63xx_regs_set {
++	RSET_DSL_LMEM = 0,
++	RSET_PERF,
++	RSET_TIMER,
++	RSET_WDT,
++	RSET_UART0,
++	RSET_GPIO,
++	RSET_SPI,
++	RSET_UDC0,
++	RSET_OHCI0,
++	RSET_OHCI_PRIV,
++	RSET_USBH_PRIV,
++	RSET_MPI,
++	RSET_PCMCIA,
++	RSET_DSL,
++	RSET_ENET0,
++	RSET_ENET1,
++	RSET_ENETDMA,
++	RSET_EHCI0,
++	RSET_SDRAM,
++	RSET_MEMC,
++	RSET_DDR,
++};
++
++#define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
++#define RSET_DSL_SIZE			4096
++#define RSET_WDT_SIZE			12
++#define RSET_ENET_SIZE			2048
++#define RSET_ENETDMA_SIZE		2048
++#define RSET_UART_SIZE			24
++#define RSET_UDC_SIZE			256
++#define RSET_OHCI_SIZE			256
++#define RSET_EHCI_SIZE			256
++#define RSET_PCMCIA_SIZE		12
++
++/*
++ * 6348 register sets base address
++ */
++#define BCM_6348_DSL_LMEM_BASE		(0xfff00000)
++#define BCM_6348_PERF_BASE		(0xfffe0000)
++#define BCM_6348_TIMER_BASE		(0xfffe0200)
++#define BCM_6348_WDT_BASE		(0xfffe021c)
++#define BCM_6348_UART0_BASE		(0xfffe0300)
++#define BCM_6348_GPIO_BASE		(0xfffe0400)
++#define BCM_6348_SPI_BASE		(0xfffe0c00)
++#define BCM_6348_UDC0_BASE		(0xfffe1000)
++#define BCM_6348_OHCI0_BASE		(0xfffe1b00)
++#define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
++#define BCM_6348_USBH_PRIV_BASE		(0xdeadbeef)
++#define BCM_6348_MPI_BASE		(0xfffe2000)
++#define BCM_6348_PCMCIA_BASE		(0xfffe2054)
++#define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
++#define BCM_6348_DSL_BASE		(0xfffe3000)
++#define BCM_6348_ENET0_BASE		(0xfffe6000)
++#define BCM_6348_ENET1_BASE		(0xfffe6800)
++#define BCM_6348_ENETDMA_BASE		(0xfffe7000)
++#define BCM_6348_EHCI0_BASE		(0xdeadbeef)
++#define BCM_6348_SDRAM_BASE		(0xfffe2300)
++#define BCM_6348_MEMC_BASE		(0xdeadbeef)
++#define BCM_6348_DDR_BASE		(0xdeadbeef)
++
++/*
++ * 6358 register sets base address
++ */
++#define BCM_6358_DSL_LMEM_BASE		(0xfff00000)
++#define BCM_6358_PERF_BASE		(0xfffe0000)
++#define BCM_6358_TIMER_BASE		(0xfffe0040)
++#define BCM_6358_WDT_BASE		(0xfffe005c)
++#define BCM_6358_UART0_BASE		(0xfffe0100)
++#define BCM_6358_GPIO_BASE		(0xfffe0080)
++#define BCM_6358_SPI_BASE		(0xdeadbeef)
++#define BCM_6358_UDC0_BASE		(0xfffe0800)
++#define BCM_6358_OHCI0_BASE		(0xfffe1400)
++#define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
++#define BCM_6358_USBH_PRIV_BASE		(0xfffe1500)
++#define BCM_6358_MPI_BASE		(0xfffe1000)
++#define BCM_6358_PCMCIA_BASE		(0xfffe1054)
++#define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
++#define BCM_6358_DSL_BASE		(0xfffe3000)
++#define BCM_6358_ENET0_BASE		(0xfffe4000)
++#define BCM_6358_ENET1_BASE		(0xfffe4800)
++#define BCM_6358_ENETDMA_BASE		(0xfffe5000)
++#define BCM_6358_EHCI0_BASE		(0xfffe1300)
++#define BCM_6358_SDRAM_BASE		(0xdeadbeef)
++#define BCM_6358_MEMC_BASE		(0xfffe1200)
++#define BCM_6358_DDR_BASE		(0xfffe12a0)
++
++
++extern const unsigned long *bcm63xx_regs_base;
++
++static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
++{
++#ifdef BCMCPU_RUNTIME_DETECT
++	return bcm63xx_regs_base[set];
++#else
++#ifdef CONFIG_BCM63XX_CPU_6348
++	switch (set) {
++	case RSET_DSL_LMEM:
++		return BCM_6348_DSL_LMEM_BASE;
++	case RSET_PERF:
++		return BCM_6348_PERF_BASE;
++	case RSET_TIMER:
++		return BCM_6348_TIMER_BASE;
++	case RSET_WDT:
++		return BCM_6348_WDT_BASE;
++	case RSET_UART0:
++		return BCM_6348_UART0_BASE;
++	case RSET_GPIO:
++		return BCM_6348_GPIO_BASE;
++	case RSET_SPI:
++		return BCM_6348_SPI_BASE;
++	case RSET_UDC0:
++		return BCM_6348_UDC0_BASE;
++	case RSET_OHCI0:
++		return BCM_6348_OHCI0_BASE;
++	case RSET_OHCI_PRIV:
++		return BCM_6348_OHCI_PRIV_BASE;
++	case RSET_USBH_PRIV:
++		return BCM_6348_USBH_PRIV_BASE;
++	case RSET_MPI:
++		return BCM_6348_MPI_BASE;
++	case RSET_PCMCIA:
++		return BCM_6348_PCMCIA_BASE;
++	case RSET_DSL:
++		return BCM_6348_DSL_BASE;
++	case RSET_ENET0:
++		return BCM_6348_ENET0_BASE;
++	case RSET_ENET1:
++		return BCM_6348_ENET1_BASE;
++	case RSET_ENETDMA:
++		return BCM_6348_ENETDMA_BASE;
++	case RSET_EHCI0:
++		return BCM_6348_EHCI0_BASE;
++	case RSET_SDRAM:
++		return BCM_6348_SDRAM_BASE;
++	case RSET_MEMC:
++		return BCM_6348_MEMC_BASE;
++	case RSET_DDR:
++		return BCM_6348_DDR_BASE;
++	}
++#endif
++#ifdef CONFIG_BCM63XX_CPU_6358
++	switch (set) {
++	case RSET_DSL_LMEM:
++		return BCM_6358_DSL_LMEM_BASE;
++	case RSET_PERF:
++		return BCM_6358_PERF_BASE;
++	case RSET_TIMER:
++		return BCM_6358_TIMER_BASE;
++	case RSET_WDT:
++		return BCM_6358_WDT_BASE;
++	case RSET_UART0:
++		return BCM_6358_UART0_BASE;
++	case RSET_GPIO:
++		return BCM_6358_GPIO_BASE;
++	case RSET_SPI:
++		return BCM_6358_SPI_BASE;
++	case RSET_UDC0:
++		return BCM_6358_UDC0_BASE;
++	case RSET_OHCI0:
++		return BCM_6358_OHCI0_BASE;
++	case RSET_OHCI_PRIV:
++		return BCM_6358_OHCI_PRIV_BASE;
++	case RSET_USBH_PRIV:
++		return BCM_6358_USBH_PRIV_BASE;
++	case RSET_MPI:
++		return BCM_6358_MPI_BASE;
++	case RSET_PCMCIA:
++		return BCM_6358_PCMCIA_BASE;
++	case RSET_ENET0:
++		return BCM_6358_ENET0_BASE;
++	case RSET_ENET1:
++		return BCM_6358_ENET1_BASE;
++	case RSET_ENETDMA:
++		return BCM_6358_ENETDMA_BASE;
++	case RSET_DSL:
++		return BCM_6358_DSL_BASE;
++	case RSET_EHCI0:
++		return BCM_6358_EHCI0_BASE;
++	case RSET_SDRAM:
++		return BCM_6358_SDRAM_BASE;
++	case RSET_MEMC:
++		return BCM_6358_MEMC_BASE;
++	case RSET_DDR:
++		return BCM_6358_DDR_BASE;
++	}
++#endif
++#endif
++	/* unreached */
++	return 0;
++}
++
++/*
++ * IRQ number changes across CPU too
++ */
++enum bcm63xx_irq {
++	IRQ_TIMER = 0,
++	IRQ_UART0,
++	IRQ_DSL,
++	IRQ_ENET0,
++	IRQ_ENET1,
++	IRQ_ENET_PHY,
++	IRQ_OHCI0,
++	IRQ_EHCI0,
++	IRQ_PCMCIA0,
++	IRQ_ENET0_RXDMA,
++	IRQ_ENET0_TXDMA,
++	IRQ_ENET1_RXDMA,
++	IRQ_ENET1_TXDMA,
++	IRQ_PCI,
++	IRQ_PCMCIA,
++};
++
++/*
++ * 6348 irqs
++ */
++#define BCM_6348_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
++#define BCM_6348_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
++#define BCM_6348_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
++#define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
++#define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
++#define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
++#define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
++#define BCM_6348_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 21)
++#define BCM_6348_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 22)
++#define BCM_6348_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 23)
++#define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
++#define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
++
++/*
++ * 6358 irqs
++ */
++#define BCM_6358_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
++#define BCM_6358_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
++#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
++#define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
++#define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
++#define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
++#define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
++#define BCM_6358_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
++#define BCM_6358_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 17)
++#define BCM_6358_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 18)
++#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
++#define BCM_6358_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
++#define BCM_6358_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
++
++extern const int *bcm63xx_irqs;
++
++static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
++{
++	return bcm63xx_irqs[irq];
++}
++
++/*
++ * return installed memory size
++ */
++unsigned int bcm63xx_get_memory_size(void);
++
++#endif /* !BCM63XX_CPU_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h b/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
+new file mode 100644
+index 0000000..b1821c8
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
+@@ -0,0 +1,10 @@
++#ifndef BCM63XX_CS_H
++#define BCM63XX_CS_H
++
++int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
++int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
++			   unsigned int setup, unsigned int hold);
++int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
++int bcm63xx_set_cs_status(unsigned int cs, int enable);
++
++#endif /* !BCM63XX_CS_H */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h b/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
+new file mode 100644
+index 0000000..31145df
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
+@@ -0,0 +1,14 @@
++#ifndef BCM63XX_GPIO_H
++#define BCM63XX_GPIO_H
++
++/* all helpers will BUG() if gpio count is >= 37. */
++#define BCM63XX_GPIO_COUNT	37
++
++void bcm63xx_gpio_set_dataout(int gpio, int val);
++int bcm63xx_gpio_get_datain(int gpio);
++void bcm63xx_gpio_set_direction(int gpio, int dir);
++
++#define GPIO_DIR_OUT	0x0
++#define GPIO_DIR_IN	0x1
++
++#endif /* !BCM63XX_GPIO_H */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_io.h b/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
+new file mode 100644
+index 0000000..1aef06f
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
+@@ -0,0 +1,93 @@
++#ifndef BCM63XX_IO_H_
++#define BCM63XX_IO_H_
++
++#include "bcm63xx_cpu.h"
++
++/*
++ * Physical memory map, RAM is mapped at 0x0.
++ *
++ * Note that size MUST be a power of two.
++ */
++#define BCM_PCMCIA_COMMON_BASE_PA	(0x20000000)
++#define BCM_PCMCIA_COMMON_SIZE		(16 * 1024 * 1024)
++#define BCM_PCMCIA_COMMON_END_PA	(BCM_PCMCIA_COMMON_BASE_PA +	\
++					 BCM_PCMCIA_COMMON_SIZE - 1)
++
++#define BCM_PCMCIA_ATTR_BASE_PA		(0x21000000)
++#define BCM_PCMCIA_ATTR_SIZE		(16 * 1024 * 1024)
++#define BCM_PCMCIA_ATTR_END_PA		(BCM_PCMCIA_ATTR_BASE_PA +	\
++					 BCM_PCMCIA_ATTR_SIZE - 1)
++
++#define BCM_PCMCIA_IO_BASE_PA		(0x22000000)
++#define BCM_PCMCIA_IO_SIZE		(64 * 1024)
++#define BCM_PCMCIA_IO_END_PA		(BCM_PCMCIA_IO_BASE_PA +	\
++					BCM_PCMCIA_IO_SIZE - 1)
++
++#define BCM_PCI_MEM_BASE_PA		(0x30000000)
++#define BCM_PCI_MEM_SIZE		(128 * 1024 * 1024)
++#define BCM_PCI_MEM_END_PA		(BCM_PCI_MEM_BASE_PA +		\
++					BCM_PCI_MEM_SIZE - 1)
++
++#define BCM_PCI_IO_BASE_PA		(0x08000000)
++#define BCM_PCI_IO_SIZE			(64 * 1024)
++#define BCM_PCI_IO_END_PA		(BCM_PCI_IO_BASE_PA +		\
++					BCM_PCI_IO_SIZE - 1)
++#define BCM_PCI_IO_HALF_PA		(BCM_PCI_IO_BASE_PA +		\
++					(BCM_PCI_IO_SIZE / 2) - 1)
++
++#define BCM_CB_MEM_BASE_PA		(0x38000000)
++#define BCM_CB_MEM_SIZE			(128 * 1024 * 1024)
++#define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
++					BCM_CB_MEM_SIZE - 1)
++
++
++/*
++ * Internal registers are accessed through KSEG3
++ */
++#define BCM_REGS_VA(x)	((void __iomem *)(x))
++
++#define bcm_readb(a)	(*(volatile unsigned char *)	BCM_REGS_VA(a))
++#define bcm_readw(a)	(*(volatile unsigned short *)	BCM_REGS_VA(a))
++#define bcm_readl(a)	(*(volatile unsigned int *)	BCM_REGS_VA(a))
++#define bcm_writeb(v,a)	(*(volatile unsigned char *)	BCM_REGS_VA((a)) = (v))
++#define bcm_writew(v,a)	(*(volatile unsigned short *)	BCM_REGS_VA((a)) = (v))
++#define bcm_writel(v,a)	(*(volatile unsigned int *)	BCM_REGS_VA((a)) = (v))
++
++/*
++ * IO helpers to access register set for current CPU
++ */
++#define bcm_rset_readb(s,o)	bcm_readb(bcm63xx_regset_address(s) + (o))
++#define bcm_rset_readw(s,o)	bcm_readw(bcm63xx_regset_address(s) + (o))
++#define bcm_rset_readl(s,o)	bcm_readl(bcm63xx_regset_address(s) + (o))
++#define bcm_rset_writeb(s,v,o)	bcm_writeb((v), \
++					bcm63xx_regset_address(s) + (o))
++#define bcm_rset_writew(s,v,o)	bcm_writew((v), \
++					bcm63xx_regset_address(s) + (o))
++#define bcm_rset_writel(s,v,o)	bcm_writel((v), \
++					bcm63xx_regset_address(s) + (o))
++
++/*
++ * helpers for frequently used register sets
++ */
++#define bcm_perf_readl(o)	bcm_rset_readl(RSET_PERF, (o))
++#define bcm_perf_writel(v,o)	bcm_rset_writel(RSET_PERF, (v), (o))
++#define bcm_timer_readl(o)	bcm_rset_readl(RSET_TIMER, (o))
++#define bcm_timer_writel(v,o)	bcm_rset_writel(RSET_TIMER, (v), (o))
++#define bcm_wdt_readl(o)	bcm_rset_readl(RSET_WDT, (o))
++#define bcm_wdt_writel(v,o)	bcm_rset_writel(RSET_WDT, (v), (o))
++#define bcm_gpio_readl(o)	bcm_rset_readl(RSET_GPIO, (o))
++#define bcm_gpio_writel(v,o)	bcm_rset_writel(RSET_GPIO, (v), (o))
++#define bcm_uart0_readl(o)	bcm_rset_readl(RSET_UART0, (o))
++#define bcm_uart0_writel(v,o)	bcm_rset_writel(RSET_UART0, (v), (o))
++#define bcm_mpi_readl(o)	bcm_rset_readl(RSET_MPI, (o))
++#define bcm_mpi_writel(v,o)	bcm_rset_writel(RSET_MPI, (v), (o))
++#define bcm_pcmcia_readl(o)	bcm_rset_readl(RSET_PCMCIA, (o))
++#define bcm_pcmcia_writel(v,o)	bcm_rset_writel(RSET_PCMCIA, (v), (o))
++#define bcm_sdram_readl(o)	bcm_rset_readl(RSET_SDRAM, (o))
++#define bcm_sdram_writel(v,o)	bcm_rset_writel(RSET_SDRAM, (v), (o))
++#define bcm_memc_readl(o)	bcm_rset_readl(RSET_MEMC, (o))
++#define bcm_memc_writel(v,o)	bcm_rset_writel(RSET_MEMC, (v), (o))
++#define bcm_ddr_readl(o)	bcm_rset_readl(RSET_DDR, (o))
++#define bcm_ddr_writel(v,o)	bcm_rset_writel(RSET_DDR, (v), (o))
++
++#endif /* ! BCM63XX_IO_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h b/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
+new file mode 100644
+index 0000000..5f95577
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
+@@ -0,0 +1,15 @@
++#ifndef BCM63XX_IRQ_H_
++#define BCM63XX_IRQ_H_
++
++#include <bcm63xx_cpu.h>
++
++#define IRQ_MIPS_BASE			0
++#define IRQ_INTERNAL_BASE		8
++
++#define IRQ_EXT_BASE			(IRQ_MIPS_BASE + 3)
++#define IRQ_EXT_0			(IRQ_EXT_BASE + 0)
++#define IRQ_EXT_1			(IRQ_EXT_BASE + 1)
++#define IRQ_EXT_2			(IRQ_EXT_BASE + 2)
++#define IRQ_EXT_3			(IRQ_EXT_BASE + 3)
++
++#endif /* ! BCM63XX_IRQ_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+new file mode 100644
+index 0000000..b5562b1
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+@@ -0,0 +1,728 @@
++#ifndef BCM63XX_REGS_H_
++#define BCM63XX_REGS_H_
++
++/*************************************************************************
++ * _REG relative to RSET_PERF
++ *************************************************************************/
++
++/* Chip Identifier / Revision register */
++#define PERF_REV_REG			0x0
++#define REV_CHIPID_SHIFT		16
++#define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
++#define REV_REVID_SHIFT			0
++#define REV_REVID_MASK			(0xffff << REV_REVID_SHIFT)
++
++/* Clock Control register */
++#define PERF_CKCTL_REG			0x4
++
++#define CKCTL_6348_ADSLPHY_EN		(1 << 0)
++#define CKCTL_6348_MPI_EN		(1 << 1)
++#define CKCTL_6348_SDRAM_EN		(1 << 2)
++#define CKCTL_6348_M2M_EN		(1 << 3)
++#define CKCTL_6348_ENET_EN		(1 << 4)
++#define CKCTL_6348_SAR_EN		(1 << 5)
++#define CKCTL_6348_USBS_EN		(1 << 6)
++#define CKCTL_6348_USBH_EN		(1 << 8)
++#define CKCTL_6348_SPI_EN		(1 << 9)
++
++#define CKCTL_6348_ALL_SAFE_EN		(CKCTL_6348_ADSLPHY_EN |	\
++					CKCTL_6348_M2M_EN |		\
++					CKCTL_6348_ENET_EN |		\
++					CKCTL_6348_SAR_EN |		\
++					CKCTL_6348_USBS_EN |		\
++					CKCTL_6348_USBH_EN |		\
++					CKCTL_6348_SPI_EN)
++
++#define CKCTL_6358_ENET_EN		(1 << 4)
++#define CKCTL_6358_ADSLPHY_EN		(1 << 5)
++#define CKCTL_6358_PCM_EN		(1 << 8)
++#define CKCTL_6358_SPI_EN		(1 << 9)
++#define CKCTL_6358_USBS_EN		(1 << 10)
++#define CKCTL_6358_SAR_EN		(1 << 11)
++#define CKCTL_6358_EMUSB_EN		(1 << 17)
++#define CKCTL_6358_ENET0_EN		(1 << 18)
++#define CKCTL_6358_ENET1_EN		(1 << 19)
++#define CKCTL_6358_USBSU_EN		(1 << 20)
++#define CKCTL_6358_EPHY_EN		(1 << 21)
++
++#define CKCTL_6358_ALL_SAFE_EN		(CKCTL_6358_ENET_EN |		\
++					CKCTL_6358_ADSLPHY_EN |		\
++					CKCTL_6358_PCM_EN |		\
++					CKCTL_6358_SPI_EN |		\
++					CKCTL_6358_USBS_EN |		\
++					CKCTL_6358_SAR_EN |		\
++					CKCTL_6358_EMUSB_EN |		\
++					CKCTL_6358_ENET0_EN |		\
++					CKCTL_6358_ENET1_EN |		\
++					CKCTL_6358_USBSU_EN |		\
++					CKCTL_6358_EPHY_EN)
++
++/* System PLL Control register  */
++#define PERF_SYS_PLL_CTL_REG		0x8
++#define SYS_PLL_SOFT_RESET		0x1
++
++/* Interrupt Mask register */
++#define PERF_IRQMASK_REG		0xc
++#define PERF_IRQSTAT_REG		0x10
++
++/* Interrupt Status register */
++#define PERF_IRQSTAT_REG		0x10
++
++/* External Interrupt Configuration register */
++#define PERF_EXTIRQ_CFG_REG		0x14
++#define EXTIRQ_CFG_SENSE(x)		(1 << (x))
++#define EXTIRQ_CFG_STAT(x)		(1 << (x + 5))
++#define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 10))
++#define EXTIRQ_CFG_MASK(x)		(1 << (x + 15))
++#define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 20))
++#define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 25))
++
++#define EXTIRQ_CFG_CLEAR_ALL		(0xf << 10)
++#define EXTIRQ_CFG_MASK_ALL		(0xf << 15)
++
++/* Soft Reset register */
++#define PERF_SOFTRESET_REG		0x28
++
++#define SOFTRESET_6348_SPI_MASK		(1 << 0)
++#define SOFTRESET_6348_ENET_MASK	(1 << 2)
++#define SOFTRESET_6348_USBH_MASK	(1 << 3)
++#define SOFTRESET_6348_USBS_MASK	(1 << 4)
++#define SOFTRESET_6348_ADSL_MASK	(1 << 5)
++#define SOFTRESET_6348_DMAMEM_MASK	(1 << 6)
++#define SOFTRESET_6348_SAR_MASK		(1 << 7)
++#define SOFTRESET_6348_ACLC_MASK	(1 << 8)
++#define SOFTRESET_6348_ADSLMIPSPLL_MASK	(1 << 10)
++
++#define SOFTRESET_6348_ALL	 (SOFTRESET_6348_SPI_MASK |		\
++				  SOFTRESET_6348_ENET_MASK |		\
++				  SOFTRESET_6348_USBH_MASK |		\
++				  SOFTRESET_6348_USBS_MASK |		\
++				  SOFTRESET_6348_ADSL_MASK |		\
++				  SOFTRESET_6348_DMAMEM_MASK |		\
++				  SOFTRESET_6348_SAR_MASK |		\
++				  SOFTRESET_6348_ACLC_MASK |		\
++				  SOFTRESET_6348_ADSLMIPSPLL_MASK)
++
++/* MIPS PLL control register */
++#define PERF_MIPSPLLCTL_REG		0x34
++#define MIPSPLLCTL_N1_SHIFT		20
++#define MIPSPLLCTL_N1_MASK		(0x7 << MIPSPLLCTL_N1_SHIFT)
++#define MIPSPLLCTL_N2_SHIFT		15
++#define MIPSPLLCTL_N2_MASK		(0x1f << MIPSPLLCTL_N2_SHIFT)
++#define MIPSPLLCTL_M1REF_SHIFT		12
++#define MIPSPLLCTL_M1REF_MASK		(0x7 << MIPSPLLCTL_M1REF_SHIFT)
++#define MIPSPLLCTL_M2REF_SHIFT		9
++#define MIPSPLLCTL_M2REF_MASK		(0x7 << MIPSPLLCTL_M2REF_SHIFT)
++#define MIPSPLLCTL_M1CPU_SHIFT		6
++#define MIPSPLLCTL_M1CPU_MASK		(0x7 << MIPSPLLCTL_M1CPU_SHIFT)
++#define MIPSPLLCTL_M1BUS_SHIFT		3
++#define MIPSPLLCTL_M1BUS_MASK		(0x7 << MIPSPLLCTL_M1BUS_SHIFT)
++#define MIPSPLLCTL_M2BUS_SHIFT		0
++#define MIPSPLLCTL_M2BUS_MASK		(0x7 << MIPSPLLCTL_M2BUS_SHIFT)
++
++/* ADSL PHY PLL Control register */
++#define PERF_ADSLPLLCTL_REG		0x38
++#define ADSLPLLCTL_N1_SHIFT		20
++#define ADSLPLLCTL_N1_MASK		(0x7 << ADSLPLLCTL_N1_SHIFT)
++#define ADSLPLLCTL_N2_SHIFT		15
++#define ADSLPLLCTL_N2_MASK		(0x1f << ADSLPLLCTL_N2_SHIFT)
++#define ADSLPLLCTL_M1REF_SHIFT		12
++#define ADSLPLLCTL_M1REF_MASK		(0x7 << ADSLPLLCTL_M1REF_SHIFT)
++#define ADSLPLLCTL_M2REF_SHIFT		9
++#define ADSLPLLCTL_M2REF_MASK		(0x7 << ADSLPLLCTL_M2REF_SHIFT)
++#define ADSLPLLCTL_M1CPU_SHIFT		6
++#define ADSLPLLCTL_M1CPU_MASK		(0x7 << ADSLPLLCTL_M1CPU_SHIFT)
++#define ADSLPLLCTL_M1BUS_SHIFT		3
++#define ADSLPLLCTL_M1BUS_MASK		(0x7 << ADSLPLLCTL_M1BUS_SHIFT)
++#define ADSLPLLCTL_M2BUS_SHIFT		0
++#define ADSLPLLCTL_M2BUS_MASK		(0x7 << ADSLPLLCTL_M2BUS_SHIFT)
++
++#define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus)		\
++				(((n1) << ADSLPLLCTL_N1_SHIFT) |	\
++				((n2) << ADSLPLLCTL_N2_SHIFT) |		\
++				((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |	\
++				((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |	\
++				((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |	\
++				((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |	\
++				((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
++
++
++/*************************************************************************
++ * _REG relative to RSET_TIMER
++ *************************************************************************/
++
++#define BCM63XX_TIMER_COUNT		4
++#define TIMER_T0_ID			0
++#define TIMER_T1_ID			1
++#define TIMER_T2_ID			2
++#define TIMER_WDT_ID			3
++
++/* Timer irqstat register */
++#define TIMER_IRQSTAT_REG		0
++#define TIMER_IRQSTAT_TIMER_CAUSE(x)	(1 << (x))
++#define TIMER_IRQSTAT_TIMER0_CAUSE	(1 << 0)
++#define TIMER_IRQSTAT_TIMER1_CAUSE	(1 << 1)
++#define TIMER_IRQSTAT_TIMER2_CAUSE	(1 << 2)
++#define TIMER_IRQSTAT_WDT_CAUSE		(1 << 3)
++#define TIMER_IRQSTAT_TIMER_IR_EN(x)	(1 << ((x) + 8))
++#define TIMER_IRQSTAT_TIMER0_IR_EN	(1 << 8)
++#define TIMER_IRQSTAT_TIMER1_IR_EN	(1 << 9)
++#define TIMER_IRQSTAT_TIMER2_IR_EN	(1 << 10)
++
++/* Timer control register */
++#define TIMER_CTLx_REG(x)		(0x4 + (x * 4))
++#define TIMER_CTL0_REG			0x4
++#define TIMER_CTL1_REG			0x8
++#define TIMER_CTL2_REG			0xC
++#define TIMER_CTL_COUNTDOWN_MASK	(0x3fffffff)
++#define TIMER_CTL_MONOTONIC_MASK	(1 << 30)
++#define TIMER_CTL_ENABLE_MASK		(1 << 31)
++
++
++/*************************************************************************
++ * _REG relative to RSET_WDT
++ *************************************************************************/
++
++/* Watchdog default count register */
++#define WDT_DEFVAL_REG			0x0
++
++/* Watchdog control register */
++#define WDT_CTL_REG			0x4
++
++/* Watchdog control register constants */
++#define WDT_START_1			(0xff00)
++#define WDT_START_2			(0x00ff)
++#define WDT_STOP_1			(0xee00)
++#define WDT_STOP_2			(0x00ee)
++
++/* Watchdog reset length register */
++#define WDT_RSTLEN_REG			0x8
++
++
++/*************************************************************************
++ * _REG relative to RSET_UARTx
++ *************************************************************************/
++
++/* UART Control Register */
++#define UART_CTL_REG			0x0
++#define UART_CTL_RXTMOUTCNT_SHIFT	0
++#define UART_CTL_RXTMOUTCNT_MASK	(0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
++#define UART_CTL_RSTTXDN_SHIFT		5
++#define UART_CTL_RSTTXDN_MASK		(1 << UART_CTL_RSTTXDN_SHIFT)
++#define UART_CTL_RSTRXFIFO_SHIFT		6
++#define UART_CTL_RSTRXFIFO_MASK		(1 << UART_CTL_RSTRXFIFO_SHIFT)
++#define UART_CTL_RSTTXFIFO_SHIFT		7
++#define UART_CTL_RSTTXFIFO_MASK		(1 << UART_CTL_RSTTXFIFO_SHIFT)
++#define UART_CTL_STOPBITS_SHIFT		8
++#define UART_CTL_STOPBITS_MASK		(0xf << UART_CTL_STOPBITS_SHIFT)
++#define UART_CTL_STOPBITS_1		(0x7 << UART_CTL_STOPBITS_SHIFT)
++#define UART_CTL_STOPBITS_2		(0xf << UART_CTL_STOPBITS_SHIFT)
++#define UART_CTL_BITSPERSYM_SHIFT	12
++#define UART_CTL_BITSPERSYM_MASK	(0x3 << UART_CTL_BITSPERSYM_SHIFT)
++#define UART_CTL_XMITBRK_SHIFT		14
++#define UART_CTL_XMITBRK_MASK		(1 << UART_CTL_XMITBRK_SHIFT)
++#define UART_CTL_RSVD_SHIFT		15
++#define UART_CTL_RSVD_MASK		(1 << UART_CTL_RSVD_SHIFT)
++#define UART_CTL_RXPAREVEN_SHIFT		16
++#define UART_CTL_RXPAREVEN_MASK		(1 << UART_CTL_RXPAREVEN_SHIFT)
++#define UART_CTL_RXPAREN_SHIFT		17
++#define UART_CTL_RXPAREN_MASK		(1 << UART_CTL_RXPAREN_SHIFT)
++#define UART_CTL_TXPAREVEN_SHIFT		18
++#define UART_CTL_TXPAREVEN_MASK		(1 << UART_CTL_TXPAREVEN_SHIFT)
++#define UART_CTL_TXPAREN_SHIFT		18
++#define UART_CTL_TXPAREN_MASK		(1 << UART_CTL_TXPAREN_SHIFT)
++#define UART_CTL_LOOPBACK_SHIFT		20
++#define UART_CTL_LOOPBACK_MASK		(1 << UART_CTL_LOOPBACK_SHIFT)
++#define UART_CTL_RXEN_SHIFT		21
++#define UART_CTL_RXEN_MASK		(1 << UART_CTL_RXEN_SHIFT)
++#define UART_CTL_TXEN_SHIFT		22
++#define UART_CTL_TXEN_MASK		(1 << UART_CTL_TXEN_SHIFT)
++#define UART_CTL_BRGEN_SHIFT		23
++#define UART_CTL_BRGEN_MASK		(1 << UART_CTL_BRGEN_SHIFT)
++
++/* UART Baudword register */
++#define UART_BAUD_REG			0x4
++
++/* UART Misc Control register */
++#define UART_MCTL_REG			0x8
++#define UART_MCTL_DTR_SHIFT		0
++#define UART_MCTL_DTR_MASK		(1 << UART_MCTL_DTR_SHIFT)
++#define UART_MCTL_RTS_SHIFT		1
++#define UART_MCTL_RTS_MASK		(1 << UART_MCTL_RTS_SHIFT)
++#define UART_MCTL_RXFIFOTHRESH_SHIFT	8
++#define UART_MCTL_RXFIFOTHRESH_MASK	(0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
++#define UART_MCTL_TXFIFOTHRESH_SHIFT	12
++#define UART_MCTL_TXFIFOTHRESH_MASK	(0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
++#define UART_MCTL_RXFIFOFILL_SHIFT	16
++#define UART_MCTL_RXFIFOFILL_MASK	(0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
++#define UART_MCTL_TXFIFOFILL_SHIFT	24
++#define UART_MCTL_TXFIFOFILL_MASK	(0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
++
++/* UART External Input Configuration register */
++#define UART_EXTINP_REG			0xc
++#define UART_EXTINP_RI_SHIFT		0
++#define UART_EXTINP_RI_MASK		(1 << UART_EXTINP_RI_SHIFT)
++#define UART_EXTINP_CTS_SHIFT		1
++#define UART_EXTINP_CTS_MASK		(1 << UART_EXTINP_CTS_SHIFT)
++#define UART_EXTINP_DCD_SHIFT		2
++#define UART_EXTINP_DCD_MASK		(1 << UART_EXTINP_DCD_SHIFT)
++#define UART_EXTINP_DSR_SHIFT		3
++#define UART_EXTINP_DSR_MASK		(1 << UART_EXTINP_DSR_SHIFT)
++#define UART_EXTINP_IRSTAT(x)		(1 << (x + 4))
++#define UART_EXTINP_IRMASK(x)		(1 << (x + 8))
++#define UART_EXTINP_IR_RI		0
++#define UART_EXTINP_IR_CTS		1
++#define UART_EXTINP_IR_DCD		2
++#define UART_EXTINP_IR_DSR		3
++#define UART_EXTINP_RI_NOSENSE_SHIFT	16
++#define UART_EXTINP_RI_NOSENSE_MASK	(1 << UART_EXTINP_RI_NOSENSE_SHIFT)
++#define UART_EXTINP_CTS_NOSENSE_SHIFT	17
++#define UART_EXTINP_CTS_NOSENSE_MASK	(1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
++#define UART_EXTINP_DCD_NOSENSE_SHIFT	18
++#define UART_EXTINP_DCD_NOSENSE_MASK	(1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
++#define UART_EXTINP_DSR_NOSENSE_SHIFT	19
++#define UART_EXTINP_DSR_NOSENSE_MASK	(1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
++
++/* UART Interrupt register */
++#define UART_IR_REG			0x10
++#define UART_IR_MASK(x)			(1 << (x + 16))
++#define UART_IR_STAT(x)			(1 << (x))
++#define UART_IR_EXTIP			0
++#define UART_IR_TXUNDER			1
++#define UART_IR_TXOVER			2
++#define UART_IR_TXTRESH			3
++#define UART_IR_TXRDLATCH		4
++#define UART_IR_TXEMPTY			5
++#define UART_IR_RXUNDER			6
++#define UART_IR_RXOVER			7
++#define UART_IR_RXTIMEOUT		8
++#define UART_IR_RXFULL			9
++#define UART_IR_RXTHRESH		10
++#define UART_IR_RXNOTEMPTY		11
++#define UART_IR_RXFRAMEERR		12
++#define UART_IR_RXPARERR		13
++#define UART_IR_RXBRK			14
++#define UART_IR_TXDONE			15
++
++/* UART Fifo register */
++#define UART_FIFO_REG			0x14
++#define UART_FIFO_VALID_SHIFT		0
++#define UART_FIFO_VALID_MASK		0xff
++#define UART_FIFO_FRAMEERR_SHIFT	8
++#define UART_FIFO_FRAMEERR_MASK		(1 << UART_FIFO_FRAMEERR_SHIFT)
++#define UART_FIFO_PARERR_SHIFT		9
++#define UART_FIFO_PARERR_MASK		(1 << UART_FIFO_PARERR_SHIFT)
++#define UART_FIFO_BRKDET_SHIFT		10
++#define UART_FIFO_BRKDET_MASK		(1 << UART_FIFO_BRKDET_SHIFT)
++#define UART_FIFO_ANYERR_MASK		(UART_FIFO_FRAMEERR_MASK |	\
++					UART_FIFO_PARERR_MASK |		\
++					UART_FIFO_BRKDET_MASK)
++
++
++/*************************************************************************
++ * _REG relative to RSET_GPIO
++ *************************************************************************/
++
++/* GPIO registers */
++#define GPIO_CTL_HI_REG			0x0
++#define GPIO_CTL_LO_REG			0x4
++#define GPIO_DATA_HI_REG		0x8
++#define GPIO_DATA_LO_REG		0xC
++
++/* GPIO mux registers and constants */
++#define GPIO_MODE_REG			0x18
++
++#define GPIO_MODE_6348_G4_DIAG		0x00090000
++#define GPIO_MODE_6348_G4_UTOPIA	0x00080000
++#define GPIO_MODE_6348_G4_LEGACY_LED	0x00030000
++#define GPIO_MODE_6348_G4_MII_SNOOP	0x00020000
++#define GPIO_MODE_6348_G4_EXT_EPHY	0x00010000
++#define GPIO_MODE_6348_G3_DIAG		0x00009000
++#define GPIO_MODE_6348_G3_UTOPIA	0x00008000
++#define GPIO_MODE_6348_G3_EXT_MII	0x00007000
++#define GPIO_MODE_6348_G2_DIAG		0x00000900
++#define GPIO_MODE_6348_G2_PCI		0x00000500
++#define GPIO_MODE_6348_G1_DIAG		0x00000090
++#define GPIO_MODE_6348_G1_UTOPIA	0x00000080
++#define GPIO_MODE_6348_G1_SPI_UART	0x00000060
++#define GPIO_MODE_6348_G1_SPI_MASTER	0x00000060
++#define GPIO_MODE_6348_G1_MII_PCCARD	0x00000040
++#define GPIO_MODE_6348_G1_MII_SNOOP	0x00000020
++#define GPIO_MODE_6348_G1_EXT_EPHY	0x00000010
++#define GPIO_MODE_6348_G0_DIAG		0x00000009
++#define GPIO_MODE_6348_G0_EXT_MII	0x00000007
++
++#define GPIO_MODE_6358_EXTRACS		(1 << 5)
++#define GPIO_MODE_6358_UART1		(1 << 6)
++#define GPIO_MODE_6358_EXTRA_SPI_SS	(1 << 7)
++#define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
++#define GPIO_MODE_6358_UTOPIA		(1 << 12)
++
++
++/*************************************************************************
++ * _REG relative to RSET_ENET
++ *************************************************************************/
++
++/* Receiver Configuration register */
++#define ENET_RXCFG_REG			0x0
++#define ENET_RXCFG_ALLMCAST_SHIFT	1
++#define ENET_RXCFG_ALLMCAST_MASK	(1 << ENET_RXCFG_ALLMCAST_SHIFT)
++#define ENET_RXCFG_PROMISC_SHIFT	3
++#define ENET_RXCFG_PROMISC_MASK		(1 << ENET_RXCFG_PROMISC_SHIFT)
++#define ENET_RXCFG_LOOPBACK_SHIFT	4
++#define ENET_RXCFG_LOOPBACK_MASK	(1 << ENET_RXCFG_LOOPBACK_SHIFT)
++#define ENET_RXCFG_ENFLOW_SHIFT		5
++#define ENET_RXCFG_ENFLOW_MASK		(1 << ENET_RXCFG_ENFLOW_SHIFT)
++
++/* Receive Maximum Length register */
++#define ENET_RXMAXLEN_REG		0x4
++#define ENET_RXMAXLEN_SHIFT		0
++#define ENET_RXMAXLEN_MASK		(0x7ff << ENET_RXMAXLEN_SHIFT)
++
++/* Transmit Maximum Length register */
++#define ENET_TXMAXLEN_REG		0x8
++#define ENET_TXMAXLEN_SHIFT		0
++#define ENET_TXMAXLEN_MASK		(0x7ff << ENET_TXMAXLEN_SHIFT)
++
++/* MII Status/Control register */
++#define ENET_MIISC_REG			0x10
++#define ENET_MIISC_MDCFREQDIV_SHIFT	0
++#define ENET_MIISC_MDCFREQDIV_MASK	(0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
++#define ENET_MIISC_PREAMBLEEN_SHIFT	7
++#define ENET_MIISC_PREAMBLEEN_MASK	(1 << ENET_MIISC_PREAMBLEEN_SHIFT)
++
++/* MII Data register */
++#define ENET_MIIDATA_REG		0x14
++#define ENET_MIIDATA_DATA_SHIFT		0
++#define ENET_MIIDATA_DATA_MASK		(0xffff << ENET_MIIDATA_DATA_SHIFT)
++#define ENET_MIIDATA_TA_SHIFT		16
++#define ENET_MIIDATA_TA_MASK		(0x3 << ENET_MIIDATA_TA_SHIFT)
++#define ENET_MIIDATA_REG_SHIFT		18
++#define ENET_MIIDATA_REG_MASK		(0x1f << ENET_MIIDATA_REG_SHIFT)
++#define ENET_MIIDATA_PHYID_SHIFT	23
++#define ENET_MIIDATA_PHYID_MASK		(0x1f << ENET_MIIDATA_PHYID_SHIFT)
++#define ENET_MIIDATA_OP_READ_MASK	(0x6 << 28)
++#define ENET_MIIDATA_OP_WRITE_MASK	(0x5 << 28)
++
++/* Ethernet Interrupt Mask register */
++#define ENET_IRMASK_REG			0x18
++
++/* Ethernet Interrupt register */
++#define ENET_IR_REG			0x1c
++#define ENET_IR_MII			(1 << 0)
++#define ENET_IR_MIB			(1 << 1)
++#define ENET_IR_FLOWC			(1 << 2)
++
++/* Ethernet Control register */
++#define ENET_CTL_REG			0x2c
++#define ENET_CTL_ENABLE_SHIFT		0
++#define ENET_CTL_ENABLE_MASK		(1 << ENET_CTL_ENABLE_SHIFT)
++#define ENET_CTL_DISABLE_SHIFT		1
++#define ENET_CTL_DISABLE_MASK		(1 << ENET_CTL_DISABLE_SHIFT)
++#define ENET_CTL_SRESET_SHIFT		2
++#define ENET_CTL_SRESET_MASK		(1 << ENET_CTL_SRESET_SHIFT)
++#define ENET_CTL_EPHYSEL_SHIFT		3
++#define ENET_CTL_EPHYSEL_MASK		(1 << ENET_CTL_EPHYSEL_SHIFT)
++
++/* Transmit Control register */
++#define ENET_TXCTL_REG			0x30
++#define ENET_TXCTL_FD_SHIFT		0
++#define ENET_TXCTL_FD_MASK		(1 << ENET_TXCTL_FD_SHIFT)
++
++/* Transmit Watermask register */
++#define ENET_TXWMARK_REG		0x34
++#define ENET_TXWMARK_WM_SHIFT		0
++#define ENET_TXWMARK_WM_MASK		(0x3f << ENET_TXWMARK_WM_SHIFT)
++
++/* MIB Control register */
++#define ENET_MIBCTL_REG			0x38
++#define ENET_MIBCTL_RDCLEAR_SHIFT	0
++#define ENET_MIBCTL_RDCLEAR_MASK	(1 << ENET_MIBCTL_RDCLEAR_SHIFT)
++
++/* Perfect Match Data Low register */
++#define ENET_PML_REG(x)			(0x58 + (x) * 8)
++#define ENET_PMH_REG(x)			(0x5c + (x) * 8)
++#define ENET_PMH_DATAVALID_SHIFT	16
++#define ENET_PMH_DATAVALID_MASK		(1 << ENET_PMH_DATAVALID_SHIFT)
++
++/* MIB register */
++#define ENET_MIB_REG(x)			(0x200 + (x) * 4)
++#define ENET_MIB_REG_COUNT		55
++
++
++/*************************************************************************
++ * _REG relative to RSET_ENETDMA
++ *************************************************************************/
++
++/* Controller Configuration Register */
++#define ENETDMA_CFG_REG			(0x0)
++#define ENETDMA_CFG_EN_SHIFT		0
++#define ENETDMA_CFG_EN_MASK		(1 << ENETDMA_CFG_EN_SHIFT)
++#define ENETDMA_CFG_FLOWCH_MASK(x)	(1 << ((x >> 1) + 1))
++
++/* Flow Control Descriptor Low Threshold register */
++#define ENETDMA_FLOWCL_REG(x)		(0x4 + (x) * 6)
++
++/* Flow Control Descriptor High Threshold register */
++#define ENETDMA_FLOWCH_REG(x)		(0x8 + (x) * 6)
++
++/* Flow Control Descriptor Buffer Alloca Threshold register */
++#define ENETDMA_BUFALLOC_REG(x)		(0xc + (x) * 6)
++#define ENETDMA_BUFALLOC_FORCE_SHIFT	31
++#define ENETDMA_BUFALLOC_FORCE_MASK	(1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
++
++/* Channel Configuration register */
++#define ENETDMA_CHANCFG_REG(x)		(0x100 + (x) * 0x10)
++#define ENETDMA_CHANCFG_EN_SHIFT	0
++#define ENETDMA_CHANCFG_EN_MASK		(1 << ENETDMA_CHANCFG_EN_SHIFT)
++#define ENETDMA_CHANCFG_PKTHALT_SHIFT	1
++#define ENETDMA_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
++
++/* Interrupt Control/Status register */
++#define ENETDMA_IR_REG(x)		(0x104 + (x) * 0x10)
++#define ENETDMA_IR_BUFDONE_MASK		(1 << 0)
++#define ENETDMA_IR_PKTDONE_MASK		(1 << 1)
++#define ENETDMA_IR_NOTOWNER_MASK	(1 << 2)
++
++/* Interrupt Mask register */
++#define ENETDMA_IRMASK_REG(x)		(0x108 + (x) * 0x10)
++
++/* Maximum Burst Length */
++#define ENETDMA_MAXBURST_REG(x)		(0x10C + (x) * 0x10)
++
++/* Ring Start Address register */
++#define ENETDMA_RSTART_REG(x)		(0x200 + (x) * 0x10)
++
++/* State Ram Word 2 */
++#define ENETDMA_SRAM2_REG(x)		(0x204 + (x) * 0x10)
++
++/* State Ram Word 3 */
++#define ENETDMA_SRAM3_REG(x)		(0x208 + (x) * 0x10)
++
++/* State Ram Word 4 */
++#define ENETDMA_SRAM4_REG(x)		(0x20c + (x) * 0x10)
++
++
++/*************************************************************************
++ * _REG relative to RSET_OHCI_PRIV
++ *************************************************************************/
++
++#define OHCI_PRIV_REG			0x0
++#define OHCI_PRIV_PORT1_HOST_SHIFT	0
++#define OHCI_PRIV_PORT1_HOST_MASK	(1 << OHCI_PRIV_PORT1_HOST_SHIFT)
++#define OHCI_PRIV_REG_SWAP_SHIFT	3
++#define OHCI_PRIV_REG_SWAP_MASK		(1 << OHCI_PRIV_REG_SWAP_SHIFT)
++
++
++/*************************************************************************
++ * _REG relative to RSET_USBH_PRIV
++ *************************************************************************/
++
++#define USBH_PRIV_SWAP_REG		0x0
++#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4
++#define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
++#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3
++#define USBH_PRIV_SWAP_EHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
++#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT	1
++#define USBH_PRIV_SWAP_OHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
++#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT	0
++#define USBH_PRIV_SWAP_OHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
++
++#define USBH_PRIV_TEST_REG		0x24
++
++
++/*************************************************************************
++ * _REG relative to RSET_MPI
++ *************************************************************************/
++
++/* well known (hard wired) chip select */
++#define MPI_CS_PCMCIA_COMMON		4
++#define MPI_CS_PCMCIA_ATTR		5
++#define MPI_CS_PCMCIA_IO		6
++
++/* Chip select base register */
++#define MPI_CSBASE_REG(x)		(0x0 + (x) * 8)
++#define MPI_CSBASE_BASE_SHIFT		13
++#define MPI_CSBASE_BASE_MASK		(0x1ffff << MPI_CSBASE_BASE_SHIFT)
++#define MPI_CSBASE_SIZE_SHIFT		0
++#define MPI_CSBASE_SIZE_MASK		(0xf << MPI_CSBASE_SIZE_SHIFT)
++
++#define MPI_CSBASE_SIZE_8K		0
++#define MPI_CSBASE_SIZE_16K		1
++#define MPI_CSBASE_SIZE_32K		2
++#define MPI_CSBASE_SIZE_64K		3
++#define MPI_CSBASE_SIZE_128K		4
++#define MPI_CSBASE_SIZE_256K		5
++#define MPI_CSBASE_SIZE_512K		6
++#define MPI_CSBASE_SIZE_1M		7
++#define MPI_CSBASE_SIZE_2M		8
++#define MPI_CSBASE_SIZE_4M		9
++#define MPI_CSBASE_SIZE_8M		10
++#define MPI_CSBASE_SIZE_16M		11
++#define MPI_CSBASE_SIZE_32M		12
++#define MPI_CSBASE_SIZE_64M		13
++#define MPI_CSBASE_SIZE_128M		14
++#define MPI_CSBASE_SIZE_256M		15
++
++/* Chip select control register */
++#define MPI_CSCTL_REG(x)		(0x4 + (x) * 8)
++#define MPI_CSCTL_ENABLE_MASK		(1 << 0)
++#define MPI_CSCTL_WAIT_SHIFT		1
++#define MPI_CSCTL_WAIT_MASK		(0x7 << MPI_CSCTL_WAIT_SHIFT)
++#define MPI_CSCTL_DATA16_MASK		(1 << 4)
++#define MPI_CSCTL_SYNCMODE_MASK		(1 << 7)
++#define MPI_CSCTL_TSIZE_MASK		(1 << 8)
++#define MPI_CSCTL_ENDIANSWAP_MASK	(1 << 10)
++#define MPI_CSCTL_SETUP_SHIFT		16
++#define MPI_CSCTL_SETUP_MASK		(0xf << MPI_CSCTL_SETUP_SHIFT)
++#define MPI_CSCTL_HOLD_SHIFT		20
++#define MPI_CSCTL_HOLD_MASK		(0xf << MPI_CSCTL_HOLD_SHIFT)
++
++/* PCI registers */
++#define MPI_SP0_RANGE_REG		0x100
++#define MPI_SP0_REMAP_REG		0x104
++#define MPI_SP0_REMAP_ENABLE_MASK	(1 << 0)
++#define MPI_SP1_RANGE_REG		0x10C
++#define MPI_SP1_REMAP_REG		0x110
++#define MPI_SP1_REMAP_ENABLE_MASK	(1 << 0)
++
++#define MPI_L2PCFG_REG			0x11C
++#define MPI_L2PCFG_CFG_TYPE_SHIFT	0
++#define MPI_L2PCFG_CFG_TYPE_MASK	(0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
++#define MPI_L2PCFG_REG_SHIFT		2
++#define MPI_L2PCFG_REG_MASK		(0x3f << MPI_L2PCFG_REG_SHIFT)
++#define MPI_L2PCFG_FUNC_SHIFT		8
++#define MPI_L2PCFG_FUNC_MASK		(0x7 << MPI_L2PCFG_FUNC_SHIFT)
++#define MPI_L2PCFG_DEVNUM_SHIFT		11
++#define MPI_L2PCFG_DEVNUM_MASK		(0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
++#define MPI_L2PCFG_CFG_USEREG_MASK	(1 << 30)
++#define MPI_L2PCFG_CFG_SEL_MASK		(1 << 31)
++
++#define MPI_L2PMEMRANGE1_REG		0x120
++#define MPI_L2PMEMBASE1_REG		0x124
++#define MPI_L2PMEMREMAP1_REG		0x128
++#define MPI_L2PMEMRANGE2_REG		0x12C
++#define MPI_L2PMEMBASE2_REG		0x130
++#define MPI_L2PMEMREMAP2_REG		0x134
++#define MPI_L2PIORANGE_REG		0x138
++#define MPI_L2PIOBASE_REG		0x13C
++#define MPI_L2PIOREMAP_REG		0x140
++#define MPI_L2P_BASE_MASK		(0xffff8000)
++#define MPI_L2PREMAP_ENABLED_MASK	(1 << 0)
++#define MPI_L2PREMAP_IS_CARDBUS_MASK	(1 << 2)
++
++#define MPI_PCIMODESEL_REG		0x144
++#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK	(1 << 0)
++#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK	(1 << 1)
++#define MPI_PCIMODESEL_EXT_ARB_MASK	(1 << 2)
++#define MPI_PCIMODESEL_PREFETCH_SHIFT	4
++#define MPI_PCIMODESEL_PREFETCH_MASK	(0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
++
++#define MPI_LOCBUSCTL_REG		0x14C
++#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK	(1 << 0)
++#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK	(1 << 1)
++
++#define MPI_LOCINT_REG			0x150
++#define MPI_LOCINT_MASK(x)		(1 << (x + 16))
++#define MPI_LOCINT_STAT(x)		(1 << (x))
++#define MPI_LOCINT_DIR_FAILED		6
++#define MPI_LOCINT_EXT_PCI_INT		7
++#define MPI_LOCINT_SERR			8
++#define MPI_LOCINT_CSERR		9
++
++#define MPI_PCICFGCTL_REG		0x178
++#define MPI_PCICFGCTL_CFGADDR_SHIFT	2
++#define MPI_PCICFGCTL_CFGADDR_MASK	(0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
++#define MPI_PCICFGCTL_WRITEEN_MASK	(1 << 7)
++
++#define MPI_PCICFGDATA_REG		0x17C
++
++/* PCI host bridge custom register */
++#define BCMPCI_REG_TIMERS		0x40
++#define REG_TIMER_TRDY_SHIFT		0
++#define REG_TIMER_TRDY_MASK		(0xff << REG_TIMER_TRDY_SHIFT)
++#define REG_TIMER_RETRY_SHIFT		8
++#define REG_TIMER_RETRY_MASK		(0xff << REG_TIMER_RETRY_SHIFT)
++
++
++/*************************************************************************
++ * _REG relative to RSET_PCMCIA
++ *************************************************************************/
++
++#define PCMCIA_C1_REG			0x0
++#define PCMCIA_C1_CD1_MASK		(1 << 0)
++#define PCMCIA_C1_CD2_MASK		(1 << 1)
++#define PCMCIA_C1_VS1_MASK		(1 << 2)
++#define PCMCIA_C1_VS2_MASK		(1 << 3)
++#define PCMCIA_C1_VS1OE_MASK		(1 << 6)
++#define PCMCIA_C1_VS2OE_MASK		(1 << 7)
++#define PCMCIA_C1_CBIDSEL_SHIFT		(8)
++#define PCMCIA_C1_CBIDSEL_MASK		(0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
++#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK	(1 << 13)
++#define PCMCIA_C1_EN_PCMCIA_MASK	(1 << 14)
++#define PCMCIA_C1_EN_CARDBUS_MASK	(1 << 15)
++#define PCMCIA_C1_RESET_MASK		(1 << 18)
++
++#define PCMCIA_C2_REG			0x8
++#define PCMCIA_C2_DATA16_MASK		(1 << 0)
++#define PCMCIA_C2_BYTESWAP_MASK		(1 << 1)
++#define PCMCIA_C2_RWCOUNT_SHIFT		2
++#define PCMCIA_C2_RWCOUNT_MASK		(0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
++#define PCMCIA_C2_INACTIVE_SHIFT	8
++#define PCMCIA_C2_INACTIVE_MASK		(0x3f << PCMCIA_C2_INACTIVE_SHIFT)
++#define PCMCIA_C2_SETUP_SHIFT		16
++#define PCMCIA_C2_SETUP_MASK		(0x3f << PCMCIA_C2_SETUP_SHIFT)
++#define PCMCIA_C2_HOLD_SHIFT		24
++#define PCMCIA_C2_HOLD_MASK		(0x3f << PCMCIA_C2_HOLD_SHIFT)
++
++
++/*************************************************************************
++ * _REG relative to RSET_SDRAM
++ *************************************************************************/
++
++#define SDRAM_CFG_REG			0x0
++#define SDRAM_CFG_ROW_SHIFT		4
++#define SDRAM_CFG_ROW_MASK		(0x3 << SDRAM_CFG_ROW_SHIFT)
++#define SDRAM_CFG_COL_SHIFT		6
++#define SDRAM_CFG_COL_MASK		(0x3 << SDRAM_CFG_COL_SHIFT)
++#define SDRAM_CFG_32B_SHIFT		10
++#define SDRAM_CFG_32B_MASK		(1 << SDRAM_CFG_32B_SHIFT)
++#define SDRAM_CFG_BANK_SHIFT		13
++#define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
++
++#define SDRAM_PRIO_REG			0x2C
++#define SDRAM_PRIO_MIPS_SHIFT		29
++#define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)
++#define SDRAM_PRIO_ADSL_SHIFT		30
++#define SDRAM_PRIO_ADSL_MASK		(1 << SDRAM_PRIO_ADSL_SHIFT)
++#define SDRAM_PRIO_EN_SHIFT		31
++#define SDRAM_PRIO_EN_MASK		(1 << SDRAM_PRIO_EN_SHIFT)
++
++
++/*************************************************************************
++ * _REG relative to RSET_MEMC
++ *************************************************************************/
++
++#define MEMC_CFG_REG			0x4
++#define MEMC_CFG_32B_SHIFT		1
++#define MEMC_CFG_32B_MASK		(1 << MEMC_CFG_32B_SHIFT)
++#define MEMC_CFG_COL_SHIFT		3
++#define MEMC_CFG_COL_MASK		(0x3 << MEMC_CFG_COL_SHIFT)
++#define MEMC_CFG_ROW_SHIFT		6
++#define MEMC_CFG_ROW_MASK		(0x3 << MEMC_CFG_ROW_SHIFT)
++
++
++/*************************************************************************
++ * _REG relative to RSET_DDR
++ *************************************************************************/
++
++#define DDR_DMIPSPLLCFG_REG		0x18
++#define DMIPSPLLCFG_M1_SHIFT		0
++#define DMIPSPLLCFG_M1_MASK		(0xff << DMIPSPLLCFG_M1_SHIFT)
++#define DMIPSPLLCFG_N1_SHIFT		23
++#define DMIPSPLLCFG_N1_MASK		(0x3f << DMIPSPLLCFG_N1_SHIFT)
++#define DMIPSPLLCFG_N2_SHIFT		29
++#define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
++
++#endif /* BCM63XX_REGS_H_ */
++
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h b/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
+new file mode 100644
+index 0000000..c0fce83
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
+@@ -0,0 +1,11 @@
++#ifndef BCM63XX_TIMER_H_
++#define BCM63XX_TIMER_H_
++
++int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
++void bcm63xx_timer_unregister(int id);
++int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
++int bcm63xx_timer_enable(int id);
++int bcm63xx_timer_disable(int id);
++unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
++
++#endif /* !BCM63XX_TIMER_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h b/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
+new file mode 100644
+index 0000000..1a5c4b1
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
+@@ -0,0 +1,51 @@
++#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
++
++#include <bcm63xx_cpu.h>
++
++#define cpu_has_tlb			1
++#define cpu_has_4kex			1
++#define cpu_has_4k_cache		1
++#define cpu_has_fpu			0
++#define cpu_has_32fpr			0
++#define cpu_has_counter			1
++#define cpu_has_watch			0
++#define cpu_has_divec			1
++#define cpu_has_vce			0
++#define cpu_has_cache_cdex_p		0
++#define cpu_has_cache_cdex_s		0
++#define cpu_has_prefetch		1
++#define cpu_has_mcheck			1
++#define cpu_has_ejtag			1
++#define cpu_has_llsc			1
++#define cpu_has_mips16			0
++#define cpu_has_mdmx			0
++#define cpu_has_mips3d			0
++#define cpu_has_smartmips		0
++#define cpu_has_vtag_icache		0
++
++#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348)
++#define cpu_has_dc_aliases		0
++#endif
++
++#define cpu_has_ic_fills_f_dc		0
++#define cpu_has_pindexed_dcache		0
++
++#define cpu_has_mips32r1		1
++#define cpu_has_mips32r2		0
++#define cpu_has_mips64r1		0
++#define cpu_has_mips64r2		0
++
++#define cpu_has_dsp			0
++#define cpu_has_mipsmt			0
++#define cpu_has_userlocal		0
++
++#define cpu_has_nofpuex			0
++#define cpu_has_64bits			0
++#define cpu_has_64bit_zero_reg		0
++
++#define cpu_dcache_line_size()		16
++#define cpu_icache_line_size()		16
++#define cpu_scache_line_size()		0
++
++#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
+diff --git a/include/asm-mips/mach-bcm63xx/gpio.h b/include/asm-mips/mach-bcm63xx/gpio.h
+new file mode 100644
+index 0000000..dd2c0f3
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/gpio.h
+@@ -0,0 +1,52 @@
++#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
++#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
++
++#include <bcm63xx_gpio.h>
++
++static inline int gpio_is_valid(int number)
++{
++	return (number >= BCM63XX_GPIO_COUNT) ? 0 : 1;
++}
++
++static inline int gpio_request(unsigned gpio, const char *label)
++{
++	return 0;
++}
++
++static inline void gpio_free(unsigned gpio)
++{
++}
++
++static inline int gpio_direction_input(unsigned gpio)
++{
++	bcm63xx_gpio_set_direction(gpio, GPIO_DIR_IN);
++	return 0;
++}
++
++static inline int gpio_direction_output(unsigned gpio, int value)
++{
++	bcm63xx_gpio_set_direction(gpio, GPIO_DIR_OUT);
++	return 0;
++}
++
++static inline int gpio_get_value(unsigned gpio)
++{
++	return bcm63xx_gpio_get_datain(gpio);
++}
++
++static inline void gpio_set_value(unsigned gpio, int value)
++{
++	bcm63xx_gpio_set_dataout(gpio, value);
++}
++
++static inline int gpio_to_irq(unsigned gpio)
++{
++	return gpio;
++}
++
++static inline int irq_to_gpio(unsigned irq)
++{
++	return irq;
++}
++
++#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
+diff --git a/include/asm-mips/mach-bcm63xx/war.h b/include/asm-mips/mach-bcm63xx/war.h
+new file mode 100644
+index 0000000..8e3f3fd
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/war.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
++#define __ASM_MIPS_MACH_BCM63XX_WAR_H
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		0
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/003-add_serial_driver_for_bcm63xx_integr.patch b/target/linux/brcm63xx/patches-2.6.27/003-add_serial_driver_for_bcm63xx_integr.patch
new file mode 100644
index 0000000..32c66ba
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/003-add_serial_driver_for_bcm63xx_integr.patch
@@ -0,0 +1,1038 @@
+From 6c489656b09998ed6a6f857e01ccf630e29358dd Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Fri, 18 Jul 2008 19:35:55 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add serial driver for bcm63xx integrated UART.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Makefile                       |    1 +
+ arch/mips/bcm63xx/dev-uart.c                     |   41 +
+ drivers/serial/Kconfig                           |   19 +
+ drivers/serial/Makefile                          |    1 +
+ drivers/serial/bcm63xx_uart.c                    |  890 ++++++++++++++++++++++
+ include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h |    6 +
+ include/linux/serial_core.h                      |    2 +
+ 7 files changed, 960 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-uart.c
+ create mode 100644 drivers/serial/bcm63xx_uart.c
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h
+
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 4fc0a1c..8f3299e 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,2 +1,3 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
++obj-y		+= dev-uart.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
+new file mode 100644
+index 0000000..5f3d89c
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-uart.c
+@@ -0,0 +1,41 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_uart.h>
++
++static struct resource uart_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device bcm63xx_uart_device = {
++	.name		= "bcm63xx_uart",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(uart_resources),
++	.resource	= uart_resources,
++};
++
++int __init bcm63xx_uart_register(void)
++{
++	uart_resources[0].start = bcm63xx_regset_address(RSET_UART0);
++	uart_resources[0].end = uart_resources[0].start;
++	uart_resources[0].end += RSET_UART_SIZE - 1;
++	uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
++	return platform_device_register(&bcm63xx_uart_device);
++}
+diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
+index 77cb342..52b31a4 100644
+--- a/drivers/serial/Kconfig
++++ b/drivers/serial/Kconfig
+@@ -1421,4 +1421,23 @@ config SPORT_BAUD_RATE
+ 	default 19200 if (SERIAL_SPORT_BAUD_RATE_19200)
+ 	default 9600 if (SERIAL_SPORT_BAUD_RATE_9600)
+ 
++config SERIAL_BCM63XX
++	tristate "bcm63xx serial port support"
++	select SERIAL_CORE
++	depends on BCM63XX
++	help
++	  If you have a bcm63xx CPU, you can enable its onboard
++	  serial port by enabling this options.
++
++          To compile this driver as a module, choose M here: the
++          module will be called bcm963xx_uart.
++
++config SERIAL_BCM63XX_CONSOLE
++	bool "Console on bcm63xx serial port"
++	depends on SERIAL_BCM63XX
++	select SERIAL_CORE_CONSOLE
++	help
++	  If you have enabled the serial port on the bcm63xx CPU
++	  you can make it the console by answering Y to this option.
++
+ endmenu
+diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
+index 7e7383e..84f6cfc 100644
+--- a/drivers/serial/Makefile
++++ b/drivers/serial/Makefile
+@@ -24,6 +24,7 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
+ obj-$(CONFIG_SERIAL_PXA) += pxa.o
+ obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
+ obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
++obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
+ obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
+ obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
+ obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
+diff --git a/drivers/serial/bcm63xx_uart.c b/drivers/serial/bcm63xx_uart.c
+new file mode 100644
+index 0000000..606f4d6
+--- /dev/null
++++ b/drivers/serial/bcm63xx_uart.c
+@@ -0,0 +1,890 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Derived from many drivers using generic_serial interface.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ *
++ *  Serial driver for BCM63xx integrated UART.
++ *
++ * Hardware flow control was _not_ tested since I only have RX/TX on
++ * my board.
++ */
++
++#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/console.h>
++#include <linux/clk.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/sysrq.h>
++#include <linux/serial.h>
++#include <linux/serial_core.h>
++
++#include <bcm63xx_clk.h>
++#include <bcm63xx_irq.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++
++#define BCM63XX_NR_UARTS	1
++
++static struct uart_port ports[BCM63XX_NR_UARTS];
++
++/*
++ * rx interrupt mask / stat
++ *
++ * mask:
++ *  - rx fifo full
++ *  - rx fifo above threshold
++ *  - rx fifo not empty for too long
++ */
++#define UART_RX_INT_MASK	(UART_IR_MASK(UART_IR_RXOVER) |		\
++				UART_IR_MASK(UART_IR_RXTHRESH) |	\
++				UART_IR_MASK(UART_IR_RXTIMEOUT))
++
++#define UART_RX_INT_STAT	(UART_IR_STAT(UART_IR_RXOVER) |		\
++				UART_IR_STAT(UART_IR_RXTHRESH) |	\
++				UART_IR_STAT(UART_IR_RXTIMEOUT))
++
++/*
++ * tx interrupt mask / stat
++ *
++ * mask:
++ * - tx fifo empty
++ * - tx fifo below threshold
++ */
++#define UART_TX_INT_MASK	(UART_IR_MASK(UART_IR_TXEMPTY) |	\
++				UART_IR_MASK(UART_IR_TXTRESH))
++
++#define UART_TX_INT_STAT	(UART_IR_STAT(UART_IR_TXEMPTY) |	\
++				UART_IR_STAT(UART_IR_TXTRESH))
++
++/*
++ * external input interrupt
++ *
++ * mask: any edge on CTS, DCD
++ */
++#define UART_EXTINP_INT_MASK	(UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
++				 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
++
++/*
++ * handy uart register accessor
++ */
++static inline unsigned int bcm_uart_readl(struct uart_port *port,
++					 unsigned int offset)
++{
++	return bcm_readl(port->membase + offset);
++}
++
++static inline void bcm_uart_writel(struct uart_port *port,
++				  unsigned int value, unsigned int offset)
++{
++	bcm_writel(value, port->membase + offset);
++}
++
++/*
++ * serial core request to check if uart tx fifo is empty
++ */
++static unsigned int bcm_uart_tx_empty(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_IR_REG);
++	return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
++}
++
++/*
++ * serial core request to set RTS and DTR pin state and loopback mode
++ */
++static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_MCTL_REG);
++	val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
++	/* invert of written value is reflected on the pin */
++	if (!(mctrl & TIOCM_DTR))
++		val |= UART_MCTL_DTR_MASK;
++	if (!(mctrl & TIOCM_RTS))
++		val |= UART_MCTL_RTS_MASK;
++	bcm_uart_writel(port, val, UART_MCTL_REG);
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	if (mctrl & TIOCM_LOOP)
++		val |= UART_CTL_LOOPBACK_MASK;
++	else
++		val &= ~UART_CTL_LOOPBACK_MASK;
++	bcm_uart_writel(port, val, UART_CTL_REG);
++}
++
++/*
++ * serial core request to return RI, CTS, DCD and DSR pin state
++ */
++static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
++{
++	unsigned int val, mctrl;
++
++	mctrl = 0;
++	val = bcm_uart_readl(port, UART_EXTINP_REG);
++	if (val & UART_EXTINP_RI_MASK)
++		mctrl |= TIOCM_RI;
++	if (val & UART_EXTINP_CTS_MASK)
++		mctrl |= TIOCM_CTS;
++	if (val & UART_EXTINP_DCD_MASK)
++		mctrl |= TIOCM_CD;
++	if (val & UART_EXTINP_DSR_MASK)
++		mctrl |= TIOCM_DSR;
++	return mctrl;
++}
++
++/*
++ * serial core request to disable tx ASAP (used for flow control)
++ */
++static void bcm_uart_stop_tx(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val &= ~(UART_CTL_TXEN_MASK);
++	bcm_uart_writel(port, val, UART_CTL_REG);
++
++	val = bcm_uart_readl(port, UART_IR_REG);
++	val &= ~UART_TX_INT_MASK;
++	bcm_uart_writel(port, val, UART_IR_REG);
++}
++
++/*
++ * serial core request to (re)enable tx
++ */
++static void bcm_uart_start_tx(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_IR_REG);
++	val |= UART_TX_INT_MASK;
++	bcm_uart_writel(port, val, UART_IR_REG);
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val |= UART_CTL_TXEN_MASK;
++	bcm_uart_writel(port, val, UART_CTL_REG);
++}
++
++/*
++ * serial core request to stop rx, called before port shutdown
++ */
++static void bcm_uart_stop_rx(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_IR_REG);
++	val &= ~UART_RX_INT_MASK;
++	bcm_uart_writel(port, val, UART_IR_REG);
++}
++
++/*
++ * serial core request to enable modem status interrupt reporting
++ */
++static void bcm_uart_enable_ms(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_IR_REG);
++	val |= UART_IR_MASK(UART_IR_EXTIP);
++	bcm_uart_writel(port, val, UART_IR_REG);
++}
++
++/*
++ * serial core request to start/stop emitting break char
++ */
++static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
++{
++	unsigned long flags;
++	unsigned int val;
++
++	spin_lock_irqsave(&port->lock, flags);
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	if (ctl)
++		val |= UART_CTL_XMITBRK_MASK;
++	else
++		val &= ~UART_CTL_XMITBRK_MASK;
++	bcm_uart_writel(port, val, UART_CTL_REG);
++
++	spin_unlock_irqrestore(&port->lock, flags);
++}
++
++/*
++ * return port type in string format
++ */
++static const char *bcm_uart_type(struct uart_port *port)
++{
++	return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
++}
++
++/*
++ * read all chars in rx fifo and send them to core
++ */
++static void bcm_uart_do_rx(struct uart_port *port)
++{
++	struct tty_struct *tty;
++	unsigned int max_count;
++
++	/* limit number of char read in interrupt, should not be
++	 * higher than fifo size anyway since we're much faster than
++	 * serial port */
++	max_count = 32;
++	tty = port->info->port.tty;
++	do {
++		unsigned int iestat, c, cstat;
++		char flag;
++
++		/* get overrun/fifo empty information from ier
++		 * register */
++		iestat = bcm_uart_readl(port, UART_IR_REG);
++		if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
++			break;
++
++		cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
++		port->icount.rx++;
++		flag = TTY_NORMAL;
++		c &= 0xff;
++
++		if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
++			/* do stats first */
++			if (cstat & UART_FIFO_BRKDET_MASK) {
++				port->icount.brk++;
++				if (uart_handle_break(port))
++					continue;
++			}
++
++			if (cstat & UART_FIFO_PARERR_MASK)
++				port->icount.parity++;
++			if (cstat & UART_FIFO_FRAMEERR_MASK)
++				port->icount.frame++;
++
++			/* update flag wrt read_status_mask */
++			cstat &= port->read_status_mask;
++			if (cstat & UART_FIFO_BRKDET_MASK)
++				flag = TTY_BREAK;
++			if (cstat & UART_FIFO_FRAMEERR_MASK)
++				flag = TTY_FRAME;
++			if (cstat & UART_FIFO_PARERR_MASK)
++				flag = TTY_PARITY;
++		}
++
++		if (uart_handle_sysrq_char(port, c))
++			continue;
++
++		if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
++			port->icount.overrun++;
++			tty_insert_flip_char(tty, 0, TTY_OVERRUN);
++		}
++
++		if ((cstat & port->ignore_status_mask) == 0)
++			tty_insert_flip_char(tty, c, flag);
++
++	} while (--max_count);
++
++	tty_flip_buffer_push(tty);
++}
++
++/*
++ * fill tx fifo with chars to send, stop when fifo is about to be full
++ * or when all chars have been sent.
++ */
++static void bcm_uart_do_tx(struct uart_port *port)
++{
++	struct circ_buf *xmit;
++	unsigned int val, max_count;
++
++	if (port->x_char) {
++		bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
++		port->icount.tx++;
++		port->x_char = 0;
++		return;
++	}
++
++	if (uart_tx_stopped(port)) {
++		bcm_uart_stop_tx(port);
++		return;
++	}
++
++	xmit = &port->info->xmit;
++	if (uart_circ_empty(xmit))
++		goto txq_empty;
++
++	val = bcm_uart_readl(port, UART_MCTL_REG);
++	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
++	max_count = port->fifosize - val;
++
++	while (max_count--) {
++		unsigned int c;
++
++		c = xmit->buf[xmit->tail];
++		bcm_uart_writel(port, c, UART_FIFO_REG);
++		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++		port->icount.tx++;
++		if (uart_circ_empty(xmit))
++			break;
++	}
++
++	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++		uart_write_wakeup(port);
++
++	if (uart_circ_empty(xmit))
++		goto txq_empty;
++	return;
++
++txq_empty:
++	/* nothing to send, disable transmit interrupt */
++	val = bcm_uart_readl(port, UART_IR_REG);
++	val &= ~UART_TX_INT_MASK;
++	bcm_uart_writel(port, val, UART_IR_REG);
++	return;
++}
++
++/*
++ * process uart interrupt
++ */
++static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
++{
++	struct uart_port *port;
++	unsigned int irqstat;
++
++	port = dev_id;
++	spin_lock(&port->lock);
++
++	irqstat = bcm_uart_readl(port, UART_IR_REG);
++	if (irqstat & UART_RX_INT_STAT)
++		bcm_uart_do_rx(port);
++
++	if (irqstat & UART_TX_INT_STAT)
++		bcm_uart_do_tx(port);
++
++	if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
++		unsigned int estat;
++
++		estat = bcm_uart_readl(port, UART_EXTINP_REG);
++		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
++			uart_handle_cts_change(port,
++					       estat & UART_EXTINP_CTS_MASK);
++		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
++			uart_handle_dcd_change(port,
++					       estat & UART_EXTINP_DCD_MASK);
++	}
++
++	spin_unlock(&port->lock);
++	return IRQ_HANDLED;
++}
++
++/*
++ * enable rx & tx operation on uart
++ */
++static void bcm_uart_enable(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
++	bcm_uart_writel(port, val, UART_CTL_REG);
++}
++
++/*
++ * disable rx & tx operation on uart
++ */
++static void bcm_uart_disable(struct uart_port *port)
++{
++	unsigned int val;
++
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
++		 UART_CTL_RXEN_MASK);
++	bcm_uart_writel(port, val, UART_CTL_REG);
++}
++
++/*
++ * clear all unread data in rx fifo and unsent data in tx fifo
++ */
++static void bcm_uart_flush(struct uart_port *port)
++{
++	unsigned int val;
++
++	/* empty rx and tx fifo */
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
++	bcm_uart_writel(port, val, UART_CTL_REG);
++
++	/* read any pending char to make sure all irq status are
++	 * cleared */
++	(void)bcm_uart_readl(port, UART_FIFO_REG);
++}
++
++/*
++ * serial core request to initialize uart and start rx operation
++ */
++static int bcm_uart_startup(struct uart_port *port)
++{
++	unsigned int val;
++	int ret;
++
++	/* mask all irq and flush port */
++	bcm_uart_disable(port);
++	bcm_uart_writel(port, 0, UART_IR_REG);
++	bcm_uart_flush(port);
++
++	/* clear any pending external input interrupt */
++	(void)bcm_uart_readl(port, UART_EXTINP_REG);
++
++	/* set rx/tx fifo thresh to fifo half size */
++	val = bcm_uart_readl(port, UART_MCTL_REG);
++	val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
++	val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
++	val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
++	bcm_uart_writel(port, val, UART_MCTL_REG);
++
++	/* set rx fifo timeout to 1 char time */
++	val = bcm_uart_readl(port, UART_CTL_REG);
++	val &= ~UART_CTL_RXTMOUTCNT_MASK;
++	val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
++	bcm_uart_writel(port, val, UART_CTL_REG);
++
++	/* report any edge on dcd and cts */
++	val = UART_EXTINP_INT_MASK;
++	val |= UART_EXTINP_DCD_NOSENSE_MASK;
++	val |= UART_EXTINP_CTS_NOSENSE_MASK;
++	bcm_uart_writel(port, val, UART_EXTINP_REG);
++
++	/* register irq and enable rx interrupts */
++	ret = request_irq(port->irq, bcm_uart_interrupt, 0,
++			  bcm_uart_type(port), port);
++	if (ret)
++		return ret;
++	bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
++	bcm_uart_enable(port);
++	return 0;
++}
++
++/*
++ * serial core request to flush & disable uart
++ */
++static void bcm_uart_shutdown(struct uart_port *port)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&port->lock, flags);
++	bcm_uart_writel(port, 0, UART_IR_REG);
++	spin_unlock_irqrestore(&port->lock, flags);
++
++	bcm_uart_disable(port);
++	bcm_uart_flush(port);
++	free_irq(port->irq, port);
++}
++
++/*
++ * serial core request to change current uart setting
++ */
++static void bcm_uart_set_termios(struct uart_port *port,
++				 struct ktermios *new,
++				 struct ktermios *old)
++{
++	unsigned int ctl, baud, quot, ier;
++	unsigned long flags;
++
++	spin_lock_irqsave(&port->lock, flags);
++
++	/* disable uart while changing speed */
++	bcm_uart_disable(port);
++	bcm_uart_flush(port);
++
++	/* update Control register */
++	ctl = bcm_uart_readl(port, UART_CTL_REG);
++	ctl &= ~UART_CTL_BITSPERSYM_MASK;
++
++	switch (new->c_cflag & CSIZE) {
++	case CS5:
++		ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
++		break;
++	case CS6:
++		ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
++		break;
++	case CS7:
++		ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
++		break;
++	default:
++		ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
++		break;
++	}
++
++	ctl &= ~UART_CTL_STOPBITS_MASK;
++	if (new->c_cflag & CSTOPB)
++		ctl |= UART_CTL_STOPBITS_2;
++	else
++		ctl |= UART_CTL_STOPBITS_1;
++
++	ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
++	if (new->c_cflag & PARENB)
++		ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
++	ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
++	if (new->c_cflag & PARODD)
++		ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
++	bcm_uart_writel(port, ctl, UART_CTL_REG);
++
++	/* update Baudword register */
++	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
++	quot = uart_get_divisor(port, baud) - 1;
++	bcm_uart_writel(port, quot, UART_BAUD_REG);
++
++	/* update Interrupt register */
++	ier = bcm_uart_readl(port, UART_IR_REG);
++
++	ier &= ~UART_IR_MASK(UART_IR_EXTIP);
++	if (UART_ENABLE_MS(port, new->c_cflag))
++		ier |= UART_IR_MASK(UART_IR_EXTIP);
++
++	bcm_uart_writel(port, ier, UART_IR_REG);
++
++	/* update read/ignore mask */
++	port->read_status_mask = UART_FIFO_VALID_MASK;
++	if (new->c_iflag & INPCK) {
++		port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
++		port->read_status_mask |= UART_FIFO_PARERR_MASK;
++	}
++	if (new->c_iflag & (BRKINT))
++		port->read_status_mask |= UART_FIFO_BRKDET_MASK;
++
++	port->ignore_status_mask = 0;
++	if (new->c_iflag & IGNPAR)
++		port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
++	if (new->c_iflag & IGNBRK)
++		port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
++	if (!(new->c_cflag & CREAD))
++		port->ignore_status_mask |= UART_FIFO_VALID_MASK;
++
++	uart_update_timeout(port, new->c_cflag, baud);
++	bcm_uart_enable(port);
++	spin_unlock_irqrestore(&port->lock, flags);
++}
++
++/*
++ * serial core request to claim uart iomem
++ */
++static int bcm_uart_request_port(struct uart_port *port)
++{
++	unsigned int size;
++
++	size = RSET_UART_SIZE;
++	if (!request_mem_region(port->mapbase, size, "bcm63xx")) {
++		dev_err(port->dev, "Memory region busy\n");
++		return -EBUSY;
++	}
++
++	port->membase = ioremap(port->mapbase, size);
++	if (!port->membase) {
++		dev_err(port->dev, "Unable to map registers\n");
++		release_mem_region(port->mapbase, size);
++		return -EBUSY;
++	}
++	return 0;
++}
++
++/*
++ * serial core request to release uart iomem
++ */
++static void bcm_uart_release_port(struct uart_port *port)
++{
++	release_mem_region(port->mapbase, RSET_UART_SIZE);
++	iounmap(port->membase);
++}
++
++/*
++ * serial core request to do any port required autoconfiguration
++ */
++static void bcm_uart_config_port(struct uart_port *port, int flags)
++{
++	if (flags & UART_CONFIG_TYPE) {
++		if (bcm_uart_request_port(port))
++			return;
++		port->type = PORT_BCM63XX;
++	}
++}
++
++/*
++ * serial core request to check that port information in serinfo are
++ * suitable
++ */
++static int bcm_uart_verify_port(struct uart_port *port,
++				struct serial_struct *serinfo)
++{
++	if (port->type != PORT_BCM63XX)
++		return -EINVAL;
++	if (port->irq != serinfo->irq)
++		return -EINVAL;
++	if (port->iotype != serinfo->io_type)
++		return -EINVAL;
++	if (port->mapbase != (unsigned long)serinfo->iomem_base)
++		return -EINVAL;
++	return 0;
++}
++
++/* serial core callbacks */
++static struct uart_ops bcm_uart_ops = {
++	.tx_empty	= bcm_uart_tx_empty,
++	.get_mctrl	= bcm_uart_get_mctrl,
++	.set_mctrl	= bcm_uart_set_mctrl,
++	.start_tx	= bcm_uart_start_tx,
++	.stop_tx	= bcm_uart_stop_tx,
++	.stop_rx	= bcm_uart_stop_rx,
++	.enable_ms	= bcm_uart_enable_ms,
++	.break_ctl	= bcm_uart_break_ctl,
++	.startup	= bcm_uart_startup,
++	.shutdown	= bcm_uart_shutdown,
++	.set_termios	= bcm_uart_set_termios,
++	.type		= bcm_uart_type,
++	.release_port	= bcm_uart_release_port,
++	.request_port	= bcm_uart_request_port,
++	.config_port	= bcm_uart_config_port,
++	.verify_port	= bcm_uart_verify_port,
++};
++
++
++
++#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
++static inline void wait_for_xmitr(struct uart_port *port)
++{
++	unsigned int tmout;
++
++	/* Wait up to 10ms for the character(s) to be sent. */
++	tmout = 10000;
++	while (--tmout) {
++		unsigned int val;
++
++		val = bcm_uart_readl(port, UART_IR_REG);
++		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
++			break;
++		udelay(1);
++	}
++
++	/* Wait up to 1s for flow control if necessary */
++	if (port->flags & UPF_CONS_FLOW) {
++		tmout = 1000000;
++		while (--tmout) {
++			unsigned int val;
++
++			val = bcm_uart_readl(port, UART_EXTINP_REG);
++			if (val & UART_EXTINP_CTS_MASK)
++				break;
++			udelay(1);
++		}
++	}
++}
++
++/*
++ * output given char
++ */
++static void bcm_console_putchar(struct uart_port *port, int ch)
++{
++	wait_for_xmitr(port);
++	bcm_uart_writel(port, ch, UART_FIFO_REG);
++}
++
++/*
++ * console core request to output given string
++ */
++static void bcm_console_write(struct console *co, const char *s,
++			      unsigned int count)
++{
++	struct uart_port *port;
++	unsigned long flags;
++	int locked;
++
++	port = &ports[co->index];
++
++	local_irq_save(flags);
++	if (port->sysrq) {
++		/* bcm_uart_interrupt() already took the lock */
++		locked = 0;
++	} else if (oops_in_progress) {
++		locked = spin_trylock(&port->lock);
++	} else {
++		spin_lock(&port->lock);
++		locked = 1;
++	}
++
++	/* call helper to deal with \r\n */
++	uart_console_write(port, s, count, bcm_console_putchar);
++
++	/* and wait for char to be transmitted */
++	wait_for_xmitr(port);
++
++	if (locked)
++		spin_unlock(&port->lock);
++	local_irq_restore(flags);
++}
++
++/*
++ * console core request to setup given console, find matching uart
++ * port and setup it.
++ */
++static int bcm_console_setup(struct console *co, char *options)
++{
++	struct uart_port *port;
++	int baud = 9600;
++	int bits = 8;
++	int parity = 'n';
++	int flow = 'n';
++
++	if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
++		return -EINVAL;
++	port = &ports[co->index];
++	if (!port->membase)
++		return -ENODEV;
++	if (options)
++		uart_parse_options(options, &baud, &parity, &bits, &flow);
++
++	return uart_set_options(port, co, baud, parity, bits, flow);
++}
++
++static struct uart_driver bcm_uart_driver;
++
++static struct console bcm63xx_console = {
++	.name		= "ttyS",
++	.write		= bcm_console_write,
++	.device		= uart_console_device,
++	.setup		= bcm_console_setup,
++	.flags		= CON_PRINTBUFFER,
++	.index		= -1,
++	.data		= &bcm_uart_driver,
++};
++
++static int __init bcm63xx_console_init(void)
++{
++	register_console(&bcm63xx_console);
++	return 0;
++}
++
++console_initcall(bcm63xx_console_init);
++
++#define BCM63XX_CONSOLE	&bcm63xx_console
++#else
++#define BCM63XX_CONSOLE	NULL
++#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
++
++static struct uart_driver bcm_uart_driver = {
++	.owner		= THIS_MODULE,
++	.driver_name	= "bcm63xx_uart",
++	.dev_name	= "ttyS",
++	.major		= TTY_MAJOR,
++	.minor		= 64,
++	.nr		= 1,
++	.cons		= BCM63XX_CONSOLE,
++};
++
++/*
++ * platform driver probe/remove callback
++ */
++static int __devinit bcm_uart_probe(struct platform_device *pdev)
++{
++	struct resource *res_mem, *res_irq;
++	struct uart_port *port;
++	struct clk *clk;
++	int ret;
++
++	if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
++		return -EINVAL;
++
++	if (ports[pdev->id].membase)
++		return -EBUSY;
++
++	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res_mem)
++		return -ENODEV;
++
++	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	if (!res_irq)
++		return -ENODEV;
++
++	clk = clk_get(&pdev->dev, "periph");
++	if (IS_ERR(clk))
++		return -ENODEV;
++
++	port = &ports[pdev->id];
++	memset(port, 0, sizeof(*port));
++	port->iotype = UPIO_MEM;
++	port->mapbase = res_mem->start;
++	port->irq = res_irq->start;
++	port->ops = &bcm_uart_ops;
++	port->flags = UPF_BOOT_AUTOCONF;
++	port->dev = &pdev->dev;
++	port->fifosize = 16;
++	port->uartclk = clk_get_rate(clk) / 2;
++	clk_put(clk);
++
++	ret = uart_add_one_port(&bcm_uart_driver, port);
++	if (ret) {
++		kfree(port);
++		return ret;
++	}
++	platform_set_drvdata(pdev, port);
++	return 0;
++}
++
++static int __devexit bcm_uart_remove(struct platform_device *pdev)
++{
++	struct uart_port *port;
++
++	port = platform_get_drvdata(pdev);
++	uart_remove_one_port(&bcm_uart_driver, port);
++	platform_set_drvdata(pdev, NULL);
++	/* mark port as free */
++	ports[pdev->id].membase = 0;
++	return 0;
++}
++
++/*
++ * platform driver stuff
++ */
++static struct platform_driver bcm_uart_platform_driver = {
++	.probe	= bcm_uart_probe,
++	.remove	= __devexit_p(bcm_uart_remove),
++	.driver	= {
++		.owner = THIS_MODULE,
++		.name  = "bcm63xx_uart",
++	},
++};
++
++static int __init bcm_uart_init(void)
++{
++	int ret;
++
++	ret = uart_register_driver(&bcm_uart_driver);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&bcm_uart_platform_driver);
++	if (ret)
++		uart_unregister_driver(&bcm_uart_driver);
++
++	return ret;
++}
++
++static void __exit bcm_uart_exit(void)
++{
++	platform_driver_unregister(&bcm_uart_platform_driver);
++	uart_unregister_driver(&bcm_uart_driver);
++}
++
++module_init(bcm_uart_init);
++module_exit(bcm_uart_exit);
++
++MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
++MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver");
++MODULE_LICENSE("GPL");
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h
+new file mode 100644
+index 0000000..bf348f5
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_uart.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_UART_H_
++#define BCM63XX_DEV_UART_H_
++
++int bcm63xx_uart_register(void);
++
++#endif /* BCM63XX_DEV_UART_H_ */
+diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
+index 3b2f6c0..f49ddff 100644
+--- a/include/linux/serial_core.h
++++ b/include/linux/serial_core.h
+@@ -155,6 +155,8 @@
+ 
+ #define PORT_SC26XX	82
+ 
++#define PORT_BCM63XX		83
++
+ #ifdef __KERNEL__
+ 
+ #include <linux/compiler.h>
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/004_add_pci_support.patch b/target/linux/brcm63xx/patches-2.6.27/004_add_pci_support.patch
new file mode 100644
index 0000000..0070f64
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/004_add_pci_support.patch
@@ -0,0 +1,504 @@
+From 2a7fa2dbbf68650644f807a50cc2d84ca30835c1 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Sun, 21 Sep 2008 04:47:13 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add PCI support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Kconfig                       |    2 +
+ arch/mips/bcm63xx/setup.c                       |    2 +
+ arch/mips/pci/Makefile                          |    2 +
+ arch/mips/pci/fixup-bcm63xx.c                   |   21 +++
+ arch/mips/pci/ops-bcm63xx.c                     |  179 +++++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.c                     |  178 ++++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.h                     |   27 ++++
+ include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h |    6 +
+ 8 files changed, 417 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/pci/fixup-bcm63xx.c
+ create mode 100644 arch/mips/pci/ops-bcm63xx.c
+ create mode 100644 arch/mips/pci/pci-bcm63xx.c
+ create mode 100644 arch/mips/pci/pci-bcm63xx.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
+
+diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
+index e6d2699..7ca370a 100644
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -3,7 +3,9 @@ menu "CPU support"
+ 
+ config BCM63XX_CPU_6348
+ 	bool "support 6348 CPU"
++	select HW_HAS_PCI
+ 
+ config BCM63XX_CPU_6358
+ 	bool "support 6358 CPU"
++	select HW_HAS_PCI
+ endmenu
+diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
+index 55c51a9..4d8b127 100644
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -105,4 +105,6 @@ void __init plat_mem_setup(void)
+ 	pm_power_off = bcm63xx_machine_halt;
+ 
+ 	set_io_port_base(0);
++	ioport_resource.start = 0;
++	ioport_resource.end = ~0;
+ }
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index c8c32f4..0b688a8 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX)	+= ops-vr41xx.o pci-vr41xx.o
+ obj-$(CONFIG_MARKEINS)		+= ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
+ obj-$(CONFIG_PCI_TX4927)	+= ops-tx4927.o
+ obj-$(CONFIG_BCM47XX)		+= pci-bcm47xx.o
++obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o fixup-bcm63xx.o \
++					ops-bcm63xx.o
+ 
+ #
+ # These are still pretty much in the old state, watch, go blind.
+diff --git a/arch/mips/pci/fixup-bcm63xx.c b/arch/mips/pci/fixup-bcm63xx.c
+new file mode 100644
+index 0000000..3408630
+--- /dev/null
++++ b/arch/mips/pci/fixup-bcm63xx.c
+@@ -0,0 +1,21 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <bcm63xx_cpu.h>
++
++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	return bcm63xx_get_irq_number(IRQ_PCI);
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
+diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
+new file mode 100644
+index 0000000..f8dce9d
+--- /dev/null
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -0,0 +1,179 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++
++#include "pci-bcm63xx.h"
++
++/*
++ * swizzle 32bits data to return only the needed part
++ */
++static int postprocess_read(u32 data, int where, unsigned int size)
++{
++	u32 ret;
++
++	ret = 0;
++	switch (size) {
++	case 1:
++		ret = (data >> ((where & 3) << 3)) & 0xff;
++		break;
++	case 2:
++		ret = (data >> ((where & 3) << 3)) & 0xffff;
++		break;
++	case 4:
++		ret = data;
++		break;
++	}
++	return ret;
++}
++
++static int preprocess_write(u32 orig_data, u32 val, int where,
++			    unsigned int size)
++{
++	u32 ret;
++
++	ret = 0;
++	switch (size) {
++	case 1:
++		ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
++			(val << ((where & 3) << 3));
++		break;
++	case 2:
++		ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
++			(val << ((where & 3) << 3));
++		break;
++	case 4:
++		ret = val;
++		break;
++	}
++	return ret;
++}
++
++/*
++ * setup hardware for a configuration cycle with given parameters
++ */
++static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
++				    unsigned int devfn, int where)
++{
++	unsigned int slot, func, reg;
++	u32 val;
++
++	slot = PCI_SLOT(devfn);
++	func = PCI_FUNC(devfn);
++	reg = where >> 2;
++
++	/* sanity check */
++	if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
++		return 1;
++
++	if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
++		return 1;
++
++	if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
++		return 1;
++
++	/* ok, setup config access */
++	val = (reg << MPI_L2PCFG_REG_SHIFT);
++	val |= (func << MPI_L2PCFG_FUNC_SHIFT);
++	val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
++	val |= MPI_L2PCFG_CFG_USEREG_MASK;
++	val |= MPI_L2PCFG_CFG_SEL_MASK;
++	/* type 0 cycle for local bus, type 1 cycle for anything else */
++	if (type != 0) {
++		/* FIXME: how to specify bus ??? */
++		val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
++	}
++	bcm_mpi_writel(val, MPI_L2PCFG_REG);
++
++	return 0;
++}
++
++static int bcm63xx_do_cfg_read(int type, unsigned int busn,
++				unsigned int devfn, int where, int size,
++				u32 *val)
++{
++	u32 data;
++
++	/* two phase cycle, first we write address, then read data at
++	 * another location, caller already has a spinlock so no need
++	 * to add one here  */
++	if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++	iob();
++	data = le32_to_cpu(__raw_readl(pci_iospace_start));
++	/* restore IO space normal behaviour */
++	bcm_mpi_writel(0, MPI_L2PCFG_REG);
++
++	*val = postprocess_read(data, where, size);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int bcm63xx_do_cfg_write(int type, unsigned int busn,
++				 unsigned int devfn, int where, int size,
++				 u32 val)
++{
++	u32 data;
++
++	/* two phase cycle, first we write address, then write data to
++	 * another location, caller already has a spinlock so no need
++	 * to add one here  */
++	if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++	iob();
++
++	data = le32_to_cpu(__raw_readl(pci_iospace_start));
++	data = preprocess_write(data, val, where, size);
++
++	__raw_writel(cpu_to_le32(data), pci_iospace_start);
++	wmb();
++	/* no way to know the access is done, we have to wait */
++	udelay(500);
++	/* restore IO space normal behaviour */
++	bcm_mpi_writel(0, MPI_L2PCFG_REG);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
++			     int where, int size, u32 *val)
++{
++	int type;
++
++	type = bus->parent ? 1 : 0;
++
++	if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return bcm63xx_do_cfg_read(type, bus->number, devfn,
++				    where, size, val);
++}
++
++static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
++			      int where, int size, u32 val)
++{
++	int type;
++
++	type = bus->parent ? 1 : 0;
++
++	if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return bcm63xx_do_cfg_write(type, bus->number, devfn,
++				     where, size, val);
++}
++
++struct pci_ops bcm63xx_pci_ops = {
++	.read   = bcm63xx_pci_read,
++	.write  = bcm63xx_pci_write
++};
+diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
+new file mode 100644
+index 0000000..52bac8e
+--- /dev/null
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -0,0 +1,178 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <asm/bootinfo.h>
++
++#include "pci-bcm63xx.h"
++
++/* allow PCI to be disabled at runtime depending on board nvram
++ * configuration */
++int bcm63xx_pci_enabled = 0;
++
++static struct resource bcm_pci_mem_resource = {
++	.name   = "bcm63xx PCI memory space",
++	.start  = BCM_PCI_MEM_BASE_PA,
++	.end    = BCM_PCI_MEM_END_PA,
++	.flags  = IORESOURCE_MEM
++};
++
++static struct resource bcm_pci_io_resource = {
++	.name   = "bcm63xx PCI IO space",
++	.start  = BCM_PCI_IO_BASE_PA,
++	.end    = BCM_PCI_IO_END_PA,
++	.flags  = IORESOURCE_IO
++};
++
++struct pci_controller bcm63xx_controller = {
++	.pci_ops	= &bcm63xx_pci_ops,
++	.io_resource	= &bcm_pci_io_resource,
++	.mem_resource	= &bcm_pci_mem_resource,
++};
++
++static u32 bcm63xx_int_cfg_readl(u32 reg)
++{
++	u32 tmp;
++
++	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
++	tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
++	bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
++	iob();
++	return bcm_mpi_readl(MPI_PCICFGDATA_REG);
++}
++
++static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
++{
++	u32 tmp;
++
++	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
++	tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
++	bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
++	bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
++}
++
++void __iomem *pci_iospace_start;
++
++static int __init bcm63xx_pci_init(void)
++{
++	unsigned int mem_size;
++	u32 val;
++
++	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
++		return -ENODEV;
++
++	if (!bcm63xx_pci_enabled)
++		return -ENODEV;
++
++	/*
++	 * configuration  access are  done through  IO space,  remap 4
++	 * first bytes to access it from CPU.
++	 *
++	 * this means that  no io access from CPU  should happen while
++	 * we do a configuration cycle,  but there's no way we can add
++	 * a spinlock for each io access, so this is currently kind of
++	 * broken on SMP.
++	 */
++	pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
++	if (!pci_iospace_start)
++		return -ENOMEM;
++
++	/* setup local bus to PCI access (PCI memory) */
++	val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
++	bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
++	bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
++	bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
++
++	/* set Cardbus IDSEL (type 0 cfg access on primary bus for
++	 * this IDSEL will be done on Cardbus instead) */
++	val = bcm_pcmcia_readl(PCMCIA_C1_REG);
++	val &= ~PCMCIA_C1_CBIDSEL_MASK;
++	val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
++	bcm_pcmcia_writel(val, PCMCIA_C1_REG);
++
++	/* disable second access windows */
++	bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
++
++	/* setup local bus  to PCI access (IO memory),  we have only 1
++	 * IO window  for both PCI  and cardbus, but it  cannot handle
++	 * both  at the  same time,  assume standard  PCI for  now, if
++	 * cardbus card has  IO zone, PCI fixup will  change window to
++	 * cardbus */
++	val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
++	bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
++	bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
++	bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
++
++	/* enable PCI related GPIO pins */
++	bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
++
++	/* setup PCI to local bus access, used by PCI device to target
++	 * local RAM while bus mastering */
++	bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
++	if (BCMCPU_IS_6358())
++		val = MPI_SP0_REMAP_ENABLE_MASK;
++	else
++		val = 0;
++	bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
++
++	bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
++	bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
++
++	mem_size = bcm63xx_get_memory_size();
++
++	/* 6348 before rev b0 exposes only 16 MB of RAM memory through
++	 * PCI, throw a warning if we have more memory */
++	if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
++		if (mem_size > (16 * 1024 * 1024))
++			printk(KERN_WARNING "bcm63xx: this CPU "
++			       "revision cannot handle more than 16MB "
++			       "of RAM for PCI bus mastering\n");
++	} else {
++		/* setup sp0 range to local RAM size */
++		bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
++		bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
++	}
++
++	/* change  host bridge  retry  counter to  infinite number  of
++	 * retry,  needed for  some broadcom  wifi cards  with Silicon
++	 * Backplane bus where access to srom seems very slow  */
++	val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
++	val &= ~REG_TIMER_RETRY_MASK;
++	bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
++
++	/* enable memory decoder and bus mastering */
++	val = bcm63xx_int_cfg_readl(PCI_COMMAND);
++	val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
++	bcm63xx_int_cfg_writel(val, PCI_COMMAND);
++
++	/* enable read prefetching & disable byte swapping for bus
++	 * mastering transfers */
++	val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
++	val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
++	val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
++	val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
++	val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
++	bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
++
++	/* enable pci interrupt */
++	val = bcm_mpi_readl(MPI_LOCINT_REG);
++	val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
++	bcm_mpi_writel(val, MPI_LOCINT_REG);
++
++	register_pci_controller(&bcm63xx_controller);
++
++	/* mark memory space used for IO mapping as reserved */
++	request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
++			   "bcm63xx PCI IO space");
++	return 0;
++}
++
++arch_initcall(bcm63xx_pci_init);
+diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
+new file mode 100644
+index 0000000..a6e594e
+--- /dev/null
++++ b/arch/mips/pci/pci-bcm63xx.h
+@@ -0,0 +1,27 @@
++#ifndef PCI_BCM63XX_H_
++#define PCI_BCM63XX_H_
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_dev_pci.h>
++
++/*
++ * Cardbus shares  the PCI bus, but has  no IDSEL, so a  special id is
++ * reserved for it.  If you have a standard PCI device at this id, you
++ * need to change the following definition.
++ */
++#define CARDBUS_PCI_IDSEL	0x8
++
++/*
++ * defined in ops-bcm63xx.c
++ */
++extern struct pci_ops bcm63xx_pci_ops;
++extern struct pci_ops bcm63xx_cb_ops;
++
++/*
++ * defined in pci-bcm63xx.c
++ */
++extern void __iomem *pci_iospace_start;
++
++#endif /* ! PCI_BCM63XX_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
+new file mode 100644
+index 0000000..c549344
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_PCI_H_
++#define BCM63XX_DEV_PCI_H_
++
++extern int bcm63xx_pci_enabled;
++
++#endif /* BCM63XX_DEV_PCI_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/005-change_pci_code_to_emulate_a_fake_cardbus_adapter.patch b/target/linux/brcm63xx/patches-2.6.27/005-change_pci_code_to_emulate_a_fake_cardbus_adapter.patch
new file mode 100644
index 0000000..6119815
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/005-change_pci_code_to_emulate_a_fake_cardbus_adapter.patch
@@ -0,0 +1,389 @@
+From 6891d3c1014cf56dc76ec583b69d341ea47984d6 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Fri, 18 Jul 2008 20:34:35 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Change PCI code to emulate a fake cardbus bridge.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/pci/ops-bcm63xx.c |  288 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.c |   44 +++++++
+ 2 files changed, 332 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
+index f8dce9d..822ae17 100644
+--- a/arch/mips/pci/ops-bcm63xx.c
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -177,3 +177,291 @@ struct pci_ops bcm63xx_pci_ops = {
+ 	.read   = bcm63xx_pci_read,
+ 	.write  = bcm63xx_pci_write
+ };
++
++#ifdef CONFIG_CARDBUS
++/*
++ * emulate configuration read access on a cardbus bridge
++ */
++#define FAKE_CB_BRIDGE_SLOT	0x1e
++
++static int fake_cb_bridge_bus_number = -1;
++
++static struct {
++	u16 pci_command;
++	u8 cb_latency;
++	u8 subordinate_busn;
++	u8 cardbus_busn;
++	u8 pci_busn;
++	int bus_assigned;
++	u16 bridge_control;
++
++	u32 mem_base0;
++	u32 mem_limit0;
++	u32 mem_base1;
++	u32 mem_limit1;
++
++	u32 io_base0;
++	u32 io_limit0;
++	u32 io_base1;
++	u32 io_limit1;
++} fake_cb_bridge_regs;
++
++static int fake_cb_bridge_read(int where, int size, u32 *val)
++{
++	unsigned int reg;
++	u32 data;
++
++	data = 0;
++	reg = where >> 2;
++	switch (reg) {
++	case (PCI_VENDOR_ID >> 2):
++	case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
++		/* create dummy vendor/device id from our cpu id */
++		data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
++		break;
++
++	case (PCI_COMMAND >> 2):
++		data = (PCI_STATUS_DEVSEL_SLOW << 16);
++		data |= fake_cb_bridge_regs.pci_command;
++		break;
++
++	case (PCI_CLASS_REVISION >> 2):
++		data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
++		break;
++
++	case (PCI_CACHE_LINE_SIZE >> 2):
++		data = (PCI_HEADER_TYPE_CARDBUS << 16);
++		break;
++
++	case (PCI_INTERRUPT_LINE >> 2):
++		/* bridge control */
++		data = (fake_cb_bridge_regs.bridge_control << 16);
++		/* pin:intA line:0xff */
++		data |= (0x1 << 8) | 0xff;
++		break;
++
++	case (PCI_CB_PRIMARY_BUS >> 2):
++		data = (fake_cb_bridge_regs.cb_latency << 24);
++		data |= (fake_cb_bridge_regs.subordinate_busn << 16);
++		data |= (fake_cb_bridge_regs.cardbus_busn << 8);
++		data |= fake_cb_bridge_regs.pci_busn;
++		break;
++
++	case (PCI_CB_MEMORY_BASE_0 >> 2):
++		data = fake_cb_bridge_regs.mem_base0;
++		break;
++
++	case (PCI_CB_MEMORY_LIMIT_0 >> 2):
++		data = fake_cb_bridge_regs.mem_limit0;
++		break;
++
++	case (PCI_CB_MEMORY_BASE_1 >> 2):
++		data = fake_cb_bridge_regs.mem_base1;
++		break;
++
++	case (PCI_CB_MEMORY_LIMIT_1 >> 2):
++		data = fake_cb_bridge_regs.mem_limit1;
++		break;
++
++	case (PCI_CB_IO_BASE_0 >> 2):
++		/* | 1 for 32bits io support */
++		data = fake_cb_bridge_regs.io_base0 | 0x1;
++		break;
++
++	case (PCI_CB_IO_LIMIT_0 >> 2):
++		data = fake_cb_bridge_regs.io_limit0;
++		break;
++
++	case (PCI_CB_IO_BASE_1 >> 2):
++		/* | 1 for 32bits io support */
++		data = fake_cb_bridge_regs.io_base1 | 0x1;
++		break;
++
++	case (PCI_CB_IO_LIMIT_1 >> 2):
++		data = fake_cb_bridge_regs.io_limit1;
++		break;
++	}
++
++	*val = postprocess_read(data, where, size);
++	return PCIBIOS_SUCCESSFUL;
++}
++
++/*
++ * emulate configuration write access on a cardbus bridge
++ */
++static int fake_cb_bridge_write(int where, int size, u32 val)
++{
++	unsigned int reg;
++	u32 data, tmp;
++	int ret;
++
++	ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
++	if (ret != PCIBIOS_SUCCESSFUL)
++		return ret;
++
++	data = preprocess_write(data, val, where, size);
++
++	reg = where >> 2;
++	switch (reg) {
++	case (PCI_COMMAND >> 2):
++		fake_cb_bridge_regs.pci_command = (data & 0xffff);
++		break;
++
++	case (PCI_CB_PRIMARY_BUS >> 2):
++		fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
++		fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
++		fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
++		fake_cb_bridge_regs.pci_busn = data & 0xff;
++		if (fake_cb_bridge_regs.cardbus_busn)
++			fake_cb_bridge_regs.bus_assigned = 1;
++		break;
++
++	case (PCI_INTERRUPT_LINE >> 2):
++		tmp = (data >> 16) & 0xffff;
++		/* disable memory prefetch support */
++		tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
++		tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
++		fake_cb_bridge_regs.bridge_control = tmp;
++		break;
++
++	case (PCI_CB_MEMORY_BASE_0 >> 2):
++		fake_cb_bridge_regs.mem_base0 = data;
++		break;
++
++	case (PCI_CB_MEMORY_LIMIT_0 >> 2):
++		fake_cb_bridge_regs.mem_limit0 = data;
++		break;
++
++	case (PCI_CB_MEMORY_BASE_1 >> 2):
++		fake_cb_bridge_regs.mem_base1 = data;
++		break;
++
++	case (PCI_CB_MEMORY_LIMIT_1 >> 2):
++		fake_cb_bridge_regs.mem_limit1 = data;
++		break;
++
++	case (PCI_CB_IO_BASE_0 >> 2):
++		fake_cb_bridge_regs.io_base0 = data;
++		break;
++
++	case (PCI_CB_IO_LIMIT_0 >> 2):
++		fake_cb_bridge_regs.io_limit0 = data;
++		break;
++
++	case (PCI_CB_IO_BASE_1 >> 2):
++		fake_cb_bridge_regs.io_base1 = data;
++		break;
++
++	case (PCI_CB_IO_LIMIT_1 >> 2):
++		fake_cb_bridge_regs.io_limit1 = data;
++		break;
++	}
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
++			   int where, int size, u32 *val)
++{
++	/* snoop access to slot 0x1e on root bus, we fake a cardbus
++	 * bridge at this location */
++	if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
++		fake_cb_bridge_bus_number = bus->number;
++		return fake_cb_bridge_read(where, size, val);
++	}
++
++	/* a  configuration  cycle for  the  device  behind the  cardbus
++	 * bridge is  actually done as a  type 0 cycle  on the primary
++	 * bus. This means that only  one device can be on the cardbus
++	 * bus */
++	if (fake_cb_bridge_regs.bus_assigned &&
++	    bus->number == fake_cb_bridge_regs.cardbus_busn &&
++	    PCI_SLOT(devfn) == 0)
++		return bcm63xx_do_cfg_read(0, 0,
++					   PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
++					   where, size, val);
++
++	return PCIBIOS_DEVICE_NOT_FOUND;
++}
++
++static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
++			    int where, int size, u32 val)
++{
++	if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
++		fake_cb_bridge_bus_number = bus->number;
++		return fake_cb_bridge_write(where, size, val);
++	}
++
++	if (fake_cb_bridge_regs.bus_assigned &&
++	    bus->number == fake_cb_bridge_regs.cardbus_busn &&
++	    PCI_SLOT(devfn) == 0)
++		return bcm63xx_do_cfg_write(0, 0,
++					    PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
++					    where, size, val);
++
++	return PCIBIOS_DEVICE_NOT_FOUND;
++}
++
++struct pci_ops bcm63xx_cb_ops = {
++	.read   = bcm63xx_cb_read,
++	.write   = bcm63xx_cb_write,
++};
++
++/*
++ * only one IO window, so it  cannot be shared by PCI and cardbus, use
++ * fixup to choose and detect unhandled configuration
++ */
++static void bcm63xx_fixup(struct pci_dev *dev)
++{
++	static int io_window = -1;
++	int i, found, new_io_window;
++	u32 val;
++
++	/* look for any io resource */
++	found = 0;
++	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
++		if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
++			found = 1;
++			break;
++		}
++	}
++
++	if (!found)
++		return;
++
++	/* skip our fake bus with only cardbus bridge on it */
++	if (dev->bus->number == fake_cb_bridge_bus_number)
++		return;
++
++	/* find on which bus the device is */
++	if (fake_cb_bridge_regs.bus_assigned &&
++	    dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
++	    PCI_SLOT(dev->devfn) == 0)
++		new_io_window = 1;
++	else
++		new_io_window = 0;
++
++	if (new_io_window == io_window)
++		return;
++
++	if (io_window != -1) {
++		printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
++		       "need IO, which hardware cannot do\n");
++		return;
++	}
++
++	printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
++	       (new_io_window == 0) ? "PCI" : "cardbus");
++
++	val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
++	if (io_window)
++		val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
++	else
++		val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
++	bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
++
++	io_window = new_io_window;
++}
++
++DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
++#endif
+diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
+index 52bac8e..601700d 100644
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -28,7 +28,11 @@ static struct resource bcm_pci_mem_resource = {
+ static struct resource bcm_pci_io_resource = {
+ 	.name   = "bcm63xx PCI IO space",
+ 	.start  = BCM_PCI_IO_BASE_PA,
++#ifdef CONFIG_CARDBUS
++	.end    = BCM_PCI_IO_HALF_PA,
++#else
+ 	.end    = BCM_PCI_IO_END_PA,
++#endif
+ 	.flags  = IORESOURCE_IO
+ };
+ 
+@@ -38,6 +42,33 @@ struct pci_controller bcm63xx_controller = {
+ 	.mem_resource	= &bcm_pci_mem_resource,
+ };
+ 
++/*
++ * We handle cardbus  via a fake Cardbus bridge,  memory and io spaces
++ * have to be  clearly separated from PCI one  since we have different
++ * memory decoder.
++ */
++#ifdef CONFIG_CARDBUS
++static struct resource bcm_cb_mem_resource = {
++	.name   = "bcm63xx Cardbus memory space",
++	.start  = BCM_CB_MEM_BASE_PA,
++	.end    = BCM_CB_MEM_END_PA,
++	.flags  = IORESOURCE_MEM
++};
++
++static struct resource bcm_cb_io_resource = {
++	.name   = "bcm63xx Cardbus IO space",
++	.start  = BCM_PCI_IO_HALF_PA + 1,
++	.end    = BCM_PCI_IO_END_PA,
++	.flags  = IORESOURCE_IO
++};
++
++struct pci_controller bcm63xx_cb_controller = {
++	.pci_ops	= &bcm63xx_cb_ops,
++	.io_resource	= &bcm_cb_io_resource,
++	.mem_resource	= &bcm_cb_mem_resource,
++};
++#endif
++
+ static u32 bcm63xx_int_cfg_readl(u32 reg)
+ {
+ 	u32 tmp;
+@@ -98,8 +129,17 @@ static int __init bcm63xx_pci_init(void)
+ 	val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
+ 	bcm_pcmcia_writel(val, PCMCIA_C1_REG);
+ 
++#ifdef CONFIG_CARDBUS
++	/* setup local bus to PCI access (Cardbus memory) */
++	val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
++	bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
++	bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
++	val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
++	bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
++#else
+ 	/* disable second access windows */
+ 	bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
++#endif
+ 
+ 	/* setup local bus  to PCI access (IO memory),  we have only 1
+ 	 * IO window  for both PCI  and cardbus, but it  cannot handle
+@@ -169,6 +209,10 @@ static int __init bcm63xx_pci_init(void)
+ 
+ 	register_pci_controller(&bcm63xx_controller);
+ 
++#ifdef CONFIG_CARDBUS
++	register_pci_controller(&bcm63xx_cb_controller);
++#endif
++
+ 	/* mark memory space used for IO mapping as reserved */
+ 	request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
+ 			   "bcm63xx PCI IO space");
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/006-pcmcia_cardbus_support.patch b/target/linux/brcm63xx/patches-2.6.27/006-pcmcia_cardbus_support.patch
new file mode 100644
index 0000000..9f067d4
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/006-pcmcia_cardbus_support.patch
@@ -0,0 +1,817 @@
+From b17597be763621ba63534fda6e1ea0a802be2087 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Fri, 18 Jul 2008 21:18:51 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add PCMCIA & Cardbus support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Makefile                         |    1 +
+ arch/mips/bcm63xx/dev-pcmcia.c                     |  135 +++++
+ drivers/pcmcia/Kconfig                             |    4 +
+ drivers/pcmcia/Makefile                            |    1 +
+ drivers/pcmcia/bcm63xx_pcmcia.c                    |  521 ++++++++++++++++++++
+ drivers/pcmcia/bcm63xx_pcmcia.h                    |   65 +++
+ include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h |   13 +
+ 7 files changed, 740 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-pcmcia.c
+ create mode 100644 drivers/pcmcia/bcm63xx_pcmcia.c
+ create mode 100644 drivers/pcmcia/bcm63xx_pcmcia.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h
+
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 8f3299e..456e915 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,3 +1,4 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
+ obj-y		+= dev-uart.o
++obj-y		+= dev-pcmcia.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/dev-pcmcia.c b/arch/mips/bcm63xx/dev-pcmcia.c
+new file mode 100644
+index 0000000..40ec4bc
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-pcmcia.c
+@@ -0,0 +1,135 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <asm/bootinfo.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cs.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_pcmcia.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++static struct resource pcmcia_resources[] = {
++	/* pcmcia registers */
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++
++	/* pcmcia memory zone resources */
++	{
++		.start		= BCM_PCMCIA_COMMON_BASE_PA,
++		.end		= BCM_PCMCIA_COMMON_END_PA,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= BCM_PCMCIA_ATTR_BASE_PA,
++		.end		= BCM_PCMCIA_ATTR_END_PA,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= BCM_PCMCIA_IO_BASE_PA,
++		.end		= BCM_PCMCIA_IO_END_PA,
++		.flags		= IORESOURCE_MEM,
++	},
++
++	/* PCMCIA irq */
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++
++	/* declare PCMCIA IO resource also */
++	{
++		.start		= BCM_PCMCIA_IO_BASE_PA,
++		.end		= BCM_PCMCIA_IO_END_PA,
++		.flags		= IORESOURCE_IO,
++	},
++};
++
++static struct bcm63xx_pcmcia_platform_data pd;
++
++static struct platform_device bcm63xx_pcmcia_device = {
++	.name		= "bcm63xx_pcmcia",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(pcmcia_resources),
++	.resource	= pcmcia_resources,
++	.dev		= {
++		.platform_data = &pd,
++	},
++};
++
++static int __init config_pcmcia_cs(unsigned int cs,
++				   u32 base, unsigned int size)
++{
++	int ret;
++
++	ret = bcm63xx_set_cs_status(cs, 0);
++	if (!ret)
++		ret = bcm63xx_set_cs_base(cs, base, size);
++	if (!ret)
++		ret = bcm63xx_set_cs_status(cs, 1);
++	return ret;
++}
++
++static const __initdata unsigned int pcmcia_cs[3][3] = {
++	/* cs, base address, size */
++	{ MPI_CS_PCMCIA_COMMON, BCM_PCMCIA_COMMON_BASE_PA,
++	  BCM_PCMCIA_COMMON_SIZE },
++
++	{ MPI_CS_PCMCIA_ATTR, BCM_PCMCIA_ATTR_BASE_PA,
++	  BCM_PCMCIA_ATTR_SIZE },
++
++	{ MPI_CS_PCMCIA_IO, BCM_PCMCIA_IO_BASE_PA,
++	  BCM_PCMCIA_IO_SIZE },
++};
++
++int __init bcm63xx_pcmcia_register(void)
++{
++	int ret, i;
++
++	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
++		return 0;
++
++	/* use correct pcmcia ready gpio depending on processor */
++	switch (bcm63xx_get_cpu_id()) {
++	case BCM6348_CPU_ID:
++		pd.ready_gpio = 22;
++		break;
++
++	case BCM6358_CPU_ID:
++		pd.ready_gpio = 22;
++		break;
++
++	default:
++		return -ENODEV;
++	}
++
++	pcmcia_resources[0].start = bcm63xx_regset_address(RSET_PCMCIA);
++	pcmcia_resources[0].end = pcmcia_resources[0].start;
++	pcmcia_resources[0].end += RSET_PCMCIA_SIZE - 1;
++	pcmcia_resources[4].start = bcm63xx_get_irq_number(IRQ_PCMCIA);
++
++	/* configure pcmcia chip selects */
++	for (i = 0; i < 3; i++) {
++		ret = config_pcmcia_cs(pcmcia_cs[i][0],
++				       pcmcia_cs[i][1],
++				       pcmcia_cs[i][2]);
++		if (ret)
++			goto out_err;
++	}
++
++	return platform_device_register(&bcm63xx_pcmcia_device);
++
++out_err:
++	printk(KERN_ERR "unable to set pcmcia chip select");
++	return ret;
++}
+diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
+index e0f8840..5c640ca 100644
+--- a/drivers/pcmcia/Kconfig
++++ b/drivers/pcmcia/Kconfig
+@@ -196,6 +196,10 @@ config PCMCIA_AU1X00
+ 	tristate "Au1x00 pcmcia support"
+ 	depends on SOC_AU1X00 && PCMCIA
+ 
++config PCMCIA_BCM63XX
++	tristate "bcm63xx pcmcia support"
++	depends on BCM63XX && PCMCIA
++
+ config PCMCIA_SA1100
+ 	tristate "SA1100 support"
+ 	depends on ARM && ARCH_SA1100 && PCMCIA
+diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
+index 269a9e9..32b19b5 100644
+--- a/drivers/pcmcia/Makefile
++++ b/drivers/pcmcia/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_PCMCIA_PXA2XX)                     += pxa2xx_core.o pxa2xx_cs.o
+ obj-$(CONFIG_M32R_PCC)				+= m32r_pcc.o
+ obj-$(CONFIG_M32R_CFC)				+= m32r_cfc.o
+ obj-$(CONFIG_PCMCIA_AU1X00)			+= au1x00_ss.o
++obj-$(CONFIG_PCMCIA_BCM63XX)			+= bcm63xx_pcmcia.o
+ obj-$(CONFIG_PCMCIA_VRC4171)			+= vrc4171_card.o
+ obj-$(CONFIG_PCMCIA_VRC4173)			+= vrc4173_cardu.o
+ obj-$(CONFIG_OMAP_CF)				+= omap_cf.o
+diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c
+new file mode 100644
+index 0000000..3a0b7fc
+--- /dev/null
++++ b/drivers/pcmcia/bcm63xx_pcmcia.c
+@@ -0,0 +1,521 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/timer.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/pci.h>
++#include <linux/gpio.h>
++
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include "bcm63xx_pcmcia.h"
++
++#define PFX	"bcm63xx_pcmcia: "
++
++#ifdef CONFIG_CARDBUS
++/* if cardbus is used, platform device needs reference to actual pci
++ * device */
++static struct pci_dev *bcm63xx_cb_dev;
++#endif
++
++/*
++ * read/write helper for pcmcia regs
++ */
++static inline u32 pcmcia_readl(struct bcm63xx_pcmcia_socket *skt, u32 off)
++{
++	return bcm_readl(skt->base + off);
++}
++
++static inline void pcmcia_writel(struct bcm63xx_pcmcia_socket *skt,
++				 u32 val, u32 off)
++{
++	bcm_writel(val, skt->base + off);
++}
++
++/*
++ * (Re-)Initialise the socket, turning on status interrupts and PCMCIA
++ * bus.  This must wait for power to stabilise so that the card status
++ * signals report correctly.
++ */
++static int bcm63xx_pcmcia_sock_init(struct pcmcia_socket *sock)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	skt = sock->driver_data;
++	return 0;
++}
++
++/*
++ * Remove power on the socket, disable IRQs from the card.
++ * Turn off status interrupts, and disable the PCMCIA bus.
++ */
++static int bcm63xx_pcmcia_suspend(struct pcmcia_socket *sock)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	skt = sock->driver_data;
++	return 0;
++}
++
++/*
++ * Implements the set_socket() operation for the in-kernel PCMCIA
++ * service (formerly SS_SetSocket in Card Services). We more or
++ * less punt all of this work and let the kernel handle the details
++ * of power configuration, reset, &c. We also record the value of
++ * `state' in order to regurgitate it to the PCMCIA core later.
++ */
++static int bcm63xx_pcmcia_set_socket(struct pcmcia_socket *sock,
++				     socket_state_t *state)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	unsigned long flags;
++	u32 val;
++
++	skt = sock->driver_data;
++
++	spin_lock_irqsave(&skt->lock, flags);
++
++	/* apply requested socket power */
++	/* FIXME: hardware can't do this */
++
++	/* apply socket reset */
++	val = pcmcia_readl(skt, PCMCIA_C1_REG);
++	if (state->flags & SS_RESET)
++		val |= PCMCIA_C1_RESET_MASK;
++	else
++		val &= ~PCMCIA_C1_RESET_MASK;
++
++	/* reverse reset logic for cardbus card */
++	if (skt->card_detected && (skt->card_type & CARD_CARDBUS))
++		val ^= PCMCIA_C1_RESET_MASK;
++
++	pcmcia_writel(skt, val, PCMCIA_C1_REG);
++
++	/* keep requested state for event reporting */
++	skt->requested_state = *state;
++
++	spin_unlock_irqrestore(&skt->lock, flags);
++
++	return 0;
++}
++
++/*
++ * identity cardtype from VS[12] input, CD[12] input while only VS2 is
++ * floating, and CD[12] input while only VS1 is floating
++ */
++enum {
++	IN_VS1 = (1 << 0),
++	IN_VS2 = (1 << 1),
++	IN_CD1_VS2H = (1 << 2),
++	IN_CD2_VS2H = (1 << 3),
++	IN_CD1_VS1H = (1 << 4),
++	IN_CD2_VS1H = (1 << 5),
++};
++
++static const u8 vscd_to_cardtype[] = {
++
++	/* VS1 float, VS2 float */
++	[IN_VS1 | IN_VS2] = (CARD_PCCARD | CARD_5V),
++
++	/* VS1 grounded, VS2 float */
++	[IN_VS2] = (CARD_PCCARD | CARD_5V | CARD_3V),
++
++	/* VS1 grounded, VS2 grounded */
++	[0] = (CARD_PCCARD | CARD_5V | CARD_3V | CARD_XV),
++
++	/* VS1 tied to CD1, VS2 float */
++	[IN_VS1 | IN_VS2 | IN_CD1_VS1H] = (CARD_CARDBUS | CARD_3V),
++
++	/* VS1 grounded, VS2 tied to CD2 */
++	[IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V | CARD_XV),
++
++	/* VS1 tied to CD2, VS2 grounded */
++	[IN_VS1 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_3V | CARD_XV | CARD_YV),
++
++	/* VS1 float, VS2 grounded */
++	[IN_VS1] = (CARD_PCCARD | CARD_XV),
++
++	/* VS1 float, VS2 tied to CD2 */
++	[IN_VS1 | IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V),
++
++	/* VS1 float, VS2 tied to CD1 */
++	[IN_VS1 | IN_VS2 | IN_CD1_VS2H] = (CARD_CARDBUS | CARD_XV | CARD_YV),
++
++	/* VS1 tied to CD2, VS2 float */
++	[IN_VS1 | IN_VS2 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_YV),
++
++	/* VS2 grounded, VS1 is tied to CD1, CD2 is grounded */
++	[IN_VS1 | IN_CD1_VS1H] = 0, /* ignore cardbay */
++};
++
++/*
++ * poll hardware to check card insertion status
++ */
++static unsigned int __get_socket_status(struct bcm63xx_pcmcia_socket *skt)
++{
++	unsigned int stat;
++	u32 val;
++
++	stat = 0;
++
++	/* check CD for card presence */
++	val = pcmcia_readl(skt, PCMCIA_C1_REG);
++
++	if (!(val & PCMCIA_C1_CD1_MASK) && !(val & PCMCIA_C1_CD2_MASK))
++		stat |= SS_DETECT;
++
++	/* if new insertion, detect cardtype */
++	if ((stat & SS_DETECT) && !skt->card_detected) {
++		unsigned int stat = 0;
++
++		/* float VS1, float VS2 */
++		val |= PCMCIA_C1_VS1OE_MASK;
++		val |= PCMCIA_C1_VS2OE_MASK;
++		pcmcia_writel(skt, val, PCMCIA_C1_REG);
++
++		/* wait for output to stabilize and read VS[12] */
++		udelay(10);
++		val = pcmcia_readl(skt, PCMCIA_C1_REG);
++		stat |= (val & PCMCIA_C1_VS1_MASK) ? IN_VS1 : 0;
++		stat |= (val & PCMCIA_C1_VS2_MASK) ? IN_VS2 : 0;
++
++		/* drive VS1 low, float VS2 */
++		val &= ~PCMCIA_C1_VS1OE_MASK;
++		val |= PCMCIA_C1_VS2OE_MASK;
++		pcmcia_writel(skt, val, PCMCIA_C1_REG);
++
++		/* wait for output to stabilize and read CD[12] */
++		udelay(10);
++		val = pcmcia_readl(skt, PCMCIA_C1_REG);
++		stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS2H : 0;
++		stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS2H : 0;
++
++		/* float VS1, drive VS2 low */
++		val |= PCMCIA_C1_VS1OE_MASK;
++		val &= ~PCMCIA_C1_VS2OE_MASK;
++		pcmcia_writel(skt, val, PCMCIA_C1_REG);
++
++		/* wait for output to stabilize and read CD[12] */
++		udelay(10);
++		val = pcmcia_readl(skt, PCMCIA_C1_REG);
++		stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS1H : 0;
++		stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS1H : 0;
++
++		/* guess cardtype from all this */
++		skt->card_type = vscd_to_cardtype[stat];
++		if (!skt->card_type)
++			printk(KERN_ERR PFX "unsupported card type\n");
++
++		/* drive both VS pin to 0 again */
++		val &= ~(PCMCIA_C1_VS1OE_MASK | PCMCIA_C1_VS2OE_MASK);
++
++		/* enable correct logic */
++		val &= ~(PCMCIA_C1_EN_PCMCIA_MASK | PCMCIA_C1_EN_CARDBUS_MASK);
++		if (skt->card_type & CARD_PCCARD)
++			val |= PCMCIA_C1_EN_PCMCIA_MASK;
++		else
++			val |= PCMCIA_C1_EN_CARDBUS_MASK;
++
++		pcmcia_writel(skt, val, PCMCIA_C1_REG);
++	}
++	skt->card_detected = (stat & SS_DETECT) ? 1 : 0;
++
++	/* report card type/voltage */
++	if (skt->card_type & CARD_CARDBUS)
++		stat |= SS_CARDBUS;
++	if (skt->card_type & CARD_3V)
++		stat |= SS_3VCARD;
++	if (skt->card_type & CARD_XV)
++		stat |= SS_XVCARD;
++	stat |= SS_POWERON;
++
++	if (gpio_get_value(skt->pd->ready_gpio))
++		stat |= SS_READY;
++
++	return stat;
++}
++
++/*
++ * core request to get current socket status
++ */
++static int bcm63xx_pcmcia_get_status(struct pcmcia_socket *sock,
++				     unsigned int *status)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++
++	skt = sock->driver_data;
++
++	spin_lock_bh(&skt->lock);
++	*status = __get_socket_status(skt);
++	spin_unlock_bh(&skt->lock);
++
++	return 0;
++}
++
++/*
++ * socket polling timer callback
++ */
++static void bcm63xx_pcmcia_poll(unsigned long data)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	unsigned int stat, events;
++
++	skt = (struct bcm63xx_pcmcia_socket *)data;
++
++	spin_lock_bh(&skt->lock);
++
++	stat = __get_socket_status(skt);
++
++	/* keep only changed bits, and mask with required one from the
++	 * core */
++	events = (stat ^ skt->old_status) & skt->requested_state.csc_mask;
++	skt->old_status = stat;
++	spin_unlock_bh(&skt->lock);
++
++	if (events)
++		pcmcia_parse_events(&skt->socket, events);
++
++	mod_timer(&skt->timer,
++		  jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE));
++}
++
++static int bcm63xx_pcmcia_set_io_map(struct pcmcia_socket *sock,
++				     struct pccard_io_map *map)
++{
++	/* this doesn't seem to be called by pcmcia layer if static
++	 * mapping is used */
++	return 0;
++}
++
++static int bcm63xx_pcmcia_set_mem_map(struct pcmcia_socket *sock,
++				      struct pccard_mem_map *map)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	struct resource *res;
++
++	skt = sock->driver_data;
++	if (map->flags & MAP_ATTRIB)
++		res = skt->attr_res;
++	else
++		res = skt->common_res;
++
++	map->static_start = res->start + map->card_start;
++	return 0;
++}
++
++static struct pccard_operations bcm63xx_pcmcia_operations = {
++	.init			= bcm63xx_pcmcia_sock_init,
++	.suspend		= bcm63xx_pcmcia_suspend,
++	.get_status		= bcm63xx_pcmcia_get_status,
++	.set_socket		= bcm63xx_pcmcia_set_socket,
++	.set_io_map		= bcm63xx_pcmcia_set_io_map,
++	.set_mem_map		= bcm63xx_pcmcia_set_mem_map,
++};
++
++/*
++ * register pcmcia socket to core
++ */
++static int bcm63xx_drv_pcmcia_probe(struct platform_device *pdev)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	struct pcmcia_socket *sock;
++	struct resource *res, *irq_res;
++	unsigned int regmem_size = 0, iomem_size = 0;
++	u32 val;
++	int ret;
++
++	skt = kzalloc(sizeof(*skt), GFP_KERNEL);
++	if (!skt)
++		return -ENOMEM;
++	spin_lock_init(&skt->lock);
++	sock = &skt->socket;
++	sock->driver_data = skt;
++
++	/* make sure we have all resources we need */
++	skt->common_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	skt->attr_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	skt->pd = pdev->dev.platform_data;
++	if (!skt->common_res || !skt->attr_res || !irq_res || !skt->pd) {
++		ret = -EINVAL;
++		goto err;
++	}
++
++	/* remap pcmcia registers */
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	regmem_size = res->end - res->start + 1;
++	if (!request_mem_region(res->start, regmem_size, "bcm63xx_pcmcia")) {
++		ret = -EINVAL;
++		goto err;
++	}
++	skt->reg_res = res;
++
++	skt->base = ioremap(res->start, regmem_size);
++	if (!skt->base) {
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	/* remap io registers */
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
++	iomem_size = res->end - res->start + 1;
++	skt->io_base = ioremap(res->start, iomem_size);
++	if (!skt->io_base) {
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	/* resources are static */
++	sock->resource_ops = &pccard_static_ops;
++	sock->ops = &bcm63xx_pcmcia_operations;
++	sock->owner = THIS_MODULE;
++	sock->dev.parent = &pdev->dev;
++	sock->features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
++	sock->io_offset = (unsigned long)skt->io_base;
++	sock->pci_irq = irq_res->start;
++
++#ifdef CONFIG_CARDBUS
++	sock->cb_dev = bcm63xx_cb_dev;
++	if (bcm63xx_cb_dev)
++		sock->features |= SS_CAP_CARDBUS;
++#endif
++
++	/* assume common & attribute memory have the same size */
++	sock->map_size = skt->common_res->end - skt->common_res->start + 1;
++
++	/* initialize polling timer */
++	setup_timer(&skt->timer, bcm63xx_pcmcia_poll, (unsigned long)skt);
++
++	/* initialize  pcmcia  control register,  drive  VS[12] to  0,
++	 * leave CB IDSEL to the old  value since it is set by the PCI
++	 * layer */
++	val = pcmcia_readl(skt, PCMCIA_C1_REG);
++	val &= PCMCIA_C1_CBIDSEL_MASK;
++	val |= PCMCIA_C1_EN_PCMCIA_GPIO_MASK;
++	pcmcia_writel(skt, val, PCMCIA_C1_REG);
++
++	/* FIXME set correct pcmcia timings */
++	val = PCMCIA_C2_DATA16_MASK;
++	val |= 10 << PCMCIA_C2_RWCOUNT_SHIFT;
++	val |= 6 << PCMCIA_C2_INACTIVE_SHIFT;
++	val |= 3 << PCMCIA_C2_SETUP_SHIFT;
++	val |= 3 << PCMCIA_C2_HOLD_SHIFT;
++	pcmcia_writel(skt, val, PCMCIA_C2_REG);
++
++	ret = pcmcia_register_socket(sock);
++	if (ret)
++		goto err;
++
++	/* start polling socket */
++	mod_timer(&skt->timer,
++		  jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE));
++
++	platform_set_drvdata(pdev, skt);
++	return 0;
++
++err:
++	if (skt->io_base)
++		iounmap(skt->io_base);
++	if (skt->base)
++		iounmap(skt->base);
++	if (skt->reg_res)
++		release_mem_region(skt->reg_res->start, regmem_size);
++	kfree(skt);
++	return ret;
++}
++
++static int bcm63xx_drv_pcmcia_remove(struct platform_device *pdev)
++{
++	struct bcm63xx_pcmcia_socket *skt;
++	struct resource *res;
++
++	skt = platform_get_drvdata(pdev);
++	del_timer_sync(&skt->timer);
++	iounmap(skt->base);
++	iounmap(skt->io_base);
++	res = skt->reg_res;
++	release_mem_region(res->start, res->end - res->start + 1);
++	kfree(skt);
++	return 0;
++}
++
++struct platform_driver bcm63xx_pcmcia_driver = {
++	.probe	= bcm63xx_drv_pcmcia_probe,
++	.remove	= __devexit_p(bcm63xx_drv_pcmcia_remove),
++	.driver	= {
++		.name	= "bcm63xx_pcmcia",
++		.owner  = THIS_MODULE,
++	},
++};
++
++#ifdef CONFIG_CARDBUS
++static int __devinit bcm63xx_cb_probe(struct pci_dev *dev,
++				      const struct pci_device_id *id)
++{
++	/* keep pci device */
++	bcm63xx_cb_dev = dev;
++	return platform_driver_register(&bcm63xx_pcmcia_driver);
++}
++
++static void __devexit bcm63xx_cb_exit(struct pci_dev *dev)
++{
++	platform_driver_unregister(&bcm63xx_pcmcia_driver);
++	bcm63xx_cb_dev = NULL;
++}
++
++static struct pci_device_id bcm63xx_cb_table[] = {
++	{
++		.vendor		= PCI_VENDOR_ID_BROADCOM,
++		.device		= PCI_ANY_ID,
++		.subvendor	= PCI_VENDOR_ID_BROADCOM,
++		.subdevice	= PCI_ANY_ID,
++		.class		= PCI_CLASS_BRIDGE_CARDBUS << 8,
++		.class_mask	= ~0,
++	},
++};
++
++MODULE_DEVICE_TABLE(pci, bcm63xx_cb_table);
++
++static struct pci_driver bcm63xx_cardbus_driver = {
++	.name		= "yenta_cardbus",
++	.id_table	= bcm63xx_cb_table,
++	.probe		= bcm63xx_cb_probe,
++	.remove		= __devexit_p(bcm63xx_cb_exit),
++};
++#endif
++
++/*
++ * if cardbus support is enabled, register our platform device after
++ * our fake cardbus bridge has been registered
++ */
++static int __init bcm63xx_pcmcia_init(void)
++{
++#ifdef CONFIG_CARDBUS
++	return pci_register_driver(&bcm63xx_cardbus_driver);
++#else
++	return platform_driver_register(&bcm63xx_pcmcia_driver);
++#endif
++}
++
++static void __exit bcm63xx_pcmcia_exit(void)
++{
++#ifdef CONFIG_CARDBUS
++	return pci_unregister_driver(&bcm63xx_cardbus_driver);
++#else
++	platform_driver_unregister(&bcm63xx_pcmcia_driver);
++#endif
++}
++
++module_init(bcm63xx_pcmcia_init);
++module_exit(bcm63xx_pcmcia_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
++MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm63xx Socket Controller");
+diff --git a/drivers/pcmcia/bcm63xx_pcmcia.h b/drivers/pcmcia/bcm63xx_pcmcia.h
+new file mode 100644
+index 0000000..85de866
+--- /dev/null
++++ b/drivers/pcmcia/bcm63xx_pcmcia.h
+@@ -0,0 +1,65 @@
++#ifndef BCM63XX_PCMCIA_H_
++#define BCM63XX_PCMCIA_H_
++
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <pcmcia/ss.h>
++#include <bcm63xx_dev_pcmcia.h>
++
++/* socket polling rate in ms */
++#define BCM63XX_PCMCIA_POLL_RATE	500
++
++enum {
++	CARD_CARDBUS = (1 << 0),
++
++	CARD_PCCARD = (1 << 1),
++
++	CARD_5V = (1 << 2),
++
++	CARD_3V = (1 << 3),
++
++	CARD_XV = (1 << 4),
++
++	CARD_YV = (1 << 5),
++};
++
++struct bcm63xx_pcmcia_socket {
++	struct pcmcia_socket socket;
++
++	/* platform specific data */
++	struct bcm63xx_pcmcia_platform_data *pd;
++
++	/* all regs access are protected by this spinlock */
++	spinlock_t lock;
++
++	/* pcmcia registers resource */
++	struct resource *reg_res;
++
++	/* base remapped address of registers */
++	void __iomem *base;
++
++	/* whether a card is detected at the moment */
++	int card_detected;
++
++	/* type of detected card (mask of above enum) */
++	u8 card_type;
++
++	/* keep last socket status to implement event reporting */
++	unsigned int old_status;
++
++	/* backup of requested socket state */
++	socket_state_t requested_state;
++
++	/* timer used for socket status polling */
++	struct timer_list timer;
++
++	/* attribute/common memory resources */
++	struct resource *attr_res;
++	struct resource *common_res;
++	struct resource *io_res;
++
++	/* base address of io memory */
++	void __iomem *io_base;
++};
++
++#endif /* BCM63XX_PCMCIA_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h
+new file mode 100644
+index 0000000..2beb396
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pcmcia.h
+@@ -0,0 +1,13 @@
++#ifndef BCM63XX_DEV_PCMCIA_H_
++#define BCM63XX_DEV_PCMCIA_H_
++
++/*
++ * PCMCIA driver platform data
++ */
++struct bcm63xx_pcmcia_platform_data {
++	unsigned int ready_gpio;
++};
++
++int bcm63xx_pcmcia_register(void);
++
++#endif /* BCM63XX_DEV_PCMCIA_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/007-usb_ohci_support.patch b/target/linux/brcm63xx/patches-2.6.27/007-usb_ohci_support.patch
new file mode 100644
index 0000000..1b7a053
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/007-usb_ohci_support.patch
@@ -0,0 +1,325 @@
+From f7416412febd7efc1d33c7506c81265719368667 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Mon, 21 Jul 2008 14:58:19 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add USB OHCI support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Kconfig                          |    6 +
+ arch/mips/bcm63xx/Makefile                         |    1 +
+ arch/mips/bcm63xx/dev-usb-ohci.c                   |   50 ++++++
+ drivers/usb/host/ohci-bcm63xx.c                    |  159 ++++++++++++++++++++
+ drivers/usb/host/ohci-hcd.c                        |    5 +
+ drivers/usb/host/ohci.h                            |    7 +-
+ .../asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h   |    6 +
+ 7 files changed, 233 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c
+ create mode 100644 drivers/usb/host/ohci-bcm63xx.c
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+
+diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
+index 7ca370a..f2ddb87 100644
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -4,8 +4,14 @@ menu "CPU support"
+ config BCM63XX_CPU_6348
+ 	bool "support 6348 CPU"
+ 	select HW_HAS_PCI
++	select USB_ARCH_HAS_OHCI
++	select USB_OHCI_BIG_ENDIAN_DESC
++	select USB_OHCI_BIG_ENDIAN_MMIO
+ 
+ config BCM63XX_CPU_6358
+ 	bool "support 6358 CPU"
+ 	select HW_HAS_PCI
++	select USB_ARCH_HAS_OHCI
++	select USB_OHCI_BIG_ENDIAN_DESC
++	select USB_OHCI_BIG_ENDIAN_MMIO
+ endmenu
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 456e915..75f0d54 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,4 +1,5 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
+ obj-y		+= dev-uart.o
+ obj-y		+= dev-pcmcia.o
++obj-y		+= dev-usb-ohci.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/dev-usb-ohci.c b/arch/mips/bcm63xx/dev-usb-ohci.c
+new file mode 100644
+index 0000000..377e67c
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ohci.c
+@@ -0,0 +1,50 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_usb_ohci.h>
++
++static struct resource ohci_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static u64 ohci_dmamask = ~(u32)0;
++
++static struct platform_device bcm63xx_ohci_device = {
++	.name		= "bcm63xx_ohci",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(ohci_resources),
++	.resource	= ohci_resources,
++	.dev		= {
++		.dma_mask		= &ohci_dmamask,
++		.coherent_dma_mask	= 0xffffffff,
++	},
++};
++
++int __init bcm63xx_ohci_register(void)
++{
++	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
++		return 0;
++
++	ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);
++	ohci_resources[0].end = ohci_resources[0].start;
++	ohci_resources[0].end += RSET_OHCI_SIZE - 1;
++	ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0);
++	return platform_device_register(&bcm63xx_ohci_device);
++}
+diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c
+new file mode 100644
+index 0000000..08807d9
+--- /dev/null
++++ b/drivers/usb/host/ohci-bcm63xx.c
+@@ -0,0 +1,159 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++
++static struct clk *usb_host_clock;
++
++static int __devinit ohci_bcm63xx_start(struct usb_hcd *hcd)
++{
++	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
++	int ret;
++
++	ret = ohci_init(ohci);
++	if (ret < 0)
++		return ret;
++
++	/* FIXME: autodetected port 2 is shared with USB slave */
++
++	ret = ohci_run(ohci);
++	if (ret < 0) {
++		err("can't start %s", hcd->self.bus_name);
++		ohci_stop(hcd);
++		return ret;
++	}
++	return 0;
++}
++
++static const struct hc_driver ohci_bcm63xx_hc_driver = {
++	.description =		hcd_name,
++	.product_desc =		"BCM63XX integrated OHCI controller",
++	.hcd_priv_size =	sizeof(struct ohci_hcd),
++
++	.irq =			ohci_irq,
++	.flags =		HCD_USB11 | HCD_MEMORY,
++	.start =		ohci_bcm63xx_start,
++	.stop =			ohci_stop,
++	.shutdown =		ohci_shutdown,
++	.urb_enqueue =		ohci_urb_enqueue,
++	.urb_dequeue =		ohci_urb_dequeue,
++	.endpoint_disable =	ohci_endpoint_disable,
++	.get_frame_number =	ohci_get_frame,
++	.hub_status_data =	ohci_hub_status_data,
++	.hub_control =		ohci_hub_control,
++	.start_port_reset =	ohci_start_port_reset,
++};
++
++static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev)
++{
++	struct resource *res_mem, *res_irq;
++	struct usb_hcd *hcd;
++	struct ohci_hcd *ohci;
++	u32 reg;
++	int ret;
++
++	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	if (!res_mem || !res_irq)
++		return -ENODEV;
++
++	if (BCMCPU_IS_6348()) {
++		struct clk *clk;
++		/* enable USB host clock */
++		clk = clk_get(&pdev->dev, "usbh");
++		if (IS_ERR(clk))
++			return -ENODEV;
++
++		clk_enable(clk);
++		usb_host_clock = clk;
++		bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG);
++
++	} else if (BCMCPU_IS_6358()) {
++		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG);
++		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG);
++		/* don't ask... */
++		bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG);
++	} else
++		return 0;
++
++	hcd = usb_create_hcd(&ohci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx");
++	if (!hcd)
++		return -ENOMEM;
++	hcd->rsrc_start = res_mem->start;
++	hcd->rsrc_len = res_mem->end - res_mem->start + 1;
++
++	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
++		pr_debug("request_mem_region failed\n");
++		ret = -EBUSY;
++		goto out;
++	}
++
++	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
++	if (!hcd->regs) {
++		pr_debug("ioremap failed\n");
++		ret = -EIO;
++		goto out1;
++	}
++
++	ohci = hcd_to_ohci(hcd);
++	ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC |
++		OHCI_QUIRK_FRAME_NO;
++	ohci_hcd_init(ohci);
++
++	ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED);
++	if (ret)
++		goto out2;
++
++	platform_set_drvdata(pdev, hcd);
++	return 0;
++
++out2:
++	iounmap(hcd->regs);
++out1:
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++out:
++	usb_put_hcd(hcd);
++	return ret;
++}
++
++static int __devexit ohci_hcd_bcm63xx_drv_remove(struct platform_device *pdev)
++{
++	struct usb_hcd *hcd;
++
++	hcd = platform_get_drvdata(pdev);
++	usb_remove_hcd(hcd);
++	iounmap(hcd->regs);
++	usb_put_hcd(hcd);
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++	if (usb_host_clock) {
++		clk_disable(usb_host_clock);
++		clk_put(usb_host_clock);
++	}
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static struct platform_driver ohci_hcd_bcm63xx_driver = {
++	.probe		= ohci_hcd_bcm63xx_drv_probe,
++	.remove		= __devexit_p(ohci_hcd_bcm63xx_drv_remove),
++	.shutdown	= usb_hcd_platform_shutdown,
++	.driver		= {
++		.name	= "bcm63xx_ohci",
++		.owner	= THIS_MODULE,
++		.bus	= &platform_bus_type
++	},
++};
++
++MODULE_ALIAS("platform:bcm63xx_ohci");
+diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
+index 8990196..7e360ef 100644
+--- a/drivers/usb/host/ohci-hcd.c
++++ b/drivers/usb/host/ohci-hcd.c
+@@ -1050,6 +1050,11 @@ MODULE_LICENSE ("GPL");
+ #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+ #endif
+ 
++#ifdef CONFIG_BCM63XX
++#include "ohci-bcm63xx.c"
++#define PLATFORM_DRIVER		ohci_hcd_bcm63xx_driver
++#endif
++
+ #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+     defined(CONFIG_CPU_SUBTYPE_SH7763)
+diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
+index faf622e..947e240 100644
+--- a/drivers/usb/host/ohci.h
++++ b/drivers/usb/host/ohci.h
+@@ -549,6 +549,11 @@ static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
+ #define writel_be(val, addr)	out_be32((__force unsigned *)addr, val)
+ #endif
+ 
++#if defined(CONFIG_MIPS) && defined(CONFIG_BCM63XX)
++#define readl_be(addr)		__raw_readl((__force unsigned *)addr)
++#define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
++#endif
++
+ static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
+ 					__hc32 __iomem * regs)
+ {
+@@ -654,7 +659,7 @@ static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
+  * some big-endian SOC implementations.  Same thing happens with PSW access.
+  */
+ 
+-#ifdef CONFIG_PPC_MPC52xx
++#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_BCM63XX)
+ #define big_endian_frame_no_quirk(ohci)	(ohci->flags & OHCI_QUIRK_FRAME_NO)
+ #else
+ #define big_endian_frame_no_quirk(ohci)	0
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+new file mode 100644
+index 0000000..518a04d
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_OHCI_H_
++#define BCM63XX_DEV_USB_OHCI_H_
++
++int bcm63xx_ohci_register(void);
++
++#endif /* BCM63XX_DEV_USB_OHCI_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/008-usb_ehci_support.patch b/target/linux/brcm63xx/patches-2.6.27/008-usb_ehci_support.patch
new file mode 100644
index 0000000..5486d98
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/008-usb_ehci_support.patch
@@ -0,0 +1,301 @@
+From 2940d1996c86c4c4dd7a82214f846d0c0b707165 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Mon, 21 Jul 2008 18:24:42 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add USB EHCI support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Kconfig                          |    2 +
+ arch/mips/bcm63xx/Makefile                         |    1 +
+ arch/mips/bcm63xx/dev-usb-ehci.c                   |   50 +++++++
+ drivers/usb/host/ehci-bcm63xx.c                    |  152 ++++++++++++++++++++
+ drivers/usb/host/ehci-hcd.c                        |    5 +
+ drivers/usb/host/ehci.h                            |    5 +
+ .../asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h   |    6 +
+ 7 files changed, 221 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c
+ create mode 100644 drivers/usb/host/ehci-bcm63xx.c
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+
+diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
+index f2ddb87..be120f7 100644
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -14,4 +14,6 @@ config BCM63XX_CPU_6358
+ 	select USB_ARCH_HAS_OHCI
+ 	select USB_OHCI_BIG_ENDIAN_DESC
+ 	select USB_OHCI_BIG_ENDIAN_MMIO
++	select USB_ARCH_HAS_EHCI
++	select USB_EHCI_BIG_ENDIAN_MMIO
+ endmenu
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 75f0d54..99e335d 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -2,4 +2,5 @@ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
+ obj-y		+= dev-uart.o
+ obj-y		+= dev-pcmcia.o
+ obj-y		+= dev-usb-ohci.o
++obj-y		+= dev-usb-ehci.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/dev-usb-ehci.c b/arch/mips/bcm63xx/dev-usb-ehci.c
+new file mode 100644
+index 0000000..7885405
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -0,0 +1,50 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_usb_ehci.h>
++
++static struct resource ehci_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static u64 ehci_dmamask = ~(u32)0;
++
++static struct platform_device bcm63xx_ehci_device = {
++	.name		= "bcm63xx_ehci",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(ehci_resources),
++	.resource	= ehci_resources,
++	.dev		= {
++		.dma_mask		= &ehci_dmamask,
++		.coherent_dma_mask	= 0xffffffff,
++	},
++};
++
++int __init bcm63xx_ehci_register(void)
++{
++	if (!BCMCPU_IS_6358())
++		return 0;
++
++	ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
++	ehci_resources[0].end = ehci_resources[0].start;
++	ehci_resources[0].end += RSET_EHCI_SIZE - 1;
++	ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0);
++	return platform_device_register(&bcm63xx_ehci_device);
++}
+diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c
+new file mode 100644
+index 0000000..2fef571
+--- /dev/null
++++ b/drivers/usb/host/ehci-bcm63xx.c
+@@ -0,0 +1,152 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++
++static int ehci_bcm63xx_setup(struct usb_hcd *hcd)
++{
++	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++	int retval;
++
++	retval = ehci_halt(ehci);
++	if (retval)
++		return retval;
++
++	retval = ehci_init(hcd);
++	if (retval)
++		return retval;
++
++	hcd->has_tt = 1;
++	ehci_reset(ehci);
++	ehci_port_power(ehci, 0);
++
++	return retval;
++}
++
++
++static const struct hc_driver ehci_bcm63xx_hc_driver = {
++	.description =		hcd_name,
++	.product_desc =		"BCM63XX integrated EHCI controller",
++	.hcd_priv_size =	sizeof(struct ehci_hcd),
++
++	.irq =			ehci_irq,
++	.flags =		HCD_MEMORY | HCD_USB2,
++
++	.reset =		ehci_bcm63xx_setup,
++	.start =		ehci_run,
++	.stop =			ehci_stop,
++	.shutdown =		ehci_shutdown,
++
++	.urb_enqueue =		ehci_urb_enqueue,
++	.urb_dequeue =		ehci_urb_dequeue,
++	.endpoint_disable =	ehci_endpoint_disable,
++
++	.get_frame_number =	ehci_get_frame,
++
++	.hub_status_data =	ehci_hub_status_data,
++	.hub_control =		ehci_hub_control,
++	.bus_suspend =		ehci_bus_suspend,
++	.bus_resume =		ehci_bus_resume,
++	.relinquish_port =	ehci_relinquish_port,
++	.port_handed_over =	ehci_port_handed_over,
++};
++
++static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev)
++{
++	struct resource *res_mem, *res_irq;
++	struct usb_hcd *hcd;
++	struct ehci_hcd *ehci;
++	u32 reg;
++	int ret;
++
++	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	if (!res_mem || !res_irq)
++		return -ENODEV;
++
++	reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG);
++	reg &= ~USBH_PRIV_SWAP_EHCI_DATA_MASK;
++	reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++	bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG);
++
++	/* don't ask... */
++	bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG);
++
++	hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx");
++	if (!hcd)
++		return -ENOMEM;
++	hcd->rsrc_start = res_mem->start;
++	hcd->rsrc_len = res_mem->end - res_mem->start + 1;
++
++	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
++		pr_debug("request_mem_region failed\n");
++		ret = -EBUSY;
++		goto out;
++	}
++
++	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
++	if (!hcd->regs) {
++		pr_debug("ioremap failed\n");
++		ret = -EIO;
++		goto out1;
++	}
++
++	ehci = hcd_to_ehci(hcd);
++	ehci->big_endian_mmio = 1;
++	ehci->big_endian_desc = 0;
++	ehci->caps = hcd->regs;
++	ehci->regs = hcd->regs +
++		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
++	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
++	ehci->sbrn = 0x20;
++
++	ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED);
++	if (ret)
++		goto out2;
++
++	platform_set_drvdata(pdev, hcd);
++	return 0;
++
++out2:
++	iounmap(hcd->regs);
++out1:
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++out:
++	usb_put_hcd(hcd);
++	return ret;
++}
++
++static int __devexit ehci_hcd_bcm63xx_drv_remove(struct platform_device *pdev)
++{
++	struct usb_hcd *hcd;
++
++	hcd = platform_get_drvdata(pdev);
++	usb_remove_hcd(hcd);
++	iounmap(hcd->regs);
++	usb_put_hcd(hcd);
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static struct platform_driver ehci_hcd_bcm63xx_driver = {
++	.probe		= ehci_hcd_bcm63xx_drv_probe,
++	.remove		= __devexit_p(ehci_hcd_bcm63xx_drv_remove),
++	.shutdown	= usb_hcd_platform_shutdown,
++	.driver		= {
++		.name	= "bcm63xx_ehci",
++		.owner	= THIS_MODULE,
++		.bus	= &platform_bus_type
++	},
++};
++
++MODULE_ALIAS("platform:bcm63xx_ehci");
+diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
+index 8409e07..3230ba3 100644
+--- a/drivers/usb/host/ehci-hcd.c
++++ b/drivers/usb/host/ehci-hcd.c
+@@ -1040,6 +1040,11 @@ MODULE_LICENSE ("GPL");
+ #define	PLATFORM_DRIVER		ixp4xx_ehci_driver
+ #endif
+ 
++#ifdef CONFIG_BCM63XX
++#include "ehci-bcm63xx.c"
++#define	PLATFORM_DRIVER		ehci_hcd_bcm63xx_driver
++#endif
++
+ #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
+     !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
+ #error "missing bus glue for ehci-hcd"
+diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
+index 5799298..71d0eca 100644
+--- a/drivers/usb/host/ehci.h
++++ b/drivers/usb/host/ehci.h
+@@ -755,6 +755,11 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
+ #define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
+ #endif
+ 
++#if defined(CONFIG_MIPS) && defined(CONFIG_BCM63XX)
++#define readl_be(addr)		__raw_readl((__force unsigned *)addr)
++#define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
++#endif
++
+ static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
+ 		__u32 __iomem * regs)
+ {
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+new file mode 100644
+index 0000000..17fb519
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_EHCI_H_
++#define BCM63XX_DEV_USB_EHCI_H_
++
++int bcm63xx_ehci_register(void);
++
++#endif /* BCM63XX_DEV_USB_EHCI_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/009-add_integrated_ethernet_mac_support.patch b/target/linux/brcm63xx/patches-2.6.27/009-add_integrated_ethernet_mac_support.patch
new file mode 100644
index 0000000..9caf692
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/009-add_integrated_ethernet_mac_support.patch
@@ -0,0 +1,2480 @@
+From 49aa7ffcd9bd2d9a0af99fced7b8511160dbf345 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Sun, 21 Sep 2008 03:43:26 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add integrated ethernet mac support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Makefile                       |    1 +
+ arch/mips/bcm63xx/dev-enet.c                     |  158 ++
+ drivers/net/Kconfig                              |    9 +
+ drivers/net/Makefile                             |    1 +
+ drivers/net/bcm63xx_enet.c                       | 1894 ++++++++++++++++++++++
+ drivers/net/bcm63xx_enet.h                       |  294 ++++
+ include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h |   45 +
+ 7 files changed, 2402 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-enet.c
+ create mode 100644 drivers/net/bcm63xx_enet.c
+ create mode 100644 drivers/net/bcm63xx_enet.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h
+
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 99e335d..5358093 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -3,4 +3,5 @@ obj-y		+= dev-uart.o
+ obj-y		+= dev-pcmcia.o
+ obj-y		+= dev-usb-ohci.o
+ obj-y		+= dev-usb-ehci.o
++obj-y		+= dev-enet.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c
+new file mode 100644
+index 0000000..c6e472e
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -0,0 +1,158 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_dev_enet.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++static struct resource shared_res[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++};
++
++static struct platform_device bcm63xx_enet_shared_device = {
++	.name		= "bcm63xx_enet_shared",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(shared_res),
++	.resource	= shared_res,
++};
++
++static int shared_device_registered = 0;
++
++static struct resource enet0_res[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.start		= IRQ_ENET0_RXDMA,
++		.flags		= IORESOURCE_IRQ,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.start		= IRQ_ENET0_TXDMA,
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static struct bcm63xx_enet_platform_data enet0_pd;
++
++static struct platform_device bcm63xx_enet0_device = {
++	.name		= "bcm63xx_enet",
++	.id		= 0,
++	.num_resources	= ARRAY_SIZE(enet0_res),
++	.resource	= enet0_res,
++	.dev		= {
++		.platform_data = &enet0_pd,
++	},
++};
++
++static struct resource enet1_res[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++	{
++		.start		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_IRQ,
++	},
++};
++
++static struct bcm63xx_enet_platform_data enet1_pd;
++
++static struct platform_device bcm63xx_enet1_device = {
++	.name		= "bcm63xx_enet",
++	.id		= 1,
++	.num_resources	= ARRAY_SIZE(enet1_res),
++	.resource	= enet1_res,
++	.dev		= {
++		.platform_data = &enet1_pd,
++	},
++};
++
++int __init bcm63xx_enet_register(int unit,
++				 const struct bcm63xx_enet_platform_data *pd)
++{
++	struct platform_device *pdev;
++	struct bcm63xx_enet_platform_data *dpd;
++	int ret;
++
++	if (unit > 1)
++		return -ENODEV;
++
++	if (!shared_device_registered) {
++		shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
++		shared_res[0].end = shared_res[0].start;
++		shared_res[0].end += RSET_ENETDMA_SIZE - 1;
++
++		ret = platform_device_register(&bcm63xx_enet_shared_device);
++		if (ret)
++			return ret;
++		shared_device_registered = 1;
++	}
++
++	if (unit == 0) {
++		enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
++		enet0_res[0].end = enet0_res[0].start;
++		enet0_res[0].end += RSET_ENET_SIZE - 1;
++		enet0_res[1].start = bcm63xx_get_irq_number(IRQ_ENET0);
++		enet0_res[2].start = bcm63xx_get_irq_number(IRQ_ENET0_RXDMA);
++		enet0_res[3].start = bcm63xx_get_irq_number(IRQ_ENET0_TXDMA);
++		pdev = &bcm63xx_enet0_device;
++	} else {
++		enet1_res[0].start = bcm63xx_regset_address(RSET_ENET1);
++		enet1_res[0].end = enet1_res[0].start;
++		enet1_res[0].end += RSET_ENET_SIZE - 1;
++		enet1_res[1].start = bcm63xx_get_irq_number(IRQ_ENET1);
++		enet1_res[2].start = bcm63xx_get_irq_number(IRQ_ENET1_RXDMA);
++		enet1_res[3].start = bcm63xx_get_irq_number(IRQ_ENET1_TXDMA);
++		pdev = &bcm63xx_enet1_device;
++	}
++
++	/* copy given platform data */
++	dpd = pdev->dev.platform_data;
++	memcpy(dpd, pd, sizeof (*pd));
++
++	/* adjust them in case internal phy is used */
++	if (dpd->use_internal_phy) {
++
++		/* internal phy only exists for enet0 */
++		if (unit == 1)
++			return -ENODEV;
++
++		dpd->phy_id = 1;
++		dpd->has_phy_interrupt = 1;
++		dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
++	}
++
++	ret = platform_device_register(pdev);
++	if (ret)
++		return ret;
++	return 0;
++}
+diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
+index bbd0e67..01f7e5a 100644
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -1840,6 +1840,15 @@ config NE_H8300
+ 	  Say Y here if you want to use the NE2000 compatible
+ 	  controller on the Renesas H8/300 processor.
+ 
++config BCM63XX_ENET
++	tristate "Broadcom 63xx internal mac support"
++	depends on BCM63XX
++	select MII
++	select PHYLIB
++	help
++	  This driver supports the ethernet MACs in the Broadcom 63xx
++	  MIPS chipset family (BCM63XX).
++
+ source "drivers/net/fs_enet/Kconfig"
+ 
+ endif # NET_ETHERNET
+diff --git a/drivers/net/Makefile b/drivers/net/Makefile
+index 284ed83..ab22f32 100644
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -123,6 +123,7 @@ obj-$(CONFIG_SB1250_MAC) += sb1250-mac.o
+ obj-$(CONFIG_B44) += b44.o
+ obj-$(CONFIG_FORCEDETH) += forcedeth.o
+ obj-$(CONFIG_NE_H8300) += ne-h8300.o
++obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
+ obj-$(CONFIG_AX88796) += ax88796.o
+ 
+ obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
+diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c
+new file mode 100644
+index 0000000..40c2565
+--- /dev/null
++++ b/drivers/net/bcm63xx_enet.c
+@@ -0,0 +1,1894 @@
++/*
++ * Driver for BCM963xx builtin Ethernet mac
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/ethtool.h>
++#include <linux/crc32.h>
++#include <linux/err.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++
++#include <bcm63xx_dev_enet.h>
++#include "bcm63xx_enet.h"
++
++static char bcm_enet_driver_name[] = "bcm63xx_enet";
++static char bcm_enet_driver_version[] = "1.0";
++
++static int copybreak __read_mostly = 128;
++module_param(copybreak, int, 0);
++MODULE_PARM_DESC(copybreak, "Receive copy threshold");
++
++/* io memory shared between all devices */
++static void __iomem *bcm_enet_shared_base;
++
++/*
++ * io helpers to access mac registers
++ */
++static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
++{
++	return bcm_readl(priv->base + off);
++}
++
++static inline void enet_writel(struct bcm_enet_priv *priv,
++			       u32 val, u32 off)
++{
++	bcm_writel(val, priv->base + off);
++}
++
++/*
++ * io helpers to access shared registers
++ */
++static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
++{
++	return bcm_readl(bcm_enet_shared_base + off);
++}
++
++static inline void enet_dma_writel(struct bcm_enet_priv *priv,
++				       u32 val, u32 off)
++{
++	bcm_writel(val, bcm_enet_shared_base + off);
++}
++
++/*
++ * write given data into mii register and wait for transfer to end
++ * with timeout (average measured transfer time is 25us)
++ */
++static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
++{
++	int limit;
++
++	/* make sure mii interrupt status is cleared */
++	enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
++
++	enet_writel(priv, data, ENET_MIIDATA_REG);
++	wmb();
++
++	/* busy wait on mii interrupt bit, with timeout */
++	limit = 1000;
++	do {
++		if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
++			break;
++		udelay(1);
++	} while (limit-- >= 0);
++
++	return (limit < 0) ? 1 : 0;
++}
++
++/*
++ * MII internal read callback
++ */
++static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
++			      int regnum)
++{
++	u32 tmp, val;
++
++	tmp = regnum << ENET_MIIDATA_REG_SHIFT;
++	tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
++	tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
++	tmp |= ENET_MIIDATA_OP_READ_MASK;
++
++	if (do_mdio_op(priv, tmp))
++		return -1;
++
++	val = enet_readl(priv, ENET_MIIDATA_REG);
++	val &= 0xffff;
++	return val;
++}
++
++/*
++ * MII internal write callback
++ */
++static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
++			       int regnum, u16 value)
++{
++	u32 tmp;
++
++	tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
++	tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
++	tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
++	tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
++	tmp |= ENET_MIIDATA_OP_WRITE_MASK;
++
++	(void)do_mdio_op(priv, tmp);
++	return 0;
++}
++
++/*
++ * MII read callback from phylib
++ */
++static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
++				     int regnum)
++{
++	return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
++}
++
++/*
++ * MII write callback from phylib
++ */
++static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
++				      int regnum, u16 value)
++{
++	return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
++}
++
++/*
++ * MII read callback from mii core
++ */
++static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
++				  int regnum)
++{
++	return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
++}
++
++/*
++ * MII write callback from mii core
++ */
++static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
++				    int regnum, int value)
++{
++	bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
++}
++
++/*
++ * refill rx queue
++ */
++static int bcm_enet_refill_rx(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++
++	while (priv->rx_desc_count < priv->rx_ring_size) {
++		struct bcm_enet_desc *desc;
++		struct sk_buff *skb;
++		dma_addr_t p;
++		int desc_idx;
++		u32 len_stat;
++
++		desc_idx = priv->rx_dirty_desc;
++		desc = &priv->rx_desc_cpu[desc_idx];
++
++		if (!priv->rx_skb[desc_idx]) {
++			skb = netdev_alloc_skb(dev, BCMENET_MAX_RX_SIZE);
++			if (!skb)
++				break;
++			priv->rx_skb[desc_idx] = skb;
++
++			p = dma_map_single(&priv->pdev->dev, skb->data,
++					   BCMENET_MAX_RX_SIZE,
++					   DMA_FROM_DEVICE);
++			desc->address = p;
++		}
++
++		len_stat = BCMENET_MAX_RX_SIZE << DMADESC_LENGTH_SHIFT;
++		len_stat |= DMADESC_OWNER_MASK;
++		if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
++			len_stat |= DMADESC_WRAP_MASK;
++			priv->rx_dirty_desc = 0;
++		} else {
++			priv->rx_dirty_desc++;
++		}
++		wmb();
++		desc->len_stat = len_stat;
++
++		priv->rx_desc_count++;
++
++		/* tell dma engine we allocated one buffer */
++		enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
++	}
++
++	/* If rx ring is still empty, set a timer to try allocating
++	 * again at a later time. */
++	if (priv->rx_desc_count == 0 && netif_running(dev)) {
++		dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
++		priv->rx_timeout.expires = jiffies + HZ;
++		add_timer(&priv->rx_timeout);
++	}
++
++	return 0;
++}
++
++/*
++ * timer callback to defer refill rx queue in case we're OOM
++ */
++static void bcm_enet_refill_rx_timer(unsigned long data)
++{
++	struct net_device *dev;
++	struct bcm_enet_priv *priv;
++
++	dev = (struct net_device *)data;
++	priv = netdev_priv(dev);
++
++	spin_lock(&priv->rx_lock);
++	bcm_enet_refill_rx((struct net_device *)data);
++	spin_unlock(&priv->rx_lock);
++}
++
++/*
++ * extract packet from rx queue
++ */
++static int bcm_enet_receive_queue(struct net_device *dev, int budget)
++{
++	struct bcm_enet_priv *priv;
++	struct device *kdev;
++	int processed;
++
++	priv = netdev_priv(dev);
++	kdev = &priv->pdev->dev;
++	processed = 0;
++
++	/* don't scan ring further than number of refilled
++	 * descriptor */
++	if (budget > priv->rx_desc_count)
++		budget = priv->rx_desc_count;
++
++	do {
++		struct bcm_enet_desc *desc;
++		struct sk_buff *skb;
++		int desc_idx;
++		u32 len_stat;
++		unsigned int len;
++
++		desc_idx = priv->rx_curr_desc;
++		desc = &priv->rx_desc_cpu[desc_idx];
++
++		/* make sure we actually read the descriptor status at
++		 * each loop */
++		rmb();
++
++		len_stat = desc->len_stat;
++
++		/* break if dma ownership belongs to hw */
++		if (len_stat & DMADESC_OWNER_MASK)
++			break;
++
++		processed++;
++		priv->rx_curr_desc++;
++		if (priv->rx_curr_desc == priv->rx_ring_size)
++			priv->rx_curr_desc = 0;
++		priv->rx_desc_count--;
++
++		/* if the packet does not have start of packet _and_
++		 * end of packet flag set, then just recycle it */
++		if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
++			priv->stats.rx_dropped++;
++			continue;
++		}
++
++		/* recycle packet if it's marked as bad */
++		if (unlikely(len_stat & DMADESC_ERR_MASK)) {
++			priv->stats.rx_errors++;
++
++			if (len_stat & DMADESC_OVSIZE_MASK)
++				priv->stats.rx_length_errors++;
++			if (len_stat & DMADESC_CRC_MASK)
++				priv->stats.rx_crc_errors++;
++			if (len_stat & DMADESC_UNDER_MASK)
++				priv->stats.rx_frame_errors++;
++			if (len_stat & DMADESC_OV_MASK)
++				priv->stats.rx_fifo_errors++;
++			continue;
++		}
++
++		/* valid packet */
++		skb = priv->rx_skb[desc_idx];
++		len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
++		/* don't include FCS */
++		len -= 4;
++
++		if (len < copybreak) {
++			struct sk_buff *nskb;
++
++			nskb = netdev_alloc_skb(dev, len + 2);
++			if (!nskb) {
++				/* forget packet, just rearm desc */
++				priv->stats.rx_dropped++;
++				continue;
++			}
++
++			/* since we're copying the data, we can align
++			 * them properly */
++			skb_reserve(nskb, NET_IP_ALIGN);
++			dma_sync_single_for_cpu(kdev, desc->address,
++						len, DMA_FROM_DEVICE);
++			memcpy(nskb->data, skb->data, len);
++			dma_sync_single_for_device(kdev, desc->address,
++						   len, DMA_FROM_DEVICE);
++			skb = nskb;
++		} else {
++			dma_unmap_single(&priv->pdev->dev, desc->address,
++					 BCMENET_MAX_RX_SIZE, DMA_FROM_DEVICE);
++			priv->rx_skb[desc_idx] = NULL;
++		}
++
++		skb_put(skb, len);
++		skb->dev = dev;
++		skb->protocol = eth_type_trans(skb, dev);
++		priv->stats.rx_packets++;
++		priv->stats.rx_bytes += len;
++		dev->last_rx = jiffies;
++		netif_receive_skb(skb);
++
++	} while (--budget > 0);
++
++	if (processed || !priv->rx_desc_count) {
++		bcm_enet_refill_rx(dev);
++
++		/* kick rx dma */
++		enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
++				ENETDMA_CHANCFG_REG(priv->rx_chan));
++	}
++
++	return processed;
++}
++
++
++/*
++ * try to or force reclaim of transmitted buffers
++ */
++static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
++{
++	struct bcm_enet_priv *priv;
++	int released;
++
++	priv = netdev_priv(dev);
++	released = 0;
++
++	while (priv->tx_desc_count < priv->tx_ring_size) {
++		struct bcm_enet_desc *desc;
++		struct sk_buff *skb;
++
++		/* We run in a bh and fight against start_xmit, which
++		 * is called with bh disabled  */
++		spin_lock(&priv->tx_lock);
++
++		desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
++
++		if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
++			spin_unlock(&priv->tx_lock);
++			break;
++		}
++
++		/* ensure other field of the descriptor were not read
++		 * before we checked ownership */
++		rmb();
++
++		skb = priv->tx_skb[priv->tx_dirty_desc];
++		priv->tx_skb[priv->tx_dirty_desc] = NULL;
++		dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
++				 DMA_TO_DEVICE);
++
++		priv->tx_dirty_desc++;
++		if (priv->tx_dirty_desc == priv->tx_ring_size)
++			priv->tx_dirty_desc = 0;
++		priv->tx_desc_count++;
++
++		spin_unlock(&priv->tx_lock);
++
++		if (desc->len_stat & DMADESC_UNDER_MASK)
++			priv->stats.tx_errors++;
++
++		dev_kfree_skb(skb);
++		released++;
++	}
++
++	if (netif_queue_stopped(dev) && released)
++		netif_wake_queue(dev);
++
++	return released;
++}
++
++/*
++ * poll func, called by network core
++ */
++static int bcm_enet_poll(struct napi_struct *napi, int budget)
++{
++	struct bcm_enet_priv *priv;
++	struct net_device *dev;
++	int tx_work_done, rx_work_done;
++
++	priv = container_of(napi, struct bcm_enet_priv, napi);
++	dev = priv->net_dev;
++
++	/* ack interrupts */
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IR_REG(priv->rx_chan));
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IR_REG(priv->tx_chan));
++
++	/* reclaim sent skb */
++	tx_work_done = bcm_enet_tx_reclaim(dev, 0);
++
++	spin_lock(&priv->rx_lock);
++	rx_work_done = bcm_enet_receive_queue(dev, budget);
++	spin_unlock(&priv->rx_lock);
++
++	if (rx_work_done >= budget || tx_work_done > 0) {
++		/* rx/tx queue is not yet empty/clean */
++		return rx_work_done;
++	}
++
++	/* no more packet in rx/tx queue, remove device from poll
++	 * queue */
++	__netif_rx_complete(dev, napi);
++
++	/* restore rx/tx interrupt */
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IRMASK_REG(priv->rx_chan));
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IRMASK_REG(priv->tx_chan));
++
++	return rx_work_done;
++}
++
++/*
++ * mac interrupt handler
++ */
++static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
++{
++	struct net_device *dev;
++	struct bcm_enet_priv *priv;
++	u32 stat;
++
++	dev = dev_id;
++	priv = netdev_priv(dev);
++
++	stat = enet_readl(priv, ENET_IR_REG);
++	if (!(stat & ENET_IR_MIB))
++		return IRQ_NONE;
++
++	/* clear & mask interrupt */
++	enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
++	enet_writel(priv, 0, ENET_IRMASK_REG);
++
++	/* read mib registers in workqueue */
++	schedule_work(&priv->mib_update_task);
++
++	return IRQ_HANDLED;
++}
++
++/*
++ * rx/tx dma interrupt handler
++ */
++static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
++{
++	struct net_device *dev;
++	struct bcm_enet_priv *priv;
++
++	dev = dev_id;
++	priv = netdev_priv(dev);
++
++	/* mask rx/tx interrupts */
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++
++	netif_rx_schedule(dev, &priv->napi);
++
++	return IRQ_HANDLED;
++}
++
++/*
++ * tx request callback
++ */
++static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++	struct bcm_enet_desc *desc;
++	u32 len_stat;
++	int ret;
++
++	priv = netdev_priv(dev);
++
++	/* lock against tx reclaim */
++	spin_lock(&priv->tx_lock);
++
++	/* make sure  the tx hw queue  is not full,  should not happen
++	 * since we stop queue before it's the case */
++	if (unlikely(!priv->tx_desc_count)) {
++		netif_stop_queue(dev);
++		dev_err(&priv->pdev->dev, "xmit called with no tx desc "
++			"available?\n");
++		ret = NETDEV_TX_BUSY;
++		goto out_unlock;
++	}
++
++	/* point to the next available desc */
++	desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
++	priv->tx_skb[priv->tx_curr_desc] = skb;
++
++	/* fill descriptor */
++	desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
++				       DMA_TO_DEVICE);
++
++	len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
++	len_stat |= DMADESC_ESOP_MASK |
++		DMADESC_APPEND_CRC |
++		DMADESC_OWNER_MASK;
++
++	priv->tx_curr_desc++;
++	if (priv->tx_curr_desc == priv->tx_ring_size) {
++		priv->tx_curr_desc = 0;
++		len_stat |= DMADESC_WRAP_MASK;
++	}
++	priv->tx_desc_count--;
++
++	/* dma might be already polling, make sure we update desc
++	 * fields in correct order */
++	wmb();
++	desc->len_stat = len_stat;
++	wmb();
++
++	/* kick tx dma */
++	enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
++			ENETDMA_CHANCFG_REG(priv->tx_chan));
++
++	/* stop queue if no more desc available */
++	if (!priv->tx_desc_count)
++		netif_stop_queue(dev);
++
++	priv->stats.tx_bytes += skb->len;
++	priv->stats.tx_packets++;
++	dev->trans_start = jiffies;
++	ret = NETDEV_TX_OK;
++
++out_unlock:
++	spin_unlock(&priv->tx_lock);
++	return ret;
++}
++
++/*
++ * Change the interface's mac address.
++ */
++static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
++{
++	struct bcm_enet_priv *priv;
++	struct sockaddr *addr = p;
++	u32 val;
++
++	priv = netdev_priv(dev);
++	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
++
++	/* use perfect match register 0 to store my mac address */
++	val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
++		(dev->dev_addr[4] << 8) | dev->dev_addr[5];
++	enet_writel(priv, val, ENET_PML_REG(0));
++
++	val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
++	val |= ENET_PMH_DATAVALID_MASK;
++	enet_writel(priv, val, ENET_PMH_REG(0));
++
++	return 0;
++}
++
++/*
++ * Change rx mode (promiscous/allmulti) and update multicast list
++ */
++static void bcm_enet_set_multicast_list(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++	struct dev_mc_list *mc_list;
++	u32 val;
++	int i;
++
++	priv = netdev_priv(dev);
++
++	val = enet_readl(priv, ENET_RXCFG_REG);
++
++	if (dev->flags & IFF_PROMISC)
++		val |= ENET_RXCFG_PROMISC_MASK;
++	else
++		val &= ~ENET_RXCFG_PROMISC_MASK;
++
++	/* only 3 perfect match registers left, first one is used for
++	 * own mac address */
++	if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 3)
++		val |= ENET_RXCFG_ALLMCAST_MASK;
++	else
++		val &= ~ENET_RXCFG_ALLMCAST_MASK;
++
++	/* no need to set perfect match registers if we catch all
++	 * multicast */
++	if (val & ENET_RXCFG_ALLMCAST_MASK) {
++		enet_writel(priv, val, ENET_RXCFG_REG);
++		return;
++	}
++
++	for (i = 0, mc_list = dev->mc_list;
++	     (mc_list != NULL) && (i < dev->mc_count) && (i < 3);
++	     i++, mc_list = mc_list->next) {
++		u8 *dmi_addr;
++		u32 tmp;
++
++		/* filter non ethernet address */
++		if (mc_list->dmi_addrlen != 6)
++			continue;
++
++		/* update perfect match registers */
++		dmi_addr = mc_list->dmi_addr;
++		tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
++			(dmi_addr[4] << 8) | dmi_addr[5];
++		enet_writel(priv, tmp, ENET_PML_REG(i + 1));
++
++		tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
++		tmp |= ENET_PMH_DATAVALID_MASK;
++		enet_writel(priv, tmp, ENET_PMH_REG(i + 1));
++	}
++
++	for (; i < 3; i++) {
++		enet_writel(priv, 0, ENET_PML_REG(i + 1));
++		enet_writel(priv, 0, ENET_PMH_REG(i + 1));
++	}
++
++	enet_writel(priv, val, ENET_RXCFG_REG);
++}
++
++/*
++ * set mac duplex parameters
++ */
++static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
++{
++	u32 val;
++
++	val = enet_readl(priv, ENET_TXCTL_REG);
++	if (fullduplex)
++		val |= ENET_TXCTL_FD_MASK;
++	else
++		val &= ~ENET_TXCTL_FD_MASK;
++	enet_writel(priv, val, ENET_TXCTL_REG);
++}
++
++/*
++ * set mac flow control parameters
++ */
++static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
++{
++	u32 val;
++
++	/* rx flow control (pause frame handling) */
++	val = enet_readl(priv, ENET_RXCFG_REG);
++	if (rx_en)
++		val |= ENET_RXCFG_ENFLOW_MASK;
++	else
++		val &= ~ENET_RXCFG_ENFLOW_MASK;
++	enet_writel(priv, val, ENET_RXCFG_REG);
++
++	/* tx flow control (pause frame generation) */
++	val = enet_dma_readl(priv, ENETDMA_CFG_REG);
++	if (tx_en)
++		val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
++	else
++		val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
++	enet_dma_writel(priv, val, ENETDMA_CFG_REG);
++}
++
++/*
++ * link changed callback (from phylib)
++ */
++static void bcm_enet_adjust_phy_link(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++	struct phy_device *phydev;
++	int status_changed;
++
++	priv = netdev_priv(dev);
++	phydev = priv->phydev;
++	status_changed = 0;
++
++	if (priv->old_link != phydev->link) {
++		status_changed = 1;
++		priv->old_link = phydev->link;
++	}
++
++	/* reflect duplex change in mac configuration */
++	if (phydev->link && phydev->duplex != priv->old_duplex) {
++		bcm_enet_set_duplex(priv,
++				    (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
++		status_changed = 1;
++		priv->old_duplex = phydev->duplex;
++	}
++
++	/* enable flow control if remote advertise it (trust phylib to
++	 * check that duplex is full */
++	if (phydev->link && phydev->pause != priv->old_pause) {
++		int rx_pause_en, tx_pause_en;
++
++		if (phydev->pause) {
++			/* pause was advertised by lpa and us */
++			rx_pause_en = 1;
++			tx_pause_en = 1;
++		} else if (!priv->pause_auto) {
++			/* pause setting overrided by user */
++			rx_pause_en = priv->pause_rx;
++			tx_pause_en = priv->pause_tx;
++		} else {
++			rx_pause_en = 0;
++			tx_pause_en = 0;
++		}
++
++		bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
++		status_changed = 1;
++		priv->old_pause = phydev->pause;
++	}
++
++	if (status_changed) {
++		pr_info("%s: link %s", dev->name, phydev->link ?
++			"UP" : "DOWN");
++		if (phydev->link)
++			printk(" - %d/%s - flow control %s", phydev->speed,
++			       DUPLEX_FULL == phydev->duplex ? "full" : "half",
++			       phydev->pause == 1 ? "rx&tx" : "off");
++
++		printk("\n");
++	}
++}
++
++/*
++ * link changed callback (if phylib is not used)
++ */
++static void bcm_enet_adjust_link(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++	bcm_enet_set_duplex(priv, priv->force_duplex_full);
++	bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
++
++	pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
++		dev->name,
++		priv->force_speed_100 ? 100 : 10,
++		priv->force_duplex_full ? "full" : "half",
++		priv->pause_rx ? "rx" : "off",
++		priv->pause_tx ? "tx" : "off");
++}
++
++/*
++ * open callback, allocate dma rings & buffers and start rx operation
++ */
++static int bcm_enet_open(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++	struct sockaddr addr;
++	struct device *kdev;
++	struct phy_device *phydev;
++	int irq_requested, i, ret;
++	unsigned int size;
++	char phy_id[BUS_ID_SIZE];
++	void *p;
++	u32 val;
++
++	priv = netdev_priv(dev);
++	priv->rx_desc_cpu = priv->tx_desc_cpu = NULL;
++	priv->rx_skb = priv->tx_skb = NULL;
++
++	kdev = &priv->pdev->dev;
++
++	if (priv->has_phy) {
++		/* connect to PHY */
++		snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT,
++			 priv->mac_id ? "1" : "0", priv->phy_id);
++
++		phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0,
++				     PHY_INTERFACE_MODE_MII);
++
++		if (IS_ERR(phydev)) {
++			dev_err(kdev, "could not attach to PHY\n");
++			return PTR_ERR(phydev);
++		}
++
++		/* mask with MAC supported features */
++		phydev->supported &= (SUPPORTED_10baseT_Half |
++				      SUPPORTED_10baseT_Full |
++				      SUPPORTED_100baseT_Half |
++				      SUPPORTED_100baseT_Full |
++				      SUPPORTED_Autoneg |
++				      SUPPORTED_Pause |
++				      SUPPORTED_MII);
++		phydev->advertising = phydev->supported;
++
++		if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
++			phydev->advertising |= SUPPORTED_Pause;
++		else
++			phydev->advertising &= ~SUPPORTED_Pause;
++
++		dev_info(kdev, "attached PHY at address %d [%s]\n",
++			 phydev->addr, phydev->drv->name);
++
++		priv->old_link = 0;
++		priv->old_duplex = -1;
++		priv->old_pause = -1;
++		priv->phydev = phydev;
++	}
++
++	/* mask all interrupts and request them */
++	enet_writel(priv, 0, ENET_IRMASK_REG);
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++
++	irq_requested = 0;
++	ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
++	if (ret)
++		goto out;
++	irq_requested++;
++
++	ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
++			  IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev);
++	if (ret)
++		goto out;
++	irq_requested++;
++
++	ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
++			  IRQF_DISABLED, dev->name, dev);
++	if (ret)
++		goto out;
++	irq_requested++;
++
++	/* initialize perfect match registers */
++	for (i = 0; i < 4; i++) {
++		enet_writel(priv, 0, ENET_PML_REG(i));
++		enet_writel(priv, 0, ENET_PMH_REG(i));
++	}
++
++	/* write device mac address */
++	memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
++	bcm_enet_set_mac_address(dev, &addr);
++
++	/* allocate rx dma ring */
++	size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
++	p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
++	if (!p) {
++		dev_err(kdev, "cannot allocate rx ring %u\n", size);
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	memset(p, 0, size);
++	priv->rx_desc_alloc_size = size;
++	priv->rx_desc_cpu = p;
++
++	/* allocate tx dma ring */
++	size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
++	p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
++	if (!p) {
++		dev_err(kdev, "cannot allocate tx ring\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	memset(p, 0, size);
++	priv->tx_desc_alloc_size = size;
++	priv->tx_desc_cpu = p;
++
++	priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
++			       GFP_KERNEL);
++	if (!priv->tx_skb) {
++		dev_err(kdev, "cannot allocate rx skb queue\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	priv->tx_desc_count = priv->tx_ring_size;
++	priv->tx_dirty_desc = 0;
++	priv->tx_curr_desc = 0;
++	spin_lock_init(&priv->tx_lock);
++
++	/* init & fill rx ring with skbs */
++	priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
++			       GFP_KERNEL);
++	if (!priv->rx_skb) {
++		dev_err(kdev, "cannot allocate rx skb queue\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	priv->rx_desc_count = 0;
++	priv->rx_dirty_desc = 0;
++	priv->rx_curr_desc = 0;
++
++	/* initialize flow control buffer allocation */
++	enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
++			ENETDMA_BUFALLOC_REG(priv->rx_chan));
++
++	if (bcm_enet_refill_rx(dev)) {
++		dev_err(kdev, "cannot allocate rx skb queue\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	/* write rx & tx ring addresses */
++	enet_dma_writel(priv, priv->rx_desc_dma,
++			ENETDMA_RSTART_REG(priv->rx_chan));
++	enet_dma_writel(priv, priv->tx_desc_dma,
++			ENETDMA_RSTART_REG(priv->tx_chan));
++
++	/* clear remaining state ram for rx & tx channel */
++	enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
++
++	/* set max rx/tx length */
++	enet_writel(priv, BCMENET_MAX_RX_SIZE, ENET_RXMAXLEN_REG);
++	enet_writel(priv, BCMENET_MAX_TX_SIZE, ENET_TXMAXLEN_REG);
++
++	/* set dma maximum burst len */
++	enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
++			ENETDMA_MAXBURST_REG(priv->rx_chan));
++	enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
++			ENETDMA_MAXBURST_REG(priv->tx_chan));
++
++	/* set correct transmit fifo watermark */
++	enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
++
++	/* set flow control low/high threshold to 1/3 / 2/3 */
++	val = priv->rx_ring_size / 3;
++	enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
++	val = (priv->rx_ring_size * 2) / 3;
++	enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
++
++	/* all set, enable mac and interrupts, start dma engine and
++	 * kick rx dma channel */
++	wmb();
++	enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG);
++	enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
++	enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
++			ENETDMA_CHANCFG_REG(priv->rx_chan));
++
++	/* watch "mib counters about to overflow" interrupt */
++	enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
++	enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
++
++	/* watch "packet transferred" interrupt in rx and tx */
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IR_REG(priv->rx_chan));
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IR_REG(priv->tx_chan));
++
++	/* make sure we enable napi before rx interrupt  */
++	napi_enable(&priv->napi);
++
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IRMASK_REG(priv->rx_chan));
++	enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
++			ENETDMA_IRMASK_REG(priv->tx_chan));
++
++	if (priv->has_phy)
++		phy_start(priv->phydev);
++	else
++		bcm_enet_adjust_link(dev);
++
++	netif_start_queue(dev);
++	return 0;
++
++out:
++	phy_disconnect(priv->phydev);
++	if (irq_requested > 2)
++		free_irq(priv->irq_tx, dev);
++	if (irq_requested > 1)
++		free_irq(priv->irq_rx, dev);
++	if (irq_requested > 0)
++		free_irq(dev->irq, dev);
++	for (i = 0; i < priv->rx_ring_size; i++) {
++		struct bcm_enet_desc *desc;
++
++		if (!priv->rx_skb[i])
++			continue;
++
++		desc = &priv->rx_desc_cpu[i];
++		dma_unmap_single(kdev, desc->address, BCMENET_MAX_RX_SIZE,
++				 DMA_FROM_DEVICE);
++		kfree_skb(priv->rx_skb[i]);
++	}
++	if (priv->rx_desc_cpu)
++		dma_free_coherent(kdev, priv->rx_desc_alloc_size,
++				  priv->rx_desc_cpu, priv->rx_desc_dma);
++	if (priv->tx_desc_cpu)
++		dma_free_coherent(kdev, priv->tx_desc_alloc_size,
++				  priv->tx_desc_cpu, priv->tx_desc_dma);
++	kfree(priv->rx_skb);
++	kfree(priv->tx_skb);
++	return ret;
++}
++
++/*
++ * disable mac
++ */
++static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
++{
++	int limit;
++	u32 val;
++
++	val = enet_readl(priv, ENET_CTL_REG);
++	val |= ENET_CTL_DISABLE_MASK;
++	enet_writel(priv, val, ENET_CTL_REG);
++
++	limit = 1000;
++	do {
++		u32 val;
++
++		val = enet_readl(priv, ENET_CTL_REG);
++		if (!(val & ENET_CTL_DISABLE_MASK))
++			break;
++		udelay(1);
++	} while (limit--);
++}
++
++/*
++ * disable dma in given channel
++ */
++static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
++{
++	int limit;
++
++	enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
++
++	limit = 1000;
++	do {
++		u32 val;
++
++		val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
++		if (!(val & ENETDMA_CHANCFG_EN_MASK))
++			break;
++		udelay(1);
++	} while (limit--);
++}
++
++/*
++ * stop callback
++ */
++static int bcm_enet_stop(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++	struct device *kdev;
++	int i;
++
++	priv = netdev_priv(dev);
++	kdev = &priv->pdev->dev;
++
++	netif_stop_queue(dev);
++	napi_disable(&priv->napi);
++	if (priv->has_phy)
++		phy_stop(priv->phydev);
++	del_timer_sync(&priv->rx_timeout);
++
++	/* mask all interrupts */
++	enet_writel(priv, 0, ENET_IRMASK_REG);
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
++	enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++
++	/* make sure no mib update is scheduled */
++	flush_scheduled_work();
++
++	/* disable dma & mac */
++	bcm_enet_disable_dma(priv, priv->tx_chan);
++	bcm_enet_disable_dma(priv, priv->rx_chan);
++	bcm_enet_disable_mac(priv);
++
++	/* force reclaim of all tx buffers */
++	bcm_enet_tx_reclaim(dev, 1);
++
++	/* free the rx skb ring */
++	for (i = 0; i < priv->rx_ring_size; i++) {
++		struct bcm_enet_desc *desc;
++
++		if (!priv->rx_skb[i])
++			continue;
++
++		desc = &priv->rx_desc_cpu[i];
++		dma_unmap_single(kdev, desc->address, BCMENET_MAX_RX_SIZE,
++				 DMA_FROM_DEVICE);
++		kfree_skb(priv->rx_skb[i]);
++	}
++
++	/* free remaining allocated memory */
++	kfree(priv->rx_skb);
++	kfree(priv->tx_skb);
++	dma_free_coherent(kdev, priv->rx_desc_alloc_size,
++			  priv->rx_desc_cpu, priv->rx_desc_dma);
++	dma_free_coherent(kdev, priv->tx_desc_alloc_size,
++			  priv->tx_desc_cpu, priv->tx_desc_dma);
++	free_irq(priv->irq_tx, dev);
++	free_irq(priv->irq_rx, dev);
++	free_irq(dev->irq, dev);
++
++	/* release phy */
++	if (priv->has_phy) {
++		phy_disconnect(priv->phydev);
++		priv->phydev = NULL;
++	}
++
++	return 0;
++}
++
++/*
++ * core request to return device rx/tx stats
++ */
++static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++	return &priv->stats;
++}
++
++/*
++ * ethtool callbacks
++ */
++struct bcm_enet_stats {
++	char stat_string[ETH_GSTRING_LEN];
++	int sizeof_stat;
++	int stat_offset;
++	int mib_reg;
++};
++
++#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),		\
++		     offsetof(struct bcm_enet_priv, m)
++
++static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
++	{ "rx_packets", GEN_STAT(stats.rx_packets), -1 },
++	{ "tx_packets",	GEN_STAT(stats.tx_packets), -1 },
++	{ "rx_bytes", GEN_STAT(stats.rx_bytes), -1 },
++	{ "tx_bytes", GEN_STAT(stats.tx_bytes), -1 },
++	{ "rx_errors", GEN_STAT(stats.rx_errors), -1 },
++	{ "tx_errors", GEN_STAT(stats.tx_errors), -1 },
++	{ "rx_dropped",	GEN_STAT(stats.rx_dropped), -1 },
++	{ "tx_dropped",	GEN_STAT(stats.tx_dropped), -1 },
++
++	{ "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
++	{ "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
++	{ "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
++	{ "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
++	{ "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
++	{ "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
++	{ "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
++	{ "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
++	{ "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
++	{ "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
++	{ "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
++	{ "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
++	{ "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
++	{ "rx_dropped",	GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
++	{ "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
++	{ "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
++	{ "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
++	{ "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
++	{ "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
++	{ "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
++	{ "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
++
++	{ "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
++	{ "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
++	{ "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
++	{ "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
++	{ "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
++	{ "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
++	{ "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
++	{ "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
++	{ "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
++	{ "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
++	{ "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
++	{ "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
++	{ "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
++	{ "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
++	{ "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
++	{ "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
++	{ "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
++	{ "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
++	{ "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
++	{ "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
++	{ "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
++	{ "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
++
++};
++
++#define BCM_ENET_STATS_LEN	\
++	(sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
++
++static const u32 unused_mib_regs[] = {
++	ETH_MIB_TX_ALL_OCTETS,
++	ETH_MIB_TX_ALL_PKTS,
++	ETH_MIB_RX_ALL_OCTETS,
++	ETH_MIB_RX_ALL_PKTS,
++};
++
++
++static void bcm_enet_get_drvinfo(struct net_device *netdev,
++				 struct ethtool_drvinfo *drvinfo)
++{
++	strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
++	strncpy(drvinfo->version, bcm_enet_driver_version, 32);
++	strncpy(drvinfo->fw_version, "N/A", 32);
++	strncpy(drvinfo->bus_info, "bcm63xx", 32);
++	drvinfo->n_stats = BCM_ENET_STATS_LEN;
++}
++
++static int bcm_enet_get_stats_count(struct net_device *netdev)
++{
++	return BCM_ENET_STATS_LEN;
++}
++
++static void bcm_enet_get_strings(struct net_device *netdev,
++				 u32 stringset, u8 *data)
++{
++	int i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
++			memcpy(data + i * ETH_GSTRING_LEN,
++			       bcm_enet_gstrings_stats[i].stat_string,
++			       ETH_GSTRING_LEN);
++		}
++		break;
++	}
++}
++
++static void update_mib_counters(struct bcm_enet_priv *priv)
++{
++	int i;
++
++	for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
++		const struct bcm_enet_stats *s;
++		u32 val;
++		char *p;
++
++		s = &bcm_enet_gstrings_stats[i];
++		if (s->mib_reg == -1)
++			continue;
++
++		val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
++		p = (char *)priv + s->stat_offset;
++
++		if (s->sizeof_stat == sizeof(u64))
++			*(u64 *)p += val;
++		else
++			*(u32 *)p += val;
++	}
++
++	/* also empty unused mib counters to make sure mib counter
++	 * overflow interrupt is cleared */
++	for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
++		(void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
++}
++
++static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = container_of(t, struct bcm_enet_priv, mib_update_task);
++	mutex_lock(&priv->mib_update_lock);
++	update_mib_counters(priv);
++	mutex_unlock(&priv->mib_update_lock);
++
++	/* reenable mib interrupt */
++	if (netif_running(priv->net_dev))
++		enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
++}
++
++static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
++				       struct ethtool_stats *stats,
++				       u64 *data)
++{
++	struct bcm_enet_priv *priv;
++	int i;
++
++	priv = netdev_priv(netdev);
++
++	mutex_lock(&priv->mib_update_lock);
++	update_mib_counters(priv);
++
++	for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
++		const struct bcm_enet_stats *s;
++		char *p;
++
++		s = &bcm_enet_gstrings_stats[i];
++		p = (char *)priv + s->stat_offset;
++		data[i] = (s->sizeof_stat == sizeof(u64)) ?
++			*(u64 *)p : *(u32 *)p;
++	}
++	mutex_unlock(&priv->mib_update_lock);
++}
++
++static int bcm_enet_get_settings(struct net_device *dev,
++				 struct ethtool_cmd *cmd)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++
++	cmd->maxrxpkt = 0;
++	cmd->maxtxpkt = 0;
++
++	if (priv->has_phy) {
++		if (!priv->phydev)
++			return -ENODEV;
++		return phy_ethtool_gset(priv->phydev, cmd);
++	} else {
++		cmd->autoneg = 0;
++		cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10;
++		cmd->duplex = (priv->force_duplex_full) ?
++			DUPLEX_FULL : DUPLEX_HALF;
++		cmd->supported = ADVERTISED_10baseT_Half  |
++			ADVERTISED_10baseT_Full |
++			ADVERTISED_100baseT_Half |
++			ADVERTISED_100baseT_Full;
++		cmd->advertising = 0;
++		cmd->port = PORT_MII;
++		cmd->transceiver = XCVR_EXTERNAL;
++	}
++	return 0;
++}
++
++static int bcm_enet_set_settings(struct net_device *dev,
++				 struct ethtool_cmd *cmd)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++	if (priv->has_phy) {
++		if (!priv->phydev)
++			return -ENODEV;
++		return phy_ethtool_sset(priv->phydev, cmd);
++	} else {
++
++		if (cmd->autoneg ||
++		    (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
++		    cmd->port != PORT_MII)
++			return -EINVAL;
++
++		priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
++		priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
++
++		if (netif_running(dev))
++			bcm_enet_adjust_link(dev);
++		return 0;
++	}
++}
++
++static void bcm_enet_get_ringparam(struct net_device *dev,
++				   struct ethtool_ringparam *ering)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++
++	/* rx/tx ring is actually only limited by memory */
++	ering->rx_max_pending = 8192;
++	ering->tx_max_pending = 8192;
++	ering->rx_mini_max_pending = 0;
++	ering->rx_jumbo_max_pending = 0;
++	ering->rx_pending = priv->rx_ring_size;
++	ering->tx_pending = priv->tx_ring_size;
++}
++
++static int bcm_enet_set_ringparam(struct net_device *dev,
++				  struct ethtool_ringparam *ering)
++{
++	struct bcm_enet_priv *priv;
++	int was_running;
++
++	priv = netdev_priv(dev);
++
++	was_running = 0;
++	if (netif_running(dev)) {
++		bcm_enet_stop(dev);
++		was_running = 1;
++	}
++
++	priv->rx_ring_size = ering->rx_pending;
++	priv->tx_ring_size = ering->tx_pending;
++
++	if (was_running) {
++		int err;
++
++		err = bcm_enet_open(dev);
++		if (err)
++			dev_close(dev);
++		else
++			bcm_enet_set_multicast_list(dev);
++	}
++	return 0;
++}
++
++static void bcm_enet_get_pauseparam(struct net_device *dev,
++				    struct ethtool_pauseparam *ecmd)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++	ecmd->autoneg = priv->pause_auto;
++	ecmd->rx_pause = priv->pause_rx;
++	ecmd->tx_pause = priv->pause_tx;
++}
++
++static int bcm_enet_set_pauseparam(struct net_device *dev,
++				   struct ethtool_pauseparam *ecmd)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++
++	if (priv->has_phy) {
++		if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
++			/* asymetric pause mode not supported,
++			 * actually possible but integrated PHY has RO
++			 * asym_pause bit */
++			return -EINVAL;
++		}
++	} else {
++		/* no pause autoneg on direct mii connection */
++		if (ecmd->autoneg)
++			return -EINVAL;
++	}
++
++	priv->pause_auto = ecmd->autoneg;
++	priv->pause_rx = ecmd->rx_pause;
++	priv->pause_tx = ecmd->tx_pause;
++
++	return 0;
++}
++
++static struct ethtool_ops bcm_enet_ethtool_ops = {
++	.get_strings		= bcm_enet_get_strings,
++	.get_stats_count	= bcm_enet_get_stats_count,
++	.get_ethtool_stats      = bcm_enet_get_ethtool_stats,
++	.get_settings		= bcm_enet_get_settings,
++	.set_settings		= bcm_enet_set_settings,
++	.get_drvinfo		= bcm_enet_get_drvinfo,
++	.get_link		= ethtool_op_get_link,
++	.get_ringparam		= bcm_enet_get_ringparam,
++	.set_ringparam		= bcm_enet_set_ringparam,
++	.get_pauseparam		= bcm_enet_get_pauseparam,
++	.set_pauseparam		= bcm_enet_set_pauseparam,
++};
++
++static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	struct bcm_enet_priv *priv;
++
++	priv = netdev_priv(dev);
++	if (priv->has_phy) {
++		if (!priv->phydev)
++			return -ENODEV;
++		return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
++	} else {
++		struct mii_if_info mii;
++
++		mii.dev = dev;
++		mii.mdio_read = bcm_enet_mdio_read_mii;
++		mii.mdio_write = bcm_enet_mdio_write_mii;
++		mii.phy_id = 0;
++		mii.phy_id_mask = 0x3f;
++		mii.reg_num_mask = 0x1f;
++		return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
++	}
++}
++
++/*
++ * preinit hardware to allow mii operation while device is down
++ */
++static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
++{
++	u32 val;
++	int limit;
++
++	/* make sure mac is disabled */
++	bcm_enet_disable_mac(priv);
++
++	/* soft reset mac */
++	val = ENET_CTL_SRESET_MASK;
++	enet_writel(priv, val, ENET_CTL_REG);
++	wmb();
++
++	limit = 1000;
++	do {
++		val = enet_readl(priv, ENET_CTL_REG);
++		if (!(val & ENET_CTL_SRESET_MASK))
++			break;
++		udelay(1);
++	} while (limit--);
++
++	/* select correct mii interface */
++	val = enet_readl(priv, ENET_CTL_REG);
++	if (priv->use_external_mii)
++		val |= ENET_CTL_EPHYSEL_MASK;
++	else
++		val &= ~ENET_CTL_EPHYSEL_MASK;
++	enet_writel(priv, val, ENET_CTL_REG);
++
++	/* turn on mdc clock */
++	enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
++		    ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
++
++	/* set mib counters to self-clear when read */
++	val = enet_readl(priv, ENET_MIBCTL_REG);
++	val |= ENET_MIBCTL_RDCLEAR_MASK;
++	enet_writel(priv, val, ENET_MIBCTL_REG);
++}
++
++/*
++ * allocate netdevice, request register memory and register device.
++ */
++static int __devinit bcm_enet_probe(struct platform_device *pdev)
++{
++	struct bcm_enet_priv *priv;
++	struct net_device *dev;
++	struct bcm63xx_enet_platform_data *pd;
++	struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
++	struct mii_bus *bus;
++	const char *clk_name;
++	unsigned int iomem_size;
++	int i, ret, mdio_registered, mem_requested;
++
++	/* stop if shared driver failed, assume driver->probe will be
++	 * called in the same order we register devices (correct ?) */
++	if (!bcm_enet_shared_base)
++		return -ENODEV;
++
++	mdio_registered = mem_requested = 0;
++
++	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
++	res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
++	if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
++		return -ENODEV;
++
++	ret = 0;
++	dev = alloc_etherdev(sizeof(*priv));
++	if (!dev)
++		return -ENOMEM;
++	priv = netdev_priv(dev);
++	memset(priv, 0, sizeof(*priv));
++
++	iomem_size = res_mem->end - res_mem->start + 1;
++	if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
++		ret = -EBUSY;
++		goto err;
++	}
++	mem_requested = 1;
++
++	priv->base = ioremap(res_mem->start, iomem_size);
++	if (priv->base == NULL) {
++		ret = -ENOMEM;
++		goto err;
++	}
++	dev->irq = priv->irq = res_irq->start;
++	priv->irq_rx = res_irq_rx->start;
++	priv->irq_tx = res_irq_tx->start;
++	priv->mac_id = pdev->id;
++
++	/* get rx & tx dma channel id for this mac */
++	if (priv->mac_id == 0) {
++		priv->rx_chan = 0;
++		priv->tx_chan = 1;
++		clk_name = "enet0";
++	} else {
++		priv->rx_chan = 2;
++		priv->tx_chan = 3;
++		clk_name = "enet1";
++	}
++
++	priv->mac_clk = clk_get(&pdev->dev, clk_name);
++	if (IS_ERR(priv->mac_clk)) {
++		ret = PTR_ERR(priv->mac_clk);
++		priv->mac_clk = NULL;
++		goto err;
++	}
++	clk_enable(priv->mac_clk);
++
++	/* initialize default and fetch platform data */
++	priv->rx_ring_size = BCMENET_DEF_RX_DESC;
++	priv->tx_ring_size = BCMENET_DEF_TX_DESC;
++
++	pd = pdev->dev.platform_data;
++	if (pd) {
++		memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
++		priv->has_phy = pd->has_phy;
++		priv->phy_id = pd->phy_id;
++		priv->has_phy_interrupt = pd->has_phy_interrupt;
++		priv->phy_interrupt = pd->phy_interrupt;
++		priv->use_external_mii = !pd->use_internal_phy;
++		priv->pause_auto = pd->pause_auto;
++		priv->pause_rx = pd->pause_rx;
++		priv->pause_tx = pd->pause_tx;
++		priv->force_duplex_full = pd->force_duplex_full;
++		priv->force_speed_100 = pd->force_speed_100;
++	}
++
++	if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
++		/* using internal PHY, enable clock */
++		priv->phy_clk = clk_get(&pdev->dev, "ephy");
++		if (IS_ERR(priv->phy_clk)) {
++			ret = PTR_ERR(priv->phy_clk);
++			priv->phy_clk = NULL;
++			goto err;
++		}
++		clk_enable(priv->phy_clk);
++	}
++
++	/* do minimal hardware init to be able to probe mii bus */
++	bcm_enet_hw_preinit(priv);
++
++	/* MII bus registration */
++	if (priv->has_phy) {
++		bus = &priv->mii_bus;
++		bus->name = "bcm63xx_enet MII bus";
++		bus->dev = &pdev->dev;
++		bus->priv = priv;
++		bus->read = bcm_enet_mdio_read_phylib;
++		bus->write = bcm_enet_mdio_write_phylib;
++		sprintf(bus->id, "%d", priv->mac_id);
++
++		/* only probe bus where we think the PHY is, because
++		 * the mdio read operation return 0 instead of 0xffff
++		 * if a slave is not present on hw */
++		bus->phy_mask = ~(1 << priv->phy_id);
++
++		bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
++		if (!bus->irq) {
++			ret = -ENOMEM;
++			goto err;
++		}
++
++		if (priv->has_phy_interrupt)
++			bus->irq[priv->phy_id] = priv->phy_interrupt;
++		else
++			bus->irq[priv->phy_id] = PHY_POLL;
++
++		ret = mdiobus_register(bus);
++		if (ret) {
++			dev_err(&pdev->dev, "unable to register mdio bus\n");
++			goto err;
++		}
++		mdio_registered = 1;
++	} else {
++
++		/* run platform code to initialize PHY device */
++		if (pd->mii_config &&
++		    pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
++				   bcm_enet_mdio_write_mii)) {
++			dev_err(&pdev->dev, "unable to configure mdio bus\n");
++			goto err;
++		}
++	}
++
++	spin_lock_init(&priv->rx_lock);
++
++	/* init rx timeout (used for oom) */
++	init_timer(&priv->rx_timeout);
++	priv->rx_timeout.function = bcm_enet_refill_rx_timer;
++	priv->rx_timeout.data = (unsigned long)dev;
++
++	/* init the mib update lock&work */
++	mutex_init(&priv->mib_update_lock);
++	INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
++
++	/* zero mib counters */
++	for (i = 0; i < ENET_MIB_REG_COUNT; i++)
++		enet_writel(priv, 0, ENET_MIB_REG(i));
++
++	/* register netdevice */
++	dev->open = bcm_enet_open;
++	dev->stop = bcm_enet_stop;
++	dev->hard_start_xmit = bcm_enet_start_xmit;
++	dev->get_stats = bcm_enet_get_stats;
++	dev->set_mac_address = bcm_enet_set_mac_address;
++	dev->set_multicast_list = bcm_enet_set_multicast_list;
++	netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
++	dev->do_ioctl = bcm_enet_ioctl;
++#ifdef CONFIG_NET_POLL_CONTROLLER
++	dev->poll_controller = bcm_enet_netpoll;
++#endif
++
++	SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
++
++	ret = register_netdev(dev);
++	if (ret)
++		goto err;
++
++	platform_set_drvdata(pdev, dev);
++	priv->pdev = pdev;
++	priv->net_dev = dev;
++	SET_NETDEV_DEV(dev, &pdev->dev);
++
++	return 0;
++
++err:
++	if (mem_requested)
++		release_mem_region(res_mem->start, iomem_size);
++	if (mdio_registered)
++		mdiobus_unregister(&priv->mii_bus);
++	kfree(priv->mii_bus.irq);
++	if (priv->mac_clk) {
++		clk_disable(priv->mac_clk);
++		clk_put(priv->mac_clk);
++	}
++	if (priv->phy_clk) {
++		clk_disable(priv->phy_clk);
++		clk_put(priv->phy_clk);
++	}
++	if (priv->base) {
++		/* turn off mdc clock */
++		enet_writel(priv, 0, ENET_MIISC_REG);
++		iounmap(priv->base);
++	}
++	free_netdev(dev);
++	return ret;
++}
++
++
++/*
++ * exit func, stops hardware and unregisters netdevice
++ */
++static int __devexit bcm_enet_remove(struct platform_device *pdev)
++{
++	struct bcm_enet_priv *priv;
++	struct net_device *dev;
++	struct resource *res;
++
++	/* stop netdevice */
++	dev = platform_get_drvdata(pdev);
++	priv = netdev_priv(dev);
++	unregister_netdev(dev);
++
++	/* turn off mdc clock */
++	enet_writel(priv, 0, ENET_MIISC_REG);
++
++	if (priv->has_phy) {
++		mdiobus_unregister(&priv->mii_bus);
++		kfree(priv->mii_bus.irq);
++	} else {
++		struct bcm63xx_enet_platform_data *pd;
++
++		pd = pdev->dev.platform_data;
++		if (pd && pd->mii_config)
++			pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
++				       bcm_enet_mdio_write_mii);
++	}
++
++	/* release device resources */
++	iounmap(priv->base);
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	release_mem_region(res->start, res->end - res->start + 1);
++
++	/* disable hw block clocks */
++	if (priv->phy_clk) {
++		clk_disable(priv->phy_clk);
++		clk_put(priv->phy_clk);
++	}
++	clk_disable(priv->mac_clk);
++	clk_put(priv->mac_clk);
++
++	free_netdev(dev);
++	return 0;
++}
++
++struct platform_driver bcm63xx_enet_driver = {
++	.probe	= bcm_enet_probe,
++	.remove	= __devexit_p(bcm_enet_remove),
++	.driver	= {
++		.name	= "bcm63xx_enet",
++		.owner  = THIS_MODULE,
++	},
++};
++
++/*
++ * reserve & remap memory space shared between all macs
++ */
++static int __devinit bcm_enet_shared_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	unsigned int iomem_size;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENODEV;
++
++	iomem_size = res->end - res->start + 1;
++	if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
++		return -EBUSY;
++
++	bcm_enet_shared_base = ioremap(res->start, iomem_size);
++	if (!bcm_enet_shared_base) {
++		release_mem_region(res->start, iomem_size);
++		return -ENOMEM;
++	}
++	return 0;
++}
++
++static int __devexit bcm_enet_shared_remove(struct platform_device *pdev)
++{
++	struct resource *res;
++
++	iounmap(bcm_enet_shared_base);
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	release_mem_region(res->start, res->end - res->start + 1);
++	return 0;
++}
++
++/*
++ * this "shared" driver is needed because both macs share a single
++ * address space
++ */
++struct platform_driver bcm63xx_enet_shared_driver = {
++	.probe	= bcm_enet_shared_probe,
++	.remove	= __devexit_p(bcm_enet_shared_remove),
++	.driver	= {
++		.name	= "bcm63xx_enet_shared",
++		.owner  = THIS_MODULE,
++	},
++};
++
++/*
++ * entry point
++ */
++static int __init bcm_enet_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&bcm63xx_enet_shared_driver);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&bcm63xx_enet_driver);
++	if (ret)
++		platform_driver_unregister(&bcm63xx_enet_shared_driver);
++
++	return ret;
++}
++
++static void __exit bcm_enet_exit(void)
++{
++	platform_driver_unregister(&bcm63xx_enet_driver);
++	platform_driver_unregister(&bcm63xx_enet_shared_driver);
++}
++
++
++module_init(bcm_enet_init);
++module_exit(bcm_enet_exit);
++
++MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
++MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/net/bcm63xx_enet.h b/drivers/net/bcm63xx_enet.h
+new file mode 100644
+index 0000000..fe7ffc1
+--- /dev/null
++++ b/drivers/net/bcm63xx_enet.h
+@@ -0,0 +1,294 @@
++#ifndef BCM63XX_ENET_H_
++#define BCM63XX_ENET_H_
++
++#include <linux/types.h>
++#include <linux/mii.h>
++#include <linux/mutex.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#include <bcm63xx_regs.h>
++#include <bcm63xx_irq.h>
++#include <bcm63xx_io.h>
++
++/* default number of descriptor */
++#define BCMENET_DEF_RX_DESC	64
++#define BCMENET_DEF_TX_DESC	32
++
++/* maximum burst len for dma (4 bytes unit) */
++#define BCMENET_DMA_MAXBURST	16
++
++/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
++ * must be low enough so that a DMA transfer of above burst length can
++ * not overflow the fifo  */
++#define BCMENET_TX_FIFO_TRESH	32
++
++/* maximum rx/tx packet size */
++#define	BCMENET_MAX_RX_SIZE	(ETH_FRAME_LEN + 4)
++#define	BCMENET_MAX_TX_SIZE	(ETH_FRAME_LEN + 4)
++
++/*
++ * rx/tx dma descriptor
++ */
++struct bcm_enet_desc {
++	u32 len_stat;
++	u32 address;
++};
++
++#define DMADESC_LENGTH_SHIFT	16
++#define DMADESC_LENGTH_MASK	(0xfff << DMADESC_LENGTH_SHIFT)
++#define DMADESC_OWNER_MASK	(1 << 15)
++#define DMADESC_EOP_MASK	(1 << 14)
++#define DMADESC_SOP_MASK	(1 << 13)
++#define DMADESC_ESOP_MASK	(DMADESC_EOP_MASK | DMADESC_SOP_MASK)
++#define DMADESC_WRAP_MASK	(1 << 12)
++
++#define DMADESC_UNDER_MASK	(1 << 9)
++#define DMADESC_APPEND_CRC	(1 << 8)
++#define DMADESC_OVSIZE_MASK	(1 << 4)
++#define DMADESC_RXER_MASK	(1 << 2)
++#define DMADESC_CRC_MASK	(1 << 1)
++#define DMADESC_OV_MASK		(1 << 0)
++#define DMADESC_ERR_MASK	(DMADESC_UNDER_MASK | \
++				DMADESC_OVSIZE_MASK | \
++				DMADESC_RXER_MASK | \
++				DMADESC_CRC_MASK | \
++				DMADESC_OV_MASK)
++
++
++/*
++ * MIB Counters register definitions
++*/
++#define ETH_MIB_TX_GD_OCTETS			0
++#define ETH_MIB_TX_GD_PKTS			1
++#define ETH_MIB_TX_ALL_OCTETS			2
++#define ETH_MIB_TX_ALL_PKTS			3
++#define ETH_MIB_TX_BRDCAST			4
++#define ETH_MIB_TX_MULT				5
++#define ETH_MIB_TX_64				6
++#define ETH_MIB_TX_65_127			7
++#define ETH_MIB_TX_128_255			8
++#define ETH_MIB_TX_256_511			9
++#define ETH_MIB_TX_512_1023			10
++#define ETH_MIB_TX_1024_MAX			11
++#define ETH_MIB_TX_JAB				12
++#define ETH_MIB_TX_OVR				13
++#define ETH_MIB_TX_FRAG				14
++#define ETH_MIB_TX_UNDERRUN			15
++#define ETH_MIB_TX_COL				16
++#define ETH_MIB_TX_1_COL			17
++#define ETH_MIB_TX_M_COL			18
++#define ETH_MIB_TX_EX_COL			19
++#define ETH_MIB_TX_LATE				20
++#define ETH_MIB_TX_DEF				21
++#define ETH_MIB_TX_CRS				22
++#define ETH_MIB_TX_PAUSE			23
++
++#define ETH_MIB_RX_GD_OCTETS			32
++#define ETH_MIB_RX_GD_PKTS			33
++#define ETH_MIB_RX_ALL_OCTETS			34
++#define ETH_MIB_RX_ALL_PKTS			35
++#define ETH_MIB_RX_BRDCAST			36
++#define ETH_MIB_RX_MULT				37
++#define ETH_MIB_RX_64				38
++#define ETH_MIB_RX_65_127			39
++#define ETH_MIB_RX_128_255			40
++#define ETH_MIB_RX_256_511			41
++#define ETH_MIB_RX_512_1023			42
++#define ETH_MIB_RX_1024_MAX			43
++#define ETH_MIB_RX_JAB				44
++#define ETH_MIB_RX_OVR				45
++#define ETH_MIB_RX_FRAG				46
++#define ETH_MIB_RX_DROP				47
++#define ETH_MIB_RX_CRC_ALIGN			48
++#define ETH_MIB_RX_UND				49
++#define ETH_MIB_RX_CRC				50
++#define ETH_MIB_RX_ALIGN			51
++#define ETH_MIB_RX_SYM				52
++#define ETH_MIB_RX_PAUSE			53
++#define ETH_MIB_RX_CNTRL			54
++
++
++struct bcm_enet_mib_counters {
++	u64 tx_gd_octets;
++	u32 tx_gd_pkts;
++	u32 tx_all_octets;
++	u32 tx_all_pkts;
++	u32 tx_brdcast;
++	u32 tx_mult;
++	u32 tx_64;
++	u32 tx_65_127;
++	u32 tx_128_255;
++	u32 tx_256_511;
++	u32 tx_512_1023;
++	u32 tx_1024_max;
++	u32 tx_jab;
++	u32 tx_ovr;
++	u32 tx_frag;
++	u32 tx_underrun;
++	u32 tx_col;
++	u32 tx_1_col;
++	u32 tx_m_col;
++	u32 tx_ex_col;
++	u32 tx_late;
++	u32 tx_def;
++	u32 tx_crs;
++	u32 tx_pause;
++	u64 rx_gd_octets;
++	u32 rx_gd_pkts;
++	u32 rx_all_octets;
++	u32 rx_all_pkts;
++	u32 rx_brdcast;
++	u32 rx_mult;
++	u32 rx_64;
++	u32 rx_65_127;
++	u32 rx_128_255;
++	u32 rx_256_511;
++	u32 rx_512_1023;
++	u32 rx_1024_max;
++	u32 rx_jab;
++	u32 rx_ovr;
++	u32 rx_frag;
++	u32 rx_drop;
++	u32 rx_crc_align;
++	u32 rx_und;
++	u32 rx_crc;
++	u32 rx_align;
++	u32 rx_sym;
++	u32 rx_pause;
++	u32 rx_cntrl;
++};
++
++
++struct bcm_enet_priv {
++
++	/* mac id (from platform device id) */
++	int mac_id;
++
++	/* base remapped address of device */
++	void __iomem *base;
++
++	/* mac irq, rx_dma irq, tx_dma irq */
++	int irq;
++	int irq_rx;
++	int irq_tx;
++
++	/* hw view of rx & tx dma ring */
++	dma_addr_t rx_desc_dma;
++	dma_addr_t tx_desc_dma;
++
++	/* allocated size (in bytes) for rx & tx dma ring */
++	unsigned int rx_desc_alloc_size;
++	unsigned int tx_desc_alloc_size;
++
++
++	struct napi_struct napi;
++
++	/* dma channel id for rx */
++	int rx_chan;
++
++	/* number of dma desc in rx ring */
++	int rx_ring_size;
++
++	/* cpu view of rx dma ring */
++	struct bcm_enet_desc *rx_desc_cpu;
++
++	/* current number of armed descriptor given to hardware for rx */
++	int rx_desc_count;
++
++	/* next rx descriptor to fetch from hardware */
++	int rx_curr_desc;
++
++	/* next dirty rx descriptor to refill */
++	int rx_dirty_desc;
++
++	/* list of skb given to hw for rx */
++	struct sk_buff **rx_skb;
++
++	/* used when rx skb allocation failed, so we defer rx queue
++	 * refill */
++	struct timer_list rx_timeout;
++
++	/* lock rx_timeout against rx normal operation */
++	spinlock_t rx_lock;
++
++
++	/* dma channel id for tx */
++	int tx_chan;
++
++	/* number of dma desc in tx ring */
++	int tx_ring_size;
++
++	/* cpu view of rx dma ring */
++	struct bcm_enet_desc *tx_desc_cpu;
++
++	/* number of available descriptor for tx */
++	int tx_desc_count;
++
++	/* next tx descriptor avaiable */
++	int tx_curr_desc;
++
++	/* next dirty tx descriptor to reclaim */
++	int tx_dirty_desc;
++
++	/* list of skb given to hw for tx */
++	struct sk_buff **tx_skb;
++
++	/* lock used by tx reclaim and xmit */
++	spinlock_t tx_lock;
++
++
++	/* set if internal phy is ignored and external mii interface
++	 * is selected */
++	int use_external_mii;
++
++	/* set if a phy is connected, phy address must be known,
++	 * probing is not possible */
++	int has_phy;
++	int phy_id;
++
++	/* set if connected phy has an associated irq */
++	int has_phy_interrupt;
++	int phy_interrupt;
++
++	/* used when a phy is connected (phylib used) */
++	struct mii_bus mii_bus;
++	struct phy_device *phydev;
++	int old_link;
++	int old_duplex;
++	int old_pause;
++
++	/* used when no phy is connected */
++	int force_speed_100;
++	int force_duplex_full;
++
++	/* pause parameters */
++	int pause_auto;
++	int pause_rx;
++	int pause_tx;
++
++	/* stats */
++	struct net_device_stats stats;
++	struct bcm_enet_mib_counters mib;
++
++	/* after mib interrupt, mib registers update is done in this
++	 * work queue */
++	struct work_struct mib_update_task;
++
++	/* lock mib update between userspace request and workqueue */
++	struct mutex mib_update_lock;
++
++	/* mac clock */
++	struct clk *mac_clk;
++
++	/* phy clock if internal phy is used */
++	struct clk *phy_clk;
++
++	/* network device reference */
++	struct net_device *net_dev;
++
++	/* platform device reference */
++	struct platform_device *pdev;
++};
++
++#endif /* ! BCM63XX_ENET_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h
+new file mode 100644
+index 0000000..d53f611
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -0,0 +1,45 @@
++#ifndef BCM63XX_DEV_ENET_H_
++#define BCM63XX_DEV_ENET_H_
++
++#include <linux/if_ether.h>
++#include <linux/init.h>
++
++/*
++ * on board ethernet platform data
++ */
++struct bcm63xx_enet_platform_data {
++	char mac_addr[ETH_ALEN];
++
++	int has_phy;
++
++	/* if has_phy, then set use_internal_phy */
++	int use_internal_phy;
++
++	/* or fill phy info to use an external one */
++	int phy_id;
++	int has_phy_interrupt;
++	int phy_interrupt;
++
++	/* if has_phy, use autonegociated pause parameters or force
++	 * them */
++	int pause_auto;
++	int pause_rx;
++	int pause_tx;
++
++	/* if !has_phy, set desired forced speed/duplex */
++	int force_speed_100;
++	int force_duplex_full;
++
++	/* if !has_phy, set callback to perform mii device
++	 * init/remove */
++	int (*mii_config)(struct net_device *dev, int probe,
++			  int (*mii_read)(struct net_device *dev,
++					  int phy_id, int reg),
++			  void (*mii_write)(struct net_device *dev,
++					    int phy_id, int reg, int val));
++};
++
++int __init bcm63xx_enet_register(int unit,
++				 const struct bcm63xx_enet_platform_data *pd);
++
++#endif /* ! BCM63XX_DEV_ENET_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/010-add_integrated_ethernet_phy_support.patch b/target/linux/brcm63xx/patches-2.6.27/010-add_integrated_ethernet_phy_support.patch
new file mode 100644
index 0000000..0ccafc1
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/010-add_integrated_ethernet_phy_support.patch
@@ -0,0 +1,183 @@
+From 7eefcb968019804e024c8243e28afb1eebd674a2 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Sun, 21 Sep 2008 02:20:53 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add integrated ethernet PHY support for phylib.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ drivers/net/phy/Kconfig   |    6 ++
+ drivers/net/phy/Makefile  |    1 +
+ drivers/net/phy/bcm63xx.c |  132 +++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 139 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/net/phy/bcm63xx.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index d55932a..a5d2c2d 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -56,6 +56,12 @@ config BROADCOM_PHY
+ 	  Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481
+ 	  and BCM5482 PHYs.
+ 
++config BCM63XX_PHY
++	tristate "Drivers for Broadcom 63xx SOCs internal PHY"
++	depends on BCM63XX
++	---help---
++	  Currently supports the 6348 and 6358 PHYs.
++
+ config ICPLUS_PHY
+ 	tristate "Drivers for ICPlus PHYs"
+ 	---help---
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index eee329f..0d43f58 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
+ obj-$(CONFIG_SMSC_PHY)		+= smsc.o
+ obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o
+ obj-$(CONFIG_BROADCOM_PHY)	+= broadcom.o
++obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
+ obj-$(CONFIG_ICPLUS_PHY)	+= icplus.o
+ obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
+ obj-$(CONFIG_FIXED_PHY)		+= fixed.o
+diff --git a/drivers/net/phy/bcm63xx.c b/drivers/net/phy/bcm63xx.c
+new file mode 100644
+index 0000000..4fed95e
+--- /dev/null
++++ b/drivers/net/phy/bcm63xx.c
+@@ -0,0 +1,132 @@
++/*
++ *	Driver for Broadcom 63xx SOCs integrated PHYs
++ *
++ *	This program is free software; you can redistribute it and/or
++ *	modify it under the terms of the GNU General Public License
++ *	as published by the Free Software Foundation; either version
++ *	2 of the License, or (at your option) any later version.
++ */
++#include <linux/module.h>
++#include <linux/phy.h>
++
++#define MII_BCM63XX_IR		0x1a	/* interrupt register */
++#define MII_BCM63XX_IR_EN	0x4000	/* global interrupt enable */
++#define MII_BCM63XX_IR_DUPLEX	0x0800	/* duplex changed */
++#define MII_BCM63XX_IR_SPEED	0x0400	/* speed changed */
++#define MII_BCM63XX_IR_LINK	0x0200	/* link changed */
++#define MII_BCM63XX_IR_GMASK	0x0100	/* global interrupt mask */
++
++MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver");
++MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
++MODULE_LICENSE("GPL");
++
++static int bcm63xx_config_init(struct phy_device *phydev)
++{
++	int reg, err;
++
++	reg = phy_read(phydev, MII_BCM63XX_IR);
++	if (reg < 0)
++		return reg;
++
++	/* Mask interrupts globally.  */
++	reg |= MII_BCM63XX_IR_GMASK;
++	err = phy_write(phydev, MII_BCM63XX_IR, reg);
++	if (err < 0)
++		return err;
++
++	/* Unmask events we are interested in  */
++	reg = ~(MII_BCM63XX_IR_DUPLEX |
++		MII_BCM63XX_IR_SPEED |
++		MII_BCM63XX_IR_LINK) |
++		MII_BCM63XX_IR_EN;
++	err = phy_write(phydev, MII_BCM63XX_IR, reg);
++	if (err < 0)
++		return err;
++	return 0;
++}
++
++static int bcm63xx_ack_interrupt(struct phy_device *phydev)
++{
++	int reg;
++
++	/* Clear pending interrupts.  */
++	reg = phy_read(phydev, MII_BCM63XX_IR);
++	if (reg < 0)
++		return reg;
++
++	return 0;
++}
++
++static int bcm63xx_config_intr(struct phy_device *phydev)
++{
++	int reg, err;
++
++	reg = phy_read(phydev, MII_BCM63XX_IR);
++	if (reg < 0)
++		return reg;
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
++		reg &= ~MII_BCM63XX_IR_GMASK;
++	else
++		reg |= MII_BCM63XX_IR_GMASK;
++
++	err = phy_write(phydev, MII_BCM63XX_IR, reg);
++	return err;
++}
++
++static struct phy_driver bcm63xx_1_driver = {
++	.phy_id		= 0x00406000,
++	.phy_id_mask	= 0xfffffc00,
++	.name		= "Broadcom BCM63XX (1)",
++	/* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */
++	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
++	.flags		= PHY_HAS_INTERRUPT,
++	.config_init	= bcm63xx_config_init,
++	.config_aneg	= genphy_config_aneg,
++	.read_status	= genphy_read_status,
++	.ack_interrupt	= bcm63xx_ack_interrupt,
++	.config_intr	= bcm63xx_config_intr,
++	.driver		= { .owner = THIS_MODULE },
++};
++
++/* same phy as above, with just a different OUI */
++static struct phy_driver bcm63xx_2_driver = {
++	.phy_id		= 0x002bdc00,
++	.phy_id_mask	= 0xfffffc00,
++	.name		= "Broadcom BCM63XX (2)",
++	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
++	.flags		= PHY_HAS_INTERRUPT,
++	.config_init	= bcm63xx_config_init,
++	.config_aneg	= genphy_config_aneg,
++	.read_status	= genphy_read_status,
++	.ack_interrupt	= bcm63xx_ack_interrupt,
++	.config_intr	= bcm63xx_config_intr,
++	.driver		= { .owner = THIS_MODULE },
++};
++
++static int __init bcm63xx_phy_init(void)
++{
++	int ret;
++
++	ret = phy_driver_register(&bcm63xx_1_driver);
++	if (ret)
++		goto out_63xx_1;
++	ret = phy_driver_register(&bcm63xx_2_driver);
++	if (ret)
++		goto out_63xx_2;
++	return ret;
++
++out_63xx_2:
++	phy_driver_unregister(&bcm63xx_1_driver);
++out_63xx_1:
++	return ret;
++}
++
++static void __exit bcm63xx_phy_exit(void)
++{
++	phy_driver_unregister(&bcm63xx_1_driver);
++	phy_driver_unregister(&bcm63xx_2_driver);
++}
++
++module_init(bcm63xx_phy_init);
++module_exit(bcm63xx_phy_exit);
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/011-add_preliminary_board_support.patch b/target/linux/brcm63xx/patches-2.6.27/011-add_preliminary_board_support.patch
new file mode 100644
index 0000000..a738bcc
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/011-add_preliminary_board_support.patch
@@ -0,0 +1,539 @@
+From b95a2bbbcae5423e5404a7b3c8dd1685e1786f13 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Wed, 17 Sep 2008 15:55:36 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add preliminary board support.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/bcm63xx/Kconfig                      |    2 +
+ arch/mips/bcm63xx/Makefile                     |    2 +
+ arch/mips/bcm63xx/boards/Kconfig               |   10 +
+ arch/mips/bcm63xx/boards/Makefile              |    1 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c      |  322 ++++++++++++++++++++++++
+ arch/mips/bcm63xx/prom.c                       |    4 +
+ arch/mips/bcm63xx/setup.c                      |   16 +-
+ include/asm-mips/mach-bcm63xx/bcm63xx_board.h  |   12 +
+ include/asm-mips/mach-bcm63xx/board_bcm963xx.h |   50 ++++
+ 9 files changed, 417 insertions(+), 2 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/boards/Kconfig
+ create mode 100644 arch/mips/bcm63xx/boards/Makefile
+ create mode 100644 arch/mips/bcm63xx/boards/board_bcm963xx.c
+ create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_board.h
+ create mode 100644 include/asm-mips/mach-bcm63xx/board_bcm963xx.h
+
+diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
+index be120f7..8c192e7 100644
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -17,3 +17,5 @@ config BCM63XX_CPU_6358
+ 	select USB_ARCH_HAS_EHCI
+ 	select USB_EHCI_BIG_ENDIAN_MMIO
+ endmenu
++
++source "arch/mips/bcm63xx/boards/Kconfig"
+diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
+index 5358093..10462ae 100644
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -5,3 +5,5 @@ obj-y		+= dev-usb-ohci.o
+ obj-y		+= dev-usb-ehci.o
+ obj-y		+= dev-enet.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
++
++obj-y		+= boards/
+diff --git a/arch/mips/bcm63xx/boards/Kconfig b/arch/mips/bcm63xx/boards/Kconfig
+new file mode 100644
+index 0000000..da5eeaa
+--- /dev/null
++++ b/arch/mips/bcm63xx/boards/Kconfig
+@@ -0,0 +1,10 @@
++choice
++	prompt "Board support"
++	depends on BCM63XX
++	default BOARD_BCM963XX
++
++config BOARD_BCM963XX
++       bool "Generic Broadcom 963xx boards"
++       help
++
++endchoice
+diff --git a/arch/mips/bcm63xx/boards/Makefile b/arch/mips/bcm63xx/boards/Makefile
+new file mode 100644
+index 0000000..af07c1a
+--- /dev/null
++++ b/arch/mips/bcm63xx/boards/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_BOARD_BCM963XX)		+= board_bcm963xx.o
+diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+new file mode 100644
+index 0000000..de52a2a
+--- /dev/null
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -0,0 +1,322 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/physmap.h>
++#include <asm/addrspace.h>
++#include <bcm63xx_board.h>
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_board.h>
++#include <bcm63xx_dev_pci.h>
++#include <bcm63xx_dev_uart.h>
++#include <bcm63xx_dev_enet.h>
++#include <bcm63xx_dev_pcmcia.h>
++#include <bcm63xx_dev_usb_ohci.h>
++#include <bcm63xx_dev_usb_ehci.h>
++#include <board_bcm963xx.h>
++
++#define PFX	"board_bcm963xx: "
++
++static struct bcm963xx_nvram nvram;
++static unsigned int mac_addr_used = 0;
++static struct board_info board;
++
++/*
++ * known 6348 boards
++ */
++#ifdef CONFIG_BCM63XX_CPU_6348
++static struct board_info __initdata board_96348r = {
++	.name				= "96348R",
++	.expected_cpu_id		= 0x6348,
++
++	.has_enet0			= 1,
++	.has_pci			= 1,
++
++	.enet0 = {
++		.has_phy		= 1,
++		.use_internal_phy	= 1,
++	},
++};
++
++static struct board_info __initdata board_96348gw = {
++	.name				= "96348GW",
++	.expected_cpu_id		= 0x6348,
++
++	.has_enet0			= 1,
++	.has_pci			= 1,
++
++	.enet0 = {
++		.has_phy		= 1,
++		.use_internal_phy	= 1,
++	},
++};
++#endif
++
++/*
++ * known 6358 boards
++ */
++#ifdef CONFIG_BCM63XX_CPU_6358
++static struct board_info __initdata board_96358vw2 = {
++	.name				= "96358VW2",
++	.expected_cpu_id		= 0x6358,
++
++	.has_enet0			= 1,
++	.has_enet1			= 1,
++	.has_pci			= 1,
++
++	.enet0 = {
++		.has_phy		= 1,
++		.use_internal_phy	= 1,
++	},
++
++	.enet1 = {
++		.force_speed_100	= 1,
++		.force_duplex_full	= 1,
++	},
++
++
++	.has_ohci0 = 1,
++	.has_pccard = 1,
++	.has_ehci0 = 1,
++};
++#endif
++
++/*
++ * all boards
++ */
++static const struct board_info __initdata *bcm963xx_boards[] = {
++#ifdef CONFIG_BCM63XX_CPU_6348
++	&board_96348r,
++	&board_96348gw,
++#endif
++
++#ifdef CONFIG_BCM63XX_CPU_6358
++	&board_96358vw2,
++#endif
++};
++
++/*
++ * early init callback, read nvram data from flash and checksum it
++ */
++void __init board_prom_init(void)
++{
++	unsigned int check_len, i;
++	u8 *boot_addr, *cfe, *p;
++	char cfe_version[32];
++	u32 val;
++
++	/* read base address of boot chip select (0) */
++	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++	val &= MPI_CSBASE_BASE_MASK;
++	boot_addr = (u8 *)KSEG1ADDR(val);
++
++	/* dump cfe version */
++	cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
++	if (!memcmp(cfe, "cfe-v", 5))
++		snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
++			 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
++	else
++		strcpy(cfe_version, "unknown");
++	printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
++
++	/* extract nvram data */
++	memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));
++
++	/* check checksum before using data */
++	if (nvram.version <= 4)
++		check_len = offsetof(struct bcm963xx_nvram, checksum_old);
++	else
++		check_len = sizeof(nvram);
++	val = 0;
++	p = (u8 *)&nvram;
++	while (check_len--)
++		val += *p;
++	if (val) {
++		printk(KERN_ERR PFX "invalid nvram checksum\n");
++		return;
++	}
++
++	/* find board by name */
++	for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
++		if (strncmp(nvram.name, bcm963xx_boards[i]->name,
++			    sizeof(nvram.name)))
++			continue;
++		/* copy, board desc array is marked initdata */
++		memcpy(&board, bcm963xx_boards[i], sizeof(board));
++		break;
++	}
++
++	/* bail out if board is not found, will complain later */
++	if (!board.name)
++		return;
++
++	/* setup pin multiplexing depending on board enabled device,
++	 * this has to be done this early since PCI init is done
++	 * inside arch_initcall */
++	val = 0;
++
++	if (board.has_pci) {
++		bcm63xx_pci_enabled = 1;
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G2_PCI;
++	}
++
++	if (board.has_pccard) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G1_MII_PCCARD;
++	}
++
++	if (board.has_enet0 && !board.enet0.use_internal_phy) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G3_EXT_MII |
++				GPIO_MODE_6348_G0_EXT_MII;
++	}
++
++	if (board.has_enet1 && !board.enet1.use_internal_phy) {
++		if (BCMCPU_IS_6348())
++			val |= GPIO_MODE_6348_G3_EXT_MII |
++				GPIO_MODE_6348_G0_EXT_MII;
++	}
++
++	bcm_gpio_writel(val, GPIO_MODE_REG);
++}
++
++/*
++ * second stage init callback, good time to panic if we couldn't
++ * identify on which board we're running since early printk is working
++ */
++void __init board_setup(void)
++{
++	if (!board.name)
++		panic("unable to detect bcm963xx board");
++	printk(KERN_INFO PFX "board name: %s\n", board.name);
++
++	/* make sure we're running on expected cpu */
++	if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
++		panic("unexpected CPU for bcm963xx board");
++}
++
++/*
++ * return board name for /proc/cpuinfo
++ */
++const char *board_get_name(void)
++{
++	return board.name;
++}
++
++/*
++ * register & return a new board mac address
++ */
++static int board_get_mac_address(u8 *mac)
++{
++	u8 *p;
++	int count;
++
++	if (mac_addr_used >= nvram.mac_addr_count) {
++		printk(KERN_ERR PFX "not enough mac address\n");
++		return -ENODEV;
++	}
++
++	memcpy(mac, nvram.mac_addr_base, ETH_ALEN);
++	p = mac + ETH_ALEN - 1;
++	count = mac_addr_used;
++
++	while (count--) {
++		do {
++			(*p)++;
++			if (*p != 0)
++				break;
++			p--;
++		} while (p != mac);
++	}
++
++	if (p == mac) {
++		printk(KERN_ERR PFX "unable to fetch mac address\n");
++		return -ENODEV;
++	}
++
++	mac_addr_used++;
++	return 0;
++}
++
++static struct mtd_partition mtd_partitions[] = {
++	{
++		.name		= "cfe",
++		.offset		= 0x0,
++		.size		= 0x40000,
++	}
++};
++
++static struct physmap_flash_data flash_data = {
++	.width			= 2,
++	.nr_parts		= ARRAY_SIZE(mtd_partitions),
++	.parts			= mtd_partitions,
++};
++
++static struct resource mtd_resources[] = {
++	{
++		.start		= 0,	/* filled at runtime */
++		.end		= 0,	/* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	}
++};
++
++static struct platform_device mtd_dev = {
++	.name			= "physmap-flash",
++	.resource		= mtd_resources,
++	.num_resources		= ARRAY_SIZE(mtd_resources),
++	.dev			= {
++		.platform_data	= &flash_data,
++	},
++};
++
++/*
++ * third stage init callback, register all board devices.
++ */
++int __init board_register_devices(void)
++{
++	u32 val;
++
++	bcm63xx_uart_register();
++
++	if (board.has_pccard)
++		bcm63xx_pcmcia_register();
++
++	if (board.has_enet0 &&
++	    !board_get_mac_address(board.enet0.mac_addr))
++		bcm63xx_enet_register(0, &board.enet0);
++
++	if (board.has_enet1 &&
++	    !board_get_mac_address(board.enet1.mac_addr))
++		bcm63xx_enet_register(1, &board.enet1);
++
++	if (board.has_ohci0)
++		bcm63xx_ohci_register();
++
++	if (board.has_ehci0)
++		bcm63xx_ehci_register();
++
++
++	/* read base address of boot chip select (0) */
++	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++	val &= MPI_CSBASE_BASE_MASK;
++	mtd_resources[0].start = val;
++	mtd_resources[0].end = 0x1FFFFFFF;
++
++	platform_device_register(&mtd_dev);
++
++	return 0;
++}
++
+diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
+index f0b49e8..d97ceed 100644
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -9,6 +9,7 @@
+ #include <linux/init.h>
+ #include <linux/bootmem.h>
+ #include <asm/bootinfo.h>
++#include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
+@@ -36,6 +37,9 @@ void __init prom_init(void)
+ 
+ 	/* assign command line from kernel config */
+ 	strcpy(arcs_cmdline, CONFIG_CMDLINE);
++
++	/* do low level board init */
++	board_prom_init();
+ }
+ 
+ void __init prom_free_prom_memory(void)
+diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
+index 4d8b127..c4516fb 100644
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -16,6 +16,7 @@
+ #include <asm/time.h>
+ #include <asm/reboot.h>
+ #include <asm/cacheflush.h>
++#include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_io.h>
+@@ -87,8 +88,9 @@ static void __bcm63xx_machine_reboot(char *p)
+ const char *get_system_type(void)
+ {
+ 	static char buf[128];
+-	sprintf(buf, "bcm963xx (0x%04x/0x%04X)",
+-		bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
++	snprintf(buf, sizeof (buf), "bcm63xx/%s (0x%04x/0x%04X)",
++		 board_get_name(),
++		 bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
+ 	return buf;
+ }
+ 
+@@ -96,6 +98,7 @@ void __init plat_time_init(void)
+ {
+ 	mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
+ }
++
+ void __init plat_mem_setup(void)
+ {
+ 	add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
+@@ -107,4 +110,13 @@ void __init plat_mem_setup(void)
+ 	set_io_port_base(0);
+ 	ioport_resource.start = 0;
+ 	ioport_resource.end = ~0;
++
++	board_setup();
++}
++
++int __init bcm63xx_register_devices(void)
++{
++	return board_register_devices();
+ }
++
++device_initcall(bcm63xx_register_devices);
+diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_board.h b/include/asm-mips/mach-bcm63xx/bcm63xx_board.h
+new file mode 100644
+index 0000000..fa3e7e6
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/bcm63xx_board.h
+@@ -0,0 +1,12 @@
++#ifndef BCM63XX_BOARD_H_
++#define BCM63XX_BOARD_H_
++
++const char *board_get_name(void);
++
++void board_prom_init(void);
++
++void board_setup(void);
++
++int board_register_devices(void);
++
++#endif /* ! BCM63XX_BOARD_H_ */
+diff --git a/include/asm-mips/mach-bcm63xx/board_bcm963xx.h b/include/asm-mips/mach-bcm63xx/board_bcm963xx.h
+new file mode 100644
+index 0000000..17e4e7e
+--- /dev/null
++++ b/include/asm-mips/mach-bcm63xx/board_bcm963xx.h
+@@ -0,0 +1,50 @@
++#ifndef BOARD_BCM963XX_H_
++#define BOARD_BCM963XX_H_
++
++#include <linux/types.h>
++#include <bcm63xx_dev_enet.h>
++
++/*
++ * flash mapping
++ */
++#define BCM963XX_CFE_VERSION_OFFSET	0x570
++#define BCM963XX_NVRAM_OFFSET		0x580
++
++/*
++ * nvram structure
++ */
++struct bcm963xx_nvram {
++	u32	version;
++	u8	reserved1[256];
++	u8	name[16];
++	u32	main_tp_number;
++	u32	psi_size;
++	u32	mac_addr_count;
++	u8	mac_addr_base[6];
++	u8	reserved2[2];
++	u32	checksum_old;
++	u8	reserved3[720];
++	u32	checksum_high;
++};
++
++/*
++ * board definition
++ */
++struct board_info {
++	u8		name[16];
++	unsigned int	expected_cpu_id;
++
++	/* enabled feature/device */
++	unsigned int	has_enet0:1;
++	unsigned int	has_enet1:1;
++	unsigned int	has_pci:1;
++	unsigned int	has_pccard:1;
++	unsigned int	has_ohci0:1;
++	unsigned int	has_ehci0:1;
++
++	/* ethernet config */
++	struct bcm63xx_enet_platform_data enet0;
++	struct bcm63xx_enet_platform_data enet1;
++};
++
++#endif /* ! BOARD_BCM963XX_H_ */
+-- 
+1.5.4.3
+
diff --git a/target/linux/brcm63xx/patches-2.6.27/012-add_defconfig.patch b/target/linux/brcm63xx/patches-2.6.27/012-add_defconfig.patch
new file mode 100644
index 0000000..5fc8847
--- /dev/null
+++ b/target/linux/brcm63xx/patches-2.6.27/012-add_defconfig.patch
@@ -0,0 +1,888 @@
+From 81ee4742b6f77589aa3b3d03b1878de1b9bf0855 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Mon, 22 Sep 2008 10:41:15 +0200
+Subject: [PATCH] [MIPS] BCM63XX: Add defconfig.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ arch/mips/configs/bcm63xx_defconfig |  868 +++++++++++++++++++++++++++++++++++
+ 1 files changed, 868 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/configs/bcm63xx_defconfig
+
+diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
+new file mode 100644
+index 0000000..65cacae
+--- /dev/null
++++ b/arch/mips/configs/bcm63xx_defconfig
+@@ -0,0 +1,868 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.27
++# Fri Oct 17 06:51:37 2008
++#
++CONFIG_MIPS=y
++
++#
++# Machine selection
++#
++# CONFIG_MACH_ALCHEMY is not set
++# CONFIG_BASLER_EXCITE is not set
++# CONFIG_BCM47XX is not set
++CONFIG_BCM63XX=y
++# CONFIG_MIPS_COBALT is not set
++# CONFIG_MACH_DECSTATION is not set
++# CONFIG_MACH_JAZZ is not set
++# CONFIG_LASAT is not set
++# CONFIG_LEMOTE_FULONG is not set
++# CONFIG_MIPS_MALTA is not set
++# CONFIG_MIPS_SIM is not set
++# CONFIG_MARKEINS is not set
++# CONFIG_MACH_VR41XX is not set
++# CONFIG_PNX8550_JBS is not set
++# CONFIG_PNX8550_STB810 is not set
++# CONFIG_PMC_MSP is not set
++# CONFIG_PMC_YOSEMITE is not set
++# CONFIG_SGI_IP22 is not set
++# CONFIG_SGI_IP27 is not set
++# CONFIG_SGI_IP28 is not set
++# CONFIG_SGI_IP32 is not set
++# CONFIG_SIBYTE_CRHINE is not set
++# CONFIG_SIBYTE_CARMEL is not set
++# CONFIG_SIBYTE_CRHONE is not set
++# CONFIG_SIBYTE_RHONE is not set
++# CONFIG_SIBYTE_SWARM is not set
++# CONFIG_SIBYTE_LITTLESUR is not set
++# CONFIG_SIBYTE_SENTOSA is not set
++# CONFIG_SIBYTE_BIGSUR is not set
++# CONFIG_SNI_RM is not set
++# CONFIG_MACH_TX39XX is not set
++# CONFIG_MACH_TX49XX is not set
++# CONFIG_MIKROTIK_RB532 is not set
++# CONFIG_WR_PPMC is not set
++
++#
++# CPU support
++#
++CONFIG_BCM63XX_CPU_6348=y
++CONFIG_BCM63XX_CPU_6358=y
++CONFIG_BOARD_BCM963XX=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_ARCH_SUPPORTS_OPROFILE=y
++CONFIG_GENERIC_FIND_NEXT_BIT=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CMOS_UPDATE=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
++# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
++CONFIG_CEVT_R4K=y
++CONFIG_CSRC_R4K=y
++CONFIG_DMA_NONCOHERENT=y
++CONFIG_DMA_NEED_PCI_MAP_STATE=y
++CONFIG_EARLY_PRINTK=y
++CONFIG_SYS_HAS_EARLY_PRINTK=y
++# CONFIG_HOTPLUG_CPU is not set
++# CONFIG_NO_IOPORT is not set
++CONFIG_GENERIC_GPIO=y
++CONFIG_CPU_BIG_ENDIAN=y
++# CONFIG_CPU_LITTLE_ENDIAN is not set
++CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
++CONFIG_IRQ_CPU=y
++CONFIG_SWAP_IO_SPACE=y
++CONFIG_MIPS_L1_CACHE_SHIFT=5
++
++#
++# CPU selection
++#
++# CONFIG_CPU_LOONGSON2 is not set
++CONFIG_CPU_MIPS32_R1=y
++# CONFIG_CPU_MIPS32_R2 is not set
++# CONFIG_CPU_MIPS64_R1 is not set
++# CONFIG_CPU_MIPS64_R2 is not set
++# CONFIG_CPU_R3000 is not set
++# CONFIG_CPU_TX39XX is not set
++# CONFIG_CPU_VR41XX is not set
++# CONFIG_CPU_R4300 is not set
++# CONFIG_CPU_R4X00 is not set
++# CONFIG_CPU_TX49XX is not set
++# CONFIG_CPU_R5000 is not set
++# CONFIG_CPU_R5432 is not set
++# CONFIG_CPU_R6000 is not set
++# CONFIG_CPU_NEVADA is not set
++# CONFIG_CPU_R8000 is not set
++# CONFIG_CPU_R10000 is not set
++# CONFIG_CPU_RM7000 is not set
++# CONFIG_CPU_RM9000 is not set
++# CONFIG_CPU_SB1 is not set
++CONFIG_SYS_HAS_CPU_MIPS32_R1=y
++CONFIG_CPU_MIPS32=y
++CONFIG_CPU_MIPSR1=y
++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
++
++#
++# Kernel type
++#
++CONFIG_32BIT=y
++# CONFIG_64BIT is not set
++CONFIG_PAGE_SIZE_4KB=y
++# CONFIG_PAGE_SIZE_8KB is not set
++# CONFIG_PAGE_SIZE_16KB is not set
++# CONFIG_PAGE_SIZE_64KB is not set
++CONFIG_CPU_HAS_PREFETCH=y
++CONFIG_MIPS_MT_DISABLED=y
++# CONFIG_MIPS_MT_SMP is not set
++# CONFIG_MIPS_MT_SMTC is not set
++CONFIG_CPU_HAS_LLSC=y
++CONFIG_CPU_HAS_SYNC=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_CPU_SUPPORTS_HIGHMEM=y
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_ARCH_POPULATES_NODE_MAP=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++# CONFIG_HIGH_RES_TIMERS is not set
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++# CONFIG_HZ_48 is not set
++# CONFIG_HZ_100 is not set
++# CONFIG_HZ_128 is not set
++CONFIG_HZ_250=y
++# CONFIG_HZ_256 is not set
++# CONFIG_HZ_1000 is not set
++# CONFIG_HZ_1024 is not set
++CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
++CONFIG_HZ=250
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_KEXEC is not set
++# CONFIG_SECCOMP is not set
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++# CONFIG_SWAP is not set
++# CONFIG_SYSVIPC is not set
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++# CONFIG_CGROUPS is not set
++# CONFIG_GROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
++# CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_BLK_DEV_INITRD is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++# CONFIG_PCSPKR_PLATFORM is not set
++CONFIG_COMPAT_BRK=y
++CONFIG_BASE_FULL=y
++# CONFIG_FUTEX is not set
++# CONFIG_EPOLL is not set
++# CONFIG_SIGNALFD is not set
++# CONFIG_TIMERFD is not set
++# CONFIG_EVENTFD is not set
++# CONFIG_SHMEM is not set
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
++# CONFIG_HAVE_IOREMAP_PROT is not set
++# CONFIG_HAVE_KPROBES is not set
++# CONFIG_HAVE_KRETPROBES is not set
++# CONFIG_HAVE_ARCH_TRACEHOOK is not set
++# CONFIG_HAVE_DMA_ATTRS is not set
++# CONFIG_USE_GENERIC_SMP_HELPERS is not set
++# CONFIG_HAVE_CLK is not set
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
++CONFIG_TINY_SHMEM=y
++CONFIG_BASE_SMALL=0
++# CONFIG_MODULES is not set
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_AS is not set
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++CONFIG_DEFAULT_NOOP=y
++CONFIG_DEFAULT_IOSCHED="noop"
++CONFIG_CLASSIC_RCU=y
++
++#
++# Bus options (PCI, PCMCIA, EISA, ISA, TC)
++#
++CONFIG_HW_HAS_PCI=y
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCI_LEGACY is not set
++CONFIG_MMU=y
++CONFIG_PCCARD=y
++# CONFIG_PCMCIA_DEBUG is not set
++CONFIG_PCMCIA=y
++CONFIG_PCMCIA_LOAD_CIS=y
++CONFIG_PCMCIA_IOCTL=y
++CONFIG_CARDBUS=y
++
++#
++# PC-card bridges
++#
++# CONFIG_YENTA is not set
++# CONFIG_PD6729 is not set
++# CONFIG_I82092 is not set
++CONFIG_PCMCIA_BCM63XX=y
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_MISC is not set
++CONFIG_TRAD_SIGNALS=y
++
++#
++# Power management options
++#
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++# CONFIG_PM is not set
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++# CONFIG_IP_PNP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_INET_DIAG is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_STANDALONE is not set
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++# CONFIG_MTD_CHAR is not set
++# CONFIG_MTD_BLKDEVS is not set
++# CONFIG_MTD_BLOCK is not set
++# CONFIG_MTD_BLOCK_RO is not set
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_START=0x8000000
++CONFIG_MTD_PHYSMAP_LEN=0
++CONFIG_MTD_PHYSMAP_BANKWIDTH=2
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++# CONFIG_MTD_NAND is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++# CONFIG_PARPORT is not set
++# CONFIG_BLK_DEV is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# Enable only one of the two stacks, unless you know what you are doing
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_IEEE1394 is not set
++# CONFIG_I2O is not set
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++CONFIG_BCM63XX_PHY=y
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_DM9000 is not set
++# CONFIG_NET_TULIP is not set
++# CONFIG_HP100 is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_NET_PCI is not set
++# CONFIG_B44 is not set
++CONFIG_BCM63XX_ENET=y
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_NET_PCMCIA is not set
++# CONFIG_WAN is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++# CONFIG_INPUT is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++# CONFIG_DEVKMEM is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++CONFIG_SERIAL_BCM63XX=y
++CONFIG_SERIAL_BCM63XX_CONSOLE=y
++# CONFIG_UNIX98_PTYS is not set
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_SYNCLINK_CS is not set
++# CONFIG_CARDMAN_4000 is not set
++# CONFIG_CARDMAN_4040 is not set
++# CONFIG_IPWIRELESS is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_I2C is not set
++# CONFIG_SPI is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_WATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_MFD_TMIO is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_VIDEO_MEDIA is not set
++
++#
++# Multimedia drivers
++#
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_DRM is not set
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++# CONFIG_FB is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=y
++
++#
++# Display hardware drivers
++#
++# CONFIG_SOUND is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
++
++#
++# Miscellaneous USB options
++#
++# CONFIG_USB_DEVICEFS is not set
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
++CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_GADGET is not set
++# CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++# CONFIG_DMADEVICES is not set
++# CONFIG_UIO is not set
++
++#
++# File systems
++#
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4DEV_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_INOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++# CONFIG_MSDOS_FS is not set
++# CONFIG_VFAT_FS is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS2_FS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_NLS is not set
++# CONFIG_DLM is not set
++
++#
++# Kernel hacking
++#
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_KERNEL is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++CONFIG_SYSCTL_SYSCALL_CHECK=y
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++CONFIG_CMDLINE="console=ttyS0,115200"
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_GENERIC_FIND_FIRST_BIT is not set
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
+-- 
+1.5.4.3
+