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author | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:14:12 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:14:12 +0000 |
commit | 1315058bda5b83bbb7f5a08319b69240dc957f14 (patch) | |
tree | af1dd5b1e3d09785cd1a38eab91126fd7013197b /target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch | |
parent | 4aa92df0d84d7e0bbafb15111bb3baa1ae3bf1de (diff) | |
download | mtk-20170518-1315058bda5b83bbb7f5a08319b69240dc957f14.zip mtk-20170518-1315058bda5b83bbb7f5a08319b69240dc957f14.tar.gz mtk-20170518-1315058bda5b83bbb7f5a08319b69240dc957f14.tar.bz2 |
brcm63xx: fix spi flash setup on (at least) some reference boards
CFE seems to leave the SPI flash mapping in an invalid state after
loading the kernel on some reference boards, so fix it up on boot.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 39273
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch index 86637ef..cca6978 100644 --- a/target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch +++ b/target/linux/brcm63xx/patches-3.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch @@ -79,7 +79,7 @@ Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318 #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -1661,6 +1661,17 @@ +@@ -1662,6 +1662,17 @@ * _REG relative to RSET_PCIE *************************************************************************/ @@ -97,7 +97,7 @@ Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318 #define PCIE_CONFIG2_REG 0x408 #define CONFIG2_BAR1_SIZE_EN 1 #define CONFIG2_BAR1_SIZE_MASK 0xf -@@ -1706,7 +1717,54 @@ +@@ -1707,7 +1718,54 @@ #define PCIE_RC_INT_C (1 << 2) #define PCIE_RC_INT_D (1 << 3) |