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authorJonas Gorski <jogo@openwrt.org>2012-07-03 21:42:07 +0000
committerJonas Gorski <jogo@openwrt.org>2012-07-03 21:42:07 +0000
commit988147111c71cc07c0e2080424c201cd4ded7150 (patch)
tree2eeb1f97cbeb70163455c72422cc716ffc9be84c /target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch
parent1e2262df76cd989b22ed1ff7d5bf21bdb00a6bb6 (diff)
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bcm63xx: update patches to latest upstream versions
SVN-Revision: 32591
Diffstat (limited to 'target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch53
1 files changed, 53 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch b/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch
new file mode 100644
index 0000000..e45a0d1
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch
@@ -0,0 +1,53 @@
+From a9168d99658bd050e49afc06880d140e2fc2c231 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 12 Jun 2012 10:23:40 +0200
+Subject: [PATCH 3/8] MIPS: BCM63XX: Use the Chip ID register for identifying the SoC
+
+Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
+revision bits. But since they all have the Chip ID register at the same
+location, we can use that to identify the SoC we are running on.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3955/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/cpu.c | 20 ++++++++++++--------
+ 1 files changed, 12 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void)
+ bcm63xx_irqs = bcm6345_irqs;
+ break;
+ case CPU_BMIPS4350:
+- switch (read_c0_prid() & 0xf0) {
+- case 0x10:
++ if ((read_c0_prid() & 0xf0) == 0x10) {
+ expected_cpu_id = BCM6358_CPU_ID;
+ bcm63xx_regs_base = bcm6358_regs_base;
+ bcm63xx_irqs = bcm6358_irqs;
+- break;
+- case 0x30:
+- expected_cpu_id = BCM6368_CPU_ID;
+- bcm63xx_regs_base = bcm6368_regs_base;
+- bcm63xx_irqs = bcm6368_irqs;
+- break;
++ } else {
++ /* all newer chips have the same chip id location */
++ u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
++
++ switch (chip_id) {
++ case BCM6368_CPU_ID:
++ expected_cpu_id = BCM6368_CPU_ID;
++ bcm63xx_regs_base = bcm6368_regs_base;
++ bcm63xx_irqs = bcm6368_irqs;
++ break;
++ }
+ }
+ break;
+ }