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authorJonas Gorski <jogo@openwrt.org>2013-04-23 13:55:36 +0000
committerJonas Gorski <jogo@openwrt.org>2013-04-23 13:55:36 +0000
commit90986b5581772a3767f5af2cadbde7310a3df296 (patch)
tree5a83f720d472bd1e039b021f92b9ff552d16cbe2 /target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch
parent2a1a16d2d55b02dd145db1be84999b88895595e5 (diff)
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bcm63xx: update patches with upstream submissions
SVN-Revision: 36407
Diffstat (limited to 'target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch57
1 files changed, 57 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch
new file mode 100644
index 0000000..27a411d
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.8/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch
@@ -0,0 +1,57 @@
+From 5da349ee614f61a2e6edb403098f40c6d40f2553 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 5 Jul 2012 21:19:20 +0200
+Subject: [PATCH 5/7] MIPS: BCM63XX: enable SPI controller for BCM6362
+
+The SPI controller shares the same register layout as the 6358 one.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c | 2 ++
+ arch/mips/bcm63xx/dev-spi.c | 4 ++--
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 3 ++-
+ 3 files changed, 6 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -202,6 +202,8 @@ static void spi_set(struct clk *clk, int
+ mask = CKCTL_6348_SPI_EN;
+ else if (BCMCPU_IS_6358())
+ mask = CKCTL_6358_SPI_EN;
++ else if (BCMCPU_IS_6362())
++ mask = CKCTL_6362_SPI_EN;
+ else
+ /* BCMCPU_IS_6368 */
+ mask = CKCTL_6368_SPI_EN;
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
+ {
+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
+ bcm63xx_regs_spi = bcm6348_regs_spi;
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
++ if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ bcm63xx_regs_spi = bcm6358_regs_spi;
+ }
+ #else
+@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
+ spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
+ }
+
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
++ if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
+ spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+ spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+ spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+@@ -74,7 +74,8 @@ static inline unsigned long bcm63xx_spir
+ #if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
+ __GEN_SPI_RSET(6348)
+ #endif
+-#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)
++#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
++ defined(CONFIG_BCM63XX_CPU_6368)
+ __GEN_SPI_RSET(6358)
+ #endif
+ #endif