diff options
| author | Jonas Gorski <jogo@openwrt.org> | 2013-05-19 18:32:13 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2013-05-19 18:32:13 +0000 |
| commit | 0a62b7c1484ee963726ffab11a86da4b2fe35a46 (patch) | |
| tree | 6b553a9636a4b125e04e7ef6942d889c0dcbdd6c /target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch | |
| parent | 1f4e5f77a0d5bc3cce01c501409ccfdce08b0382 (diff) | |
| download | mtk-20170518-0a62b7c1484ee963726ffab11a86da4b2fe35a46.zip mtk-20170518-0a62b7c1484ee963726ffab11a86da4b2fe35a46.tar.gz mtk-20170518-0a62b7c1484ee963726ffab11a86da4b2fe35a46.tar.bz2 | |
bcm63xx: add 3.9 support
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 36660
Diffstat (limited to 'target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch new file mode 100644 index 0000000..3c5b119 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch @@ -0,0 +1,56 @@ +From ec6f1e53b22d01e628b79b99f7a33960034e97e7 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Mon, 21 Nov 2011 00:53:26 +0100 +Subject: [PATCH 6/7] MIPS: BCM63XX: enable pcie for BCM6362 + +The PCIe controller is almost the same as the BCM6328 one, with only +the SERDES register being at a different location. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 ++- + arch/mips/pci/pci-bcm63xx.c | 11 +++++++++-- + 2 files changed, 11 insertions(+), 3 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1365,7 +1365,8 @@ + /************************************************************************* + * _REG relative to RSET_MISC + *************************************************************************/ +-#define MISC_SERDES_CTRL_REG 0x0 ++#define MISC_SERDES_CTRL_6328_REG 0x0 ++#define MISC_SERDES_CTRL_6362_REG 0x4 + #define SERDES_PCIE_EN (1 << 0) + #define SERDES_PCIE_EXD_EN (1 << 15) + +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -121,11 +121,17 @@ void __iomem *pci_iospace_start; + static void __init bcm63xx_reset_pcie(void) + { + u32 val; ++ u32 reg; + + /* enable SERDES */ +- val = bcm_misc_readl(MISC_SERDES_CTRL_REG); ++ if (BCMCPU_IS_6328()) ++ reg = MISC_SERDES_CTRL_6328_REG; ++ else ++ reg = MISC_SERDES_CTRL_6362_REG; ++ ++ val = bcm_misc_readl(reg); + val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; +- bcm_misc_writel(val, MISC_SERDES_CTRL_REG); ++ bcm_misc_writel(val, reg); + + /* reset the PCIe core */ + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); +@@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void) + + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: ++ case BCM6362_CPU_ID: + return bcm63xx_register_pcie(); + case BCM6348_CPU_ID: + case BCM6358_CPU_ID: |