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| author | Jonas Gorski <jonas.gorski@gmail.com> | 2018-01-13 18:43:32 +0100 |
|---|---|---|
| committer | Jonas Gorski <jonas.gorski@gmail.com> | 2018-02-11 23:15:05 +0100 |
| commit | 1ba38f6100243b263fc0d147cd59e76c1ad87a61 (patch) | |
| tree | 34cdc616d8ba5a02565b7fecdd9401b1f6329718 /target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch | |
| parent | 592472f60f7b79e824ce91a57b52976c5f174f28 (diff) | |
| download | mtk-20170518-1ba38f6100243b263fc0d147cd59e76c1ad87a61.zip mtk-20170518-1ba38f6100243b263fc0d147cd59e76c1ad87a61.tar.gz mtk-20170518-1ba38f6100243b263fc0d147cd59e76c1ad87a61.tar.bz2 | |
brcm63xx: add kernel 4.14 support
Add support for kernel 4.14. Increases compressed kernel size by ~64k
compared to 4.9.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Diffstat (limited to 'target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000..57af836 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.14/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,23 @@ +From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field + +Some SoC have a variant id field in the chip id register. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -10,6 +10,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 12 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + |