cns3xxx: update to linux 3.10

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 41917

5 files changed, 227 insertions, 234 deletions

diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
index c02a382..b1155ef 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
@@ -20,77 +20,68 @@
  * R10 - DMA Direction
  * R11 - DMA type
  * R12 - fiq_buffer Address
- * R13 - DMA type Address
 */
 
 	.global	cns3xxx_fiq_end
 ENTRY(cns3xxx_fiq_start)
-	mov r8, #0
-	str r8, [r13]
+	str	r8, [r13]
 
-	ldr r9, [r12]
-	ldr r8, [r9]
-	add r8, r8, #1
-	str r8, [r9]
-
-	ldmib r12, {r8, r9, r10}
-	and r11, r10, #0x3000000
-	and r10, r10, #0xff
-
-	teq r11, #0x1000000
-	beq cns3xxx_dma_map_area
-	teq r11, #0x2000000
-	beq cns3xxx_dma_unmap_area
-	b cns3xxx_dma_flush_range
-
-cns3xxx_fiq_exit:
-	mov r8, #0
-	str r8, [r12, #12]
-	mcr p15, 0, r8, c7, c10, 4    @ drain write buffer
-	subs pc, lr, #4
-
-cns3xxx_dma_map_area:
-	add r9, r9, r8
-	teq r10, #DMA_FROM_DEVICE
-	beq cns3xxx_dma_inv_range
-	b cns3xxx_dma_clean_range
-
-cns3xxx_dma_unmap_area:
-	add r9, r9, r8
-	teq r10, #DMA_TO_DEVICE
-	bne cns3xxx_dma_inv_range
-	b cns3xxx_fiq_exit
+	ldmia	r12, {r8, r9, r10}
+	and	r11, r10, #0x3000000
+	and	r10, r10, #0xff
 
+	teq	r11, #0x1000000
+	beq	cns3xxx_dma_map_area
+	teq	r11, #0x2000000
+	beq	cns3xxx_dma_unmap_area
+	/* fall through */
 cns3xxx_dma_flush_range:
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-	mcr p15, 0, r8, c7, c14, 1   @ clean & invalidate D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c14, 1		@ clean & invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	/* fall through */
+cns3xxx_fiq_exit:
+	mov	r8, #0
+	str	r8, [r12, #8]
+	mcr	p15, 0, r8, c7, c10, 4		@ drain write buffer
+	subs	pc, lr, #4
 
+cns3xxx_dma_map_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_FROM_DEVICE
+	beq	cns3xxx_dma_inv_range
+	teq	r10, #DMA_TO_DEVICE
+	bne	cns3xxx_dma_flush_range
+	/* fall through */
 cns3xxx_dma_clean_range:
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-	mcr p15, 0, r8, c7, c10, 1    @ clean D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c10, 1		@ clean D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	cns3xxx_fiq_exit
 
+cns3xxx_dma_unmap_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_TO_DEVICE
+	beq	cns3xxx_fiq_exit
+	/* fall through */
 cns3xxx_dma_inv_range:
-	tst r8, #D_CACHE_LINE_SIZE - 1
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
-	mcrne p15, 0, r8, c7, c10, 1    @ clean D line
-	tst r9, #D_CACHE_LINE_SIZE - 1
-	bic r9, r9, #D_CACHE_LINE_SIZE - 1
-	mcrne p15, 0, r9, c7, c14, 1    @ clean & invalidate D line
+	tst	r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r8, c7, c10, 1		@ clean D line
+	tst	r9, #D_CACHE_LINE_SIZE - 1
+	bic	r9, r9, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r9, c7, c14, 1		@ clean & invalidate D line
 1:
-	mcr p15, 0, r8, c7, c6, 1   @ invalidate D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c6, 1		@ invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	cns3xxx_fiq_exit
 
 cns3xxx_fiq_end:
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
index 4f5d500..35434f8 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
@@ -141,8 +142,6 @@ static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 	struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
-	struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
-	struct irq_chip_type *ct = gc->chip_types;
 	u16 i;
 	u32 reg;
 
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h
deleted file mode 100644
index f286d0d..0000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-cns3xxx/include/mach/platform.h
- *
- * Copyright 2011 Gateworks Corporation
- *		  Chris Lang <clang@gateworks.com
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
-
-#ifndef __ASSEMBLY__
-
-/* Information about built-in Ethernet MAC interfaces */
-struct cns3xxx_plat_info {
-	u8 ports; /* Bitmap of enabled Ports */
-	u8 hwaddr[4][6];
-	u32 phy[3];
-};
-
-#endif /* __ASM_ARCH_PLATFORM_H */
-#endif
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
index 4903749..9021f3d 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
@@ -39,19 +39,19 @@
 #include <linux/pps-gpio.h>
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/platform_data/cns3xxx.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/platform.h>
-#include <mach/pm.h>
 #include <mach/gpio.h>
-#include <asm/hardware/gic.h>
 #include "core.h"
 #include "devices.h"
+#include "cns3xxx.h"
+#include "pm.h"
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
@@ -192,8 +192,16 @@ static struct spi_board_info __initdata laguna_spi_devices[] = {
 	},
 };
 
+static struct resource laguna_spi_resource = {
+	.start    = CNS3XXX_SSP_BASE + 0x40,
+	.end      = CNS3XXX_SSP_BASE + 0x6f,
+	.flags    = IORESOURCE_MEM,
+};
+
 static struct platform_device laguna_spi_controller = {
 	.name = "cns3xxx_spi",
+	.resource = &laguna_spi_resource,
+	.num_resources = 1,
 };
 
 /*
@@ -314,9 +322,30 @@ static struct cns3xxx_plat_info laguna_net_data = {
 	},
 };
 
+static struct resource laguna_net_resource[] = {
+	{
+		.name = "eth0_mem",
+		.start = CNS3XXX_SWITCH_BASE,
+		.end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM
+	}, {
+		.name = "eth_rx",
+		.start = IRQ_CNS3XXX_SW_R0RXC,
+		.end = IRQ_CNS3XXX_SW_R0RXC,
+		.flags = IORESOURCE_IRQ
+	}, {
+		.name = "eth_stat",
+		.start = IRQ_CNS3XXX_SW_STATUS,
+		.end = IRQ_CNS3XXX_SW_STATUS,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
 static struct platform_device laguna_net_device = {
 	.name = "cns3xxx_eth",
 	.id = 0,
+	.resource = laguna_net_resource,
+	.num_resources = ARRAY_SIZE(laguna_net_resource),
 	.dev.platform_data = &laguna_net_data,
 };
 
@@ -361,29 +390,26 @@ static struct resource laguna_uart_resources[] = {
 
 static struct plat_serial8250_port laguna_uart_data[] = {
 	{
-		.membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART0_BASE),
 		.irq            = IRQ_CNS3XXX_UART0,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
 	},{
-		.membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART1_BASE),
 		.irq            = IRQ_CNS3XXX_UART1,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
 	},{
-		.membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART2_BASE),
 		.irq            = IRQ_CNS3XXX_UART2,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
@@ -526,7 +552,7 @@ static struct platform_device cns3xxx_usb_otg_device = {
 static struct resource laguna_i2c_resource[] = {
 	{
 		.start    = CNS3XXX_SSP_BASE + 0x20,
-		.end      = 0x7100003f,
+		.end      = CNS3XXX_SSP_BASE + 0x3f,
 		.flags    = IORESOURCE_MEM,
 	},{
 		.start    = IRQ_CNS3XXX_I2C,
@@ -771,10 +797,37 @@ static struct gpio laguna_gpio_gw2380[] = {
  */
 static void __init laguna_init(void)
 {
+	struct clk *clk;
+	u32 __iomem *reg;
+
+	clk = clk_register_fixed_rate(NULL, "cpu", NULL,
+				      CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+				      cns3xxx_cpu_clock() * (1000000 / 8));
+	clk_register_clkdev(clk, "cpu", NULL);
+
 	platform_device_register(&laguna_watchdog);
 
 	platform_device_register(&laguna_i2c_controller);
 
+	/* Set ext_int 0-3 drive strength to 21 mA */
+	reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
+	*reg |= 0x300;
+
+	/* Enable SCL/SDA for I2C */
+	reg = MISC_GPIOB_PIN_ENABLE_REG;
+	*reg |= BIT(12) | BIT(13);
+
+	/* Enable MMC/SD pins */
+	reg = MISC_GPIOA_PIN_ENABLE_REG;
+	*reg |= 0xf80;
+
+	cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+	cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+	cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+
+	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
+	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
+
 	i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
 
 	pm_power_off = cns3xxx_power_off;
@@ -786,22 +839,12 @@ static struct map_desc laguna_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(CNS3XXX_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	},{
-		.virtual	= CNS3XXX_UART1_BASE_VIRT,
-		.pfn		= __phys_to_pfn(CNS3XXX_UART1_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	},{
-		.virtual	= CNS3XXX_UART2_BASE_VIRT,
-		.pfn		= __phys_to_pfn(CNS3XXX_UART2_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
 	},
 };
 
 static void __init laguna_map_io(void)
 {
-	cns3xxx_common_init();
+	cns3xxx_map_io();
 	cns3xxx_pcie_iotable_init();
 	iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
 	laguna_early_serial_setup();
@@ -1022,11 +1065,11 @@ static int __init laguna_model_setup(void)
 late_initcall(laguna_model_setup);
 
 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
+	.smp		= smp_ops(cns3xxx_smp_ops),
 	.atag_offset	= 0x100,
 	.map_io		= laguna_map_io,
 	.init_irq	= cns3xxx_init_irq,
-	.timer		= &cns3xxx_timer,
-	.handle_irq	= gic_handle_irq,
+	.init_time	= cns3xxx_timer_init,
 	.init_machine	= laguna_init,
 	.restart	= cns3xxx_restart,
 MACHINE_END
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
index 77ac97a..5359885 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
@@ -21,46 +21,61 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 #include <asm/fiq.h>
 #include <mach/smp.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 
 static struct fiq_handler fh = {
 	.name = "cns3xxx-fiq"
 };
 
-static unsigned int fiq_buffer[8];
+struct fiq_req {
+	union {
+		struct {
+			const void *addr;
+			size_t size;
+		} map;
+		struct {
+			const void *addr;
+			size_t size;
+		} unmap;
+		struct {
+			const void *start;
+			const void *end;
+		} flush;
+	};
+	volatile uint flags;
+	void __iomem *reg;
+} ____cacheline_aligned;
+
+extern unsigned int fiq_number[2];
+
+DEFINE_PER_CPU(struct fiq_req, fiq_data);
 
 #define FIQ_ENABLED         0x80000000
-#define FIQ_GENERATE				0x00010000
+#define FIQ_GENERATE        0x00010000
 #define CNS3XXX_MAP_AREA    0x01000000
 #define CNS3XXX_UNMAP_AREA  0x02000000
 #define CNS3XXX_FLUSH_RANGE 0x03000000
 
 extern void cns3xxx_secondary_startup(void);
 extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-extern unsigned int fiq_number[2];
-extern struct cpu_cache_fns cpu_cache;
-struct cpu_cache_fns cpu_cache_save;
 
 #define SCU_CPU_STATUS 0x08
 static void __iomem *scu_base;
 
-static void __init cns3xxx_set_fiq_regs(void)
+static inline void __cpuinit cns3xxx_set_fiq_regs(unsigned int cpu)
 {
 	struct pt_regs FIQ_regs;
-	unsigned int cpu = smp_processor_id();
-
-	if (cpu) {
-		FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
-		FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
-	} else {
-		FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
-		FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
-	}
+	struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
+
+	FIQ_regs.ARM_r8 = 0;
+	FIQ_regs.ARM_ip = (unsigned int)fiq_req;
+	FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
+	fiq_req->reg = MISC_FIQ_CPU(!cpu);
+
 	set_fiq_regs(&FIQ_regs);
 }
 
@@ -74,16 +89,10 @@ static void __init cns3xxx_init_fiq(void)
 	fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
 
 	ret = claim_fiq(&fh);
-
-	if (ret) {
+	if (ret)
 		return;
-	}
 
 	set_fiq_handler(fiqhandler_start, fiqhandler_length);
-	fiq_buffer[0] = (unsigned int)&fiq_number[0];
-	fiq_buffer[3] = 0;
-	fiq_buffer[4] = (unsigned int)&fiq_number[1];
-	fiq_buffer[7] = 0;
 }
 
 
@@ -105,16 +114,9 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * Setup Secondary Core FIQ regs
 	 */
-	cns3xxx_set_fiq_regs();
+	cns3xxx_set_fiq_regs(1);
 
 	/*
 	 * let the primary processor know we're out of the
@@ -123,14 +125,6 @@ static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
 	write_pen_release(-1);
 
 	/*
-	 * Fixup DMA Operations
-	 *
-	 */
-	cpu_cache.dma_map_area = (void *)smp_dma_map_area;
-	cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
-	cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
-
-	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
@@ -162,7 +156,7 @@ static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-	gic_raise_softirq(cpumask_of(cpu), 1);
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
 
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
@@ -204,8 +198,6 @@ static void __init cns3xxx_smp_init_cpus(void)
 			break;
 	}
 	ncores = i;
-
-	set_smp_cross_call(gic_raise_softirq);
 }
 
 static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
@@ -238,111 +230,105 @@ static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
 	 * Setup FIQ's for main cpu
 	 */
 	cns3xxx_init_fiq();
-	cns3xxx_set_fiq_regs();
-	memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
+	cns3xxx_set_fiq_regs(0);
 }
 
+extern void v6_dma_map_area(const void *, size_t, int);
+extern void v6_dma_unmap_area(const void *, size_t, int);
+extern void v6_dma_flush_range(const void *, const void *);
+extern void v6_flush_kern_dcache_area(void *, size_t);
 
-static inline unsigned long cns3xxx_cpu_id(void)
+void fiq_dma_map_area(const void *addr, size_t size, int dir)
 {
-	unsigned long cpu;
-
-	asm volatile(
-		" mrc p15, 0, %0, c0, c0, 5  @ cns3xxx_cpu_id\n"
-		: "=r" (cpu) : : "memory", "cc");
-	return (cpu & 0xf);
-}
-
-void smp_dma_map_area(const void *addr, size_t size, int dir)
-{
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
+
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-		fiq_buffer[1] = (unsigned int)addr;
-		fiq_buffer[2] = size;
-		fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_map_area(addr, size, dir);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)addr;
-		fiq_buffer[6] = size;
-		fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_map_area(addr, size, dir);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_map_area(addr, size, dir);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->map.addr = addr;
+	req->map.size = size;
+	req->flags = dir | CNS3XXX_MAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_map_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
-void smp_dma_unmap_area(const void *addr, size_t size, int dir)
+void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
 {
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
 
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-
-		fiq_buffer[1] = (unsigned int)addr;
-		fiq_buffer[2] = size;
-		fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_unmap_area(addr, size, dir);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)addr;
-		fiq_buffer[6] = size;
-		fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_unmap_area(addr, size, dir);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_unmap_area(addr, size, dir);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->unmap.addr = addr;
+	req->unmap.size = size;
+	req->flags = dir | CNS3XXX_UNMAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_unmap_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
-void smp_dma_flush_range(const void *start, const void *end)
+void fiq_dma_flush_range(const void *start, const void *end)
 {
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
+
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-
-		fiq_buffer[1] = (unsigned int)start;
-		fiq_buffer[2] = (unsigned int)end;
-		fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_flush_range(start, end);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)start;
-		fiq_buffer[6] = (unsigned int)end;
-		fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_flush_range(start, end);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_flush_range(start, end);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+
+	req->flush.start = start;
+	req->flush.end = end;
+	req->flags = CNS3XXX_FLUSH_RANGE;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_flush_range(start, end);
+
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
+void fiq_flush_kern_dcache_area(void *addr, size_t size)
+{
+	fiq_dma_flush_range(addr, addr + size);
+}
+
 struct smp_operations cns3xxx_smp_ops __initdata = {
 	.smp_init_cpus      = cns3xxx_smp_init_cpus,
 	.smp_prepare_cpus   = cns3xxx_smp_prepare_cpus,