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authorFelix Fietkau <nbd@openwrt.org>2012-10-10 11:38:58 +0000
committerFelix Fietkau <nbd@openwrt.org>2012-10-10 11:38:58 +0000
commit6bb7409e5a85da6ae3323ec179311a99d0de79e5 (patch)
treeedb4cf3e11e3af7964098ca779d6ed1120476954 /target/linux/cns3xxx
parentc6d2712db35b3bf24a5ecb02a8b6f650c0e3486d (diff)
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cns3xxx: Fix laguna arm11mpcore watchdog
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where all mpcore-wdt boards point the driver base too. I believe this is wrong because 0x600 is aliased to the timer/watchdog of the 'current CPU' where 0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus if your timer/watchdog application is switching between CPU's it can end up writing to the wrong CPU's registers which results in random board resets from watchdog timeouts etc. This patch forces the timer/watchdog driver to use CPU0's registers always. Its my opinion that other mpcore-wdt boards should be doing the same thing. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 33683
Diffstat (limited to 'target/linux/cns3xxx')
-rw-r--r--target/linux/cns3xxx/patches-3.3/300-laguna_support.patch2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
index 7fe970a..a4602f9 100644
--- a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
+++ b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
@@ -563,7 +563,7 @@
+
+static struct resource laguna_watchdog_resources[] = {
+ [0] = {
-+ .start = CNS3XXX_TC11MP_TWD_BASE,
++ .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },