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| author | Felix Fietkau <nbd@openwrt.org> | 2014-07-10 21:11:02 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2014-07-10 21:11:02 +0000 |
| commit | a17a58e310e41829a634ac507477a0f6457a65d0 (patch) | |
| tree | 35a4ed66e80e43de424f0c8de9904a820545ed0e /target/linux/generic/files | |
| parent | 9c51ab13d386497081de772ba5689cacc13e7b4d (diff) | |
| download | mtk-20170518-a17a58e310e41829a634ac507477a0f6457a65d0.zip mtk-20170518-a17a58e310e41829a634ac507477a0f6457a65d0.tar.gz mtk-20170518-a17a58e310e41829a634ac507477a0f6457a65d0.tar.bz2 | |
ar8216: disable EEE by default on AR8327 to fix stability issues (#14597)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 41577
Diffstat (limited to 'target/linux/generic/files')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.c | 9 | ||||
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.h | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c index 3f60878..fe0ddb9 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -1626,6 +1626,15 @@ ar8327_init_globals(struct ar8xxx_priv *priv) /* Enable MIB counters */ ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB); + + /* Disable EEE on all ports due to stability issues */ + t = priv->read(priv, AR8327_REG_EEE_CTRL); + t |= AR8327_EEE_CTRL_DISABLE_PHY(0) | + AR8327_EEE_CTRL_DISABLE_PHY(1) | + AR8327_EEE_CTRL_DISABLE_PHY(2) | + AR8327_EEE_CTRL_DISABLE_PHY(3) | + AR8327_EEE_CTRL_DISABLE_PHY(4); + priv->write(priv, AR8327_REG_EEE_CTRL, t); } static void diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index 00d6d7f..eb553b4 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -366,6 +366,9 @@ #define AR8327_SGMII_CTRL_EN_RX BIT(2) #define AR8327_SGMII_CTRL_EN_TX BIT(3) +#define AR8327_REG_EEE_CTRL 0x100 +#define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) + #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) #define AR8327_PORT_VLAN0_DEF_SVID_S 0 |