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author | Felix Fietkau <nbd@openwrt.org> | 2012-06-16 21:06:33 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2012-06-16 21:06:33 +0000 |
commit | 50958f5e03071cab154344d0f2e3c03c12bc250e (patch) | |
tree | 6818a2dfbef3f2e9180ca3d48f06f66721b176b2 /target/linux/generic/patches-3.3 | |
parent | a5e2890ecbd5953370e37e131ac3da6b64c532b0 (diff) | |
download | mtk-20170518-50958f5e03071cab154344d0f2e3c03c12bc250e.zip mtk-20170518-50958f5e03071cab154344d0f2e3c03c12bc250e.tar.gz mtk-20170518-50958f5e03071cab154344d0f2e3c03c12bc250e.tar.bz2 |
kernel: replace the brcm47xx fuse workaround patches with a generic patch that applies to all mips targets
The dcache bug that it works around is a generic issue, not a brcm47xx cache quirk
SVN-Revision: 32395
Diffstat (limited to 'target/linux/generic/patches-3.3')
-rw-r--r-- | target/linux/generic/patches-3.3/309-mips_fuse_workaround.patch | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.3/309-mips_fuse_workaround.patch b/target/linux/generic/patches-3.3/309-mips_fuse_workaround.patch new file mode 100644 index 0000000..78ab64f --- /dev/null +++ b/target/linux/generic/patches-3.3/309-mips_fuse_workaround.patch @@ -0,0 +1,32 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -39,6 +39,7 @@ void (*__flush_kernel_vmap_range)(unsign + void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); + + EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); ++EXPORT_SYMBOL(__flush_cache_all); + + /* MIPS specific cache operations */ + void (*flush_cache_sigtramp)(unsigned long addr); +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -19,6 +19,9 @@ + #include <linux/pipe_fs_i.h> + #include <linux/swap.h> + #include <linux/splice.h> ++#ifdef CONFIG_MIPS ++#include <asm/cacheflush.h> ++#endif + + MODULE_ALIAS_MISCDEV(FUSE_MINOR); + MODULE_ALIAS("devname:fuse"); +@@ -655,6 +658,9 @@ static int fuse_copy_fill(struct fuse_co + static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) + { + unsigned ncpy = min(*size, cs->len); ++#ifdef CONFIG_MIPS ++ __flush_cache_all(); ++#endif + if (val) { + if (cs->write) + memcpy(cs->buf, *val, ncpy); |