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authorJohn Crispin <john@openwrt.org>2007-12-22 00:17:22 +0000
committerJohn Crispin <john@openwrt.org>2007-12-22 00:17:22 +0000
commit7af3296c76f4e3f7f564a4b195f283841e0978d9 (patch)
treedccc547dc41fd3b11647857aa364108fc79a7cbe /target/linux/ifxmips/files/drivers
parent285395cfca2b9ae3c9400177938c47874281e1c0 (diff)
downloadmtk-20170518-7af3296c76f4e3f7f564a4b195f283841e0978d9.zip
mtk-20170518-7af3296c76f4e3f7f564a4b195f283841e0978d9.tar.gz
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change danube 2 ifxmips
SVN-Revision: 9821
Diffstat (limited to 'target/linux/ifxmips/files/drivers')
-rw-r--r--target/linux/ifxmips/files/drivers/char/danube_gpio.c130
-rw-r--r--target/linux/ifxmips/files/drivers/char/danube_led.c52
-rw-r--r--target/linux/ifxmips/files/drivers/char/danube_ssc.c26
-rw-r--r--target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c96
-rw-r--r--target/linux/ifxmips/files/drivers/mtd/maps/danube.c18
-rw-r--r--target/linux/ifxmips/files/drivers/net/danube_mii0.c32
-rw-r--r--target/linux/ifxmips/files/drivers/serial/danube_asc.c126
7 files changed, 240 insertions, 240 deletions
diff --git a/target/linux/ifxmips/files/drivers/char/danube_gpio.c b/target/linux/ifxmips/files/drivers/char/danube_gpio.c
index dbdb71e..2a42665 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_gpio.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_gpio.c
@@ -38,12 +38,12 @@ static unsigned int danube_gpio_major = 0;
static struct semaphore port_sem;
/* TODO do we really need this ? return in a define is forbidden by coding style */
-#define DANUBE_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
+#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
danube_port_reserve_pin (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(danube_port_reserve_pin);
int
danube_port_free_pin (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@@ -63,8 +63,8 @@ EXPORT_SYMBOL(danube_port_free_pin);
int
danube_port_set_open_drain (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OD);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@@ -73,8 +73,8 @@ EXPORT_SYMBOL(danube_port_set_open_drain);
int
danube_port_clear_open_drain (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OD);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@@ -83,8 +83,8 @@ EXPORT_SYMBOL(danube_port_clear_open_drain);
int
danube_port_set_pudsel (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDSEL);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@@ -93,8 +93,8 @@ EXPORT_SYMBOL(danube_port_set_pudsel);
int
danube_port_clear_pudsel (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDSEL);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@@ -103,8 +103,8 @@ EXPORT_SYMBOL(danube_port_clear_pudsel);
int
danube_port_set_puden (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDEN);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@@ -113,8 +113,8 @@ EXPORT_SYMBOL(danube_port_set_puden);
int
danube_port_clear_puden (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDEN);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@@ -123,8 +123,8 @@ EXPORT_SYMBOL(danube_port_clear_puden);
int
danube_port_set_stoff (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_STOFF);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@@ -133,8 +133,8 @@ EXPORT_SYMBOL(danube_port_set_stoff);
int
danube_port_clear_stoff (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_STOFF);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@@ -143,8 +143,8 @@ EXPORT_SYMBOL(danube_port_clear_stoff);
int
danube_port_set_dir_out (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_DIR);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@@ -153,8 +153,8 @@ EXPORT_SYMBOL(danube_port_set_dir_out);
int
danube_port_set_dir_in (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_DIR);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@@ -163,8 +163,8 @@ EXPORT_SYMBOL(danube_port_set_dir_in);
int
danube_port_set_output (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OUT);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@@ -173,8 +173,8 @@ EXPORT_SYMBOL(danube_port_set_output);
int
danube_port_clear_output (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OUT);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@@ -183,9 +183,9 @@ EXPORT_SYMBOL(danube_port_clear_output);
int
danube_port_get_input (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
- if (readl(DANUBE_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
+ if (readl(IFXMIPS_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
return 0;
else
return 1;
@@ -195,8 +195,8 @@ EXPORT_SYMBOL(danube_port_get_input);
int
danube_port_set_altsel0 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@@ -205,8 +205,8 @@ EXPORT_SYMBOL(danube_port_set_altsel0);
int
danube_port_clear_altsel0 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@@ -215,8 +215,8 @@ EXPORT_SYMBOL(danube_port_clear_altsel0);
int
danube_port_set_altsel1 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@@ -225,8 +225,8 @@ EXPORT_SYMBOL(danube_port_set_altsel1);
int
danube_port_clear_altsel1 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@@ -264,24 +264,24 @@ danube_port_read_procmem (char *buf, char **start, off_t offset, int count,
len += sprintf (buf + len,
"----------------------------------------\n");
- len += danube_port_read_procmem_helper("P0-OUT", DANUBE_GPIO_P0_OUT, &buf[len]);
- len += danube_port_read_procmem_helper("P1-OUT", DANUBE_GPIO_P1_OUT, &buf[len]);
- len += danube_port_read_procmem_helper("P0-IN ", DANUBE_GPIO_P0_IN, &buf[len]);
- len += danube_port_read_procmem_helper("P1-IN ", DANUBE_GPIO_P1_IN, &buf[len]);
- len += danube_port_read_procmem_helper("P0-DIR", DANUBE_GPIO_P0_DIR, &buf[len]);
- len += danube_port_read_procmem_helper("P1-DIR", DANUBE_GPIO_P1_DIR, &buf[len]);
- len += danube_port_read_procmem_helper("P0-STO ", DANUBE_GPIO_P0_STOFF, &buf[len]);
- len += danube_port_read_procmem_helper("P1-STO ", DANUBE_GPIO_P1_STOFF, &buf[len]);
- len += danube_port_read_procmem_helper("P0-PUDE", DANUBE_GPIO_P0_PUDEN, &buf[len]);
- len += danube_port_read_procmem_helper("P1-PUDE", DANUBE_GPIO_P1_PUDEN, &buf[len]);
- len += danube_port_read_procmem_helper("P0-OD ", DANUBE_GPIO_P0_OD, &buf[len]);
- len += danube_port_read_procmem_helper("P1-OD ", DANUBE_GPIO_P1_OD, &buf[len]);
- len += danube_port_read_procmem_helper("P0-PUDS", DANUBE_GPIO_P0_PUDSEL, &buf[len]);
- len += danube_port_read_procmem_helper("P1-PUDS", DANUBE_GPIO_P1_PUDSEL, &buf[len]);
- len += danube_port_read_procmem_helper("P0-ALT0", DANUBE_GPIO_P0_ALTSEL0, &buf[len]);
- len += danube_port_read_procmem_helper("P1-ALT0", DANUBE_GPIO_P1_ALTSEL0, &buf[len]);
- len += danube_port_read_procmem_helper("P0-ALT1", DANUBE_GPIO_P0_ALTSEL1, &buf[len]);
- len += danube_port_read_procmem_helper("P1-ALT1", DANUBE_GPIO_P1_ALTSEL1, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-OUT", IFXMIPS_GPIO_P0_OUT, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-OUT", IFXMIPS_GPIO_P1_OUT, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-IN ", IFXMIPS_GPIO_P0_IN, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-IN ", IFXMIPS_GPIO_P1_IN, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-DIR", IFXMIPS_GPIO_P0_DIR, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-DIR", IFXMIPS_GPIO_P1_DIR, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-STO ", IFXMIPS_GPIO_P0_STOFF, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-STO ", IFXMIPS_GPIO_P1_STOFF, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-PUDE", IFXMIPS_GPIO_P0_PUDEN, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-PUDE", IFXMIPS_GPIO_P1_PUDEN, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-OD ", IFXMIPS_GPIO_P0_OD, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-OD ", IFXMIPS_GPIO_P1_OD, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-PUDS", IFXMIPS_GPIO_P0_PUDSEL, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-PUDS", IFXMIPS_GPIO_P1_PUDSEL, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-ALT0", IFXMIPS_GPIO_P0_ALTSEL0, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-ALT0", IFXMIPS_GPIO_P1_ALTSEL0, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-ALT1", IFXMIPS_GPIO_P0_ALTSEL1, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-ALT1", IFXMIPS_GPIO_P1_ALTSEL1, &buf[len]);
len = len + sprintf (buf + len, "\n\n");
*eof = 1;
@@ -308,7 +308,7 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
int ret = 0;
volatile struct danube_port_ioctl_parm parm;
- if (_IOC_TYPE (cmd) != DANUBE_PORT_IOC_MAGIC)
+ if (_IOC_TYPE (cmd) != IFXMIPS_PORT_IOC_MAGIC)
return -EINVAL;
if (_IOC_DIR (cmd) & _IOC_WRITE) {
@@ -330,63 +330,63 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
return -EBUSY;
switch (cmd) {
- case DANUBE_PORT_IOCOD:
+ case IFXMIPS_PORT_IOCOD:
if (parm.value == 0x00)
danube_port_clear_open_drain(parm.port, parm.pin);
else
danube_port_set_open_drain(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCPUDSEL:
+ case IFXMIPS_PORT_IOCPUDSEL:
if (parm.value == 0x00)
danube_port_clear_pudsel(parm.port, parm.pin);
else
danube_port_set_pudsel(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCPUDEN:
+ case IFXMIPS_PORT_IOCPUDEN:
if (parm.value == 0x00)
danube_port_clear_puden(parm.port, parm.pin);
else
danube_port_set_puden(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCSTOFF:
+ case IFXMIPS_PORT_IOCSTOFF:
if (parm.value == 0x00)
danube_port_clear_stoff(parm.port, parm.pin);
else
danube_port_set_stoff(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCDIR:
+ case IFXMIPS_PORT_IOCDIR:
if (parm.value == 0x00)
danube_port_set_dir_in(parm.port, parm.pin);
else
danube_port_set_dir_out(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCOUTPUT:
+ case IFXMIPS_PORT_IOCOUTPUT:
if (parm.value == 0x00)
danube_port_clear_output(parm.port, parm.pin);
else
danube_port_set_output(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCALTSEL0:
+ case IFXMIPS_PORT_IOCALTSEL0:
if (parm.value == 0x00)
danube_port_clear_altsel0(parm.port, parm.pin);
else
danube_port_set_altsel0(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCALTSEL1:
+ case IFXMIPS_PORT_IOCALTSEL1:
if (parm.value == 0x00)
danube_port_clear_altsel1(parm.port, parm.pin);
else
danube_port_set_altsel1(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCINPUT:
+ case IFXMIPS_PORT_IOCINPUT:
parm.value = danube_port_get_input(parm.port, parm.pin);
copy_to_user((void*)arg, (void*)&parm,
sizeof(struct danube_port_ioctl_parm));
diff --git a/target/linux/ifxmips/files/drivers/char/danube_led.c b/target/linux/ifxmips/files/drivers/char/danube_led.c
index 86a92d5..f1483cc 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_led.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_led.c
@@ -31,12 +31,12 @@
#include <asm/danube/danube_gpio.h>
#include <asm/danube/danube_pmu.h>
-#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
-//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
+#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
+//#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING
-#define DANUBE_LED_SPEED DANUBE_LED_8HZ
+#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ
-#define DANUBE_LED_GPIO_PORT 0
+#define IFXMIPS_LED_GPIO_PORT 0
static int danube_led_major;
@@ -44,7 +44,7 @@ void
danube_led_set (unsigned int led)
{
led &= 0xffffff;
- writel(readl(DANUBE_LED_CPU0) | led, DANUBE_LED_CPU0);
+ writel(readl(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_set);
@@ -52,7 +52,7 @@ void
danube_led_clear (unsigned int led)
{
led = ~(led & 0xffffff);
- writel(readl(DANUBE_LED_CPU0) & led, DANUBE_LED_CPU0);
+ writel(readl(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_clear);
@@ -60,7 +60,7 @@ void
danube_led_blink_set (unsigned int led)
{
led &= 0xffffff;
- writel(readl(DANUBE_LED_CON0) | led, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_set);
@@ -68,7 +68,7 @@ void
danube_led_blink_clear (unsigned int led)
{
led = ~(led & 0xffffff);
- writel(readl(DANUBE_LED_CON0) & led, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_clear);
@@ -80,10 +80,10 @@ danube_led_setup_gpio (void)
/* we need to setup pins SH,D,ST (4,5,6) */
for (i = 4; i < 7; i++)
{
- danube_port_set_altsel0(DANUBE_LED_GPIO_PORT, i);
- danube_port_clear_altsel1(DANUBE_LED_GPIO_PORT, i);
- danube_port_set_dir_out(DANUBE_LED_GPIO_PORT, i);
- danube_port_set_open_drain(DANUBE_LED_GPIO_PORT, i);
+ danube_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i);
}
}
@@ -144,32 +144,32 @@ danube_led_init (void)
danube_led_setup_gpio();
- writel(0, DANUBE_LED_AR);
- writel(0, DANUBE_LED_CPU0);
- writel(0, DANUBE_LED_CPU1);
- writel(LED_CON0_SWU, DANUBE_LED_CON0);
- writel(0, DANUBE_LED_CON1);
+ writel(0, IFXMIPS_LED_AR);
+ writel(0, IFXMIPS_LED_CPU0);
+ writel(0, IFXMIPS_LED_CPU1);
+ writel(LED_CON0_SWU, IFXMIPS_LED_CON0);
+ writel(0, IFXMIPS_LED_CON1);
/* setup the clock edge that the shift register is triggered on */
- writel(readl(DANUBE_LED_CON0) & ~DANUBE_LED_EDGE_MASK, DANUBE_LED_CON0);
- writel(readl(DANUBE_LED_CON0) | DANUBE_LED_CLK_EDGE, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
/* per default leds 15-0 are set */
- writel(DANUBE_LED_GROUP1 | DANUBE_LED_GROUP0, DANUBE_LED_CON1);
+ writel(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
/* leds are update periodically by the FPID */
- writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_UPD_MASK, DANUBE_LED_CON1);
- writel(readl(DANUBE_LED_CON1) | DANUBE_LED_UPD_SRC_FPI, DANUBE_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
/* set led update speed */
- writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_MASK, DANUBE_LED_CON1);
- writel(readl(DANUBE_LED_CON1) | DANUBE_LED_SPEED, DANUBE_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
/* adsl 0 and 1 leds are updated by the arc */
- writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
/* per default, the leds are turned on */
- danube_pmu_enable(DANUBE_PMU_PWDCR_LED);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
diff --git a/target/linux/ifxmips/files/drivers/char/danube_ssc.c b/target/linux/ifxmips/files/drivers/char/danube_ssc.c
index 1f90dac..c26b7bb 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_ssc.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_ssc.c
@@ -872,20 +872,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
/* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
/* Set p0.15 to alternative 01, others to 00 (In/OUT) */
- *(DANUBE_GPIO_P0_DIR) = (*DANUBE_GPIO_P0_DIR) | (0xA000);
- *(DANUBE_GPIO_P0_ALTSEL0) = (((*DANUBE_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
- *(DANUBE_GPIO_P0_ALTSEL1) = (((*DANUBE_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
- *(DANUBE_GPIO_P0_OD) = (*DANUBE_GPIO_P0_OD) | 0xA000;
+ *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
+ *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
+ *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
+ *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
/* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
- *(DANUBE_GPIO_P1_DIR) = ((*DANUBE_GPIO_P1_DIR) | (0x46)) & (~1);
- *(DANUBE_GPIO_P1_ALTSEL0) = ((*DANUBE_GPIO_P1_ALTSEL0) | (0x47));
- *(DANUBE_GPIO_P1_ALTSEL1) = (*DANUBE_GPIO_P1_ALTSEL1) & (~0x47);
- *(DANUBE_GPIO_P1_OD) = (*DANUBE_GPIO_P1_OD) | 0x0046;
+ *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
+ *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
+ *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
+ *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
/*CS3 */
/*TODO: CS4 CS5 CS6 */
- *DANUBE_GPIO_P0_OUT = ((*DANUBE_GPIO_P0_OUT) | 0x2000);
+ *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
local_irq_restore (flags);
@@ -1273,10 +1273,10 @@ ifx_ssc_init (void)
info->txbuf = NULL;
/* values specific to SSC1 */
if (i == 0) {
- info->mapbase = DANUBE_SSC1_BASE_ADDR;
- info->txirq = DANUBE_SSC_TIR;
- info->rxirq = DANUBE_SSC_RIR;
- info->errirq = DANUBE_SSC_EIR;
+ info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
+ info->txirq = IFXMIPS_SSC_TIR;
+ info->rxirq = IFXMIPS_SSC_RIR;
+ info->errirq = IFXMIPS_SSC_EIR;
}
WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
diff --git a/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c b/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
index be2b339..54885c1 100644
--- a/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
+++ b/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
@@ -43,8 +43,8 @@ danube_wdt_enable (unsigned int timeout)
int retval = 0;
/* clock divider & prewarning limit */
- wdt_clkdiv = 1 << (7 * DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR)));
- wdt_pwl = 0x8000 >> DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR));
+ wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR)));
+ wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR));
//TODO
printk("WARNING FUNCTION CALL MISSING!!!");
@@ -65,21 +65,21 @@ danube_wdt_enable (unsigned int timeout)
}
/* Write first part of password access */
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- wdt_cr &= (!DANUBE_BIU_WDT_CR_PW_SET(0xff) &
- !DANUBE_BIU_WDT_CR_PWL_SET(0x3) &
- !DANUBE_BIU_WDT_CR_CLKDIV_SET(0x3) &
- !DANUBE_BIU_WDT_CR_RELOAD_SET(0xffff));
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ wdt_cr &= (!IFXMIPS_BIU_WDT_CR_PW_SET(0xff) &
+ !IFXMIPS_BIU_WDT_CR_PWL_SET(0x3) &
+ !IFXMIPS_BIU_WDT_CR_CLKDIV_SET(0x3) &
+ !IFXMIPS_BIU_WDT_CR_RELOAD_SET(0xffff));
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) |
- DANUBE_BIU_WDT_CR_PWL_SET(DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR))) |
- DANUBE_BIU_WDT_CR_CLKDIV_SET(DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR))) |
- DANUBE_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
- DANUBE_BIU_WDT_CR_GEN);
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) |
+ IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR))) |
+ IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR))) |
+ IFXMIPS_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
+ IFXMIPS_BIU_WDT_CR_GEN);
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
printk("watchdog enabled\n");
@@ -90,8 +90,8 @@ out:
void
danube_wdt_disable (void)
{
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
printk("watchdog disabled\n");
}
@@ -102,20 +102,20 @@ danube_wdt_enable_feature (int en, int type)
{
unsigned int wdt_cr = 0;
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
if (en)
{
- wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff));
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | type);
+ wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | type);
} else {
- wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff) & ~type);
- wdt_cr |= DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2);
+ wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff) & ~type);
+ wdt_cr |= IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2);
}
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -123,14 +123,14 @@ danube_wdt_prewarning_limit (int pwl)
{
unsigned int wdt_cr = 0;
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xf300ffff;
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_PWL_SET(pwl));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_PWL_SET(pwl));
/* Set reload value in second password access */
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -138,14 +138,14 @@ danube_wdt_set_clkdiv (int clkdiv)
{
unsigned int wdt_cr = 0;
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xfc00ffff;
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_CLKDIV_SET(clkdiv));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_CLKDIV_SET(clkdiv));
/* Set reload value in second password access */
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
static int
@@ -156,7 +156,7 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
static int timeout = -1;
unsigned int user_arg;
- if ((cmd != DANUBE_WDT_IOC_STOP) && (cmd != DANUBE_WDT_IOC_PING) && (cmd != DANUBE_WDT_IOC_GET_STATUS))
+ if ((cmd != IFXMIPS_WDT_IOC_STOP) && (cmd != IFXMIPS_WDT_IOC_PING) && (cmd != IFXMIPS_WDT_IOC_GET_STATUS))
{
if (copy_from_user((void *) &user_arg, (void *) arg, sizeof (int))){
result = -EINVAL;
@@ -166,43 +166,43 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
switch (cmd)
{
- case DANUBE_WDT_IOC_START:
+ case IFXMIPS_WDT_IOC_START:
if ((result = danube_wdt_enable(user_arg)) < 0)
timeout = -1;
else
timeout = user_arg;
break;
- case DANUBE_WDT_IOC_STOP:
+ case IFXMIPS_WDT_IOC_STOP:
printk("disable watch dog timer\n");
danube_wdt_disable();
break;
- case DANUBE_WDT_IOC_PING:
+ case IFXMIPS_WDT_IOC_PING:
if (timeout < 0)
result = -EIO;
else
result = danube_wdt_enable(timeout);
break;
- case DANUBE_WDT_IOC_GET_STATUS:
- user_arg = readl(DANUBE_BIU_WDT_SR);
+ case IFXMIPS_WDT_IOC_GET_STATUS:
+ user_arg = readl(IFXMIPS_BIU_WDT_SR);
copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
break;
- case DANUBE_WDT_IOC_SET_PWL:
+ case IFXMIPS_WDT_IOC_SET_PWL:
danube_wdt_prewarning_limit(user_arg);
break;
- case DANUBE_WDT_IOC_SET_DSEN:
- danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_DSEN);
+ case IFXMIPS_WDT_IOC_SET_DSEN:
+ danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_DSEN);
break;
- case DANUBE_WDT_IOC_SET_LPEN:
- danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_LPEN);
+ case IFXMIPS_WDT_IOC_SET_LPEN:
+ danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_LPEN);
break;
- case DANUBE_WDT_IOC_SET_CLKDIV:
+ case IFXMIPS_WDT_IOC_SET_CLKDIV:
danube_wdt_set_clkdiv(user_arg);
break;
@@ -239,11 +239,11 @@ danube_wdt_register_proc_read (char *buf, char **start, off_t offset, int count,
{
int len = 0;
- len += sprintf (buf + len, "DANUBE_BIU_WDT_PROC_READ\n");
- len += sprintf (buf + len, "DANUBE_BIU_WDT_CR(0x%08x) : 0x%08x\n",
- (unsigned int)DANUBE_BIU_WDT_CR, readl(DANUBE_BIU_WDT_CR));
- len += sprintf (buf + len, "DANUBE_BIU_WDT_SR(0x%08x) : 0x%08x\n",
- (unsigned int)DANUBE_BIU_WDT_SR, readl(DANUBE_BIU_WDT_SR));
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_PROC_READ\n");
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_CR(0x%08x) : 0x%08x\n",
+ (unsigned int)IFXMIPS_BIU_WDT_CR, readl(IFXMIPS_BIU_WDT_CR));
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_SR(0x%08x) : 0x%08x\n",
+ (unsigned int)IFXMIPS_BIU_WDT_SR, readl(IFXMIPS_BIU_WDT_SR));
*eof = 1;
diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/danube.c b/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
index 25e9df3..46ab528 100644
--- a/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
+++ b/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
@@ -1,5 +1,5 @@
/*
- * Driver for DANUBE flashmap
+ * Driver for IFXMIPS flashmap
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
static struct map_info
danube_map = {
- .name = "DANUBE_FLASH",
+ .name = "IFXMIPS_FLASH",
.bankwidth = 2,
.size = 0x400000,
};
@@ -108,8 +108,8 @@ danube_partitions[4] = {
},
};
-#define DANUBE_FLASH_START 0x10000000
-#define DANUBE_FLASH_MAX 0x2000000
+#define IFXMIPS_FLASH_START 0x10000000
+#define IFXMIPS_FLASH_MAX 0x2000000
int
find_uImage_size (unsigned long start_offset){
@@ -136,16 +136,16 @@ init_danube_mtd (void)
struct mtd_partition *parts = NULL;
unsigned long uimage_size;
- writel(0x1d7ff, DANUBE_EBU_BUSCON0);
+ writel(0x1d7ff, IFXMIPS_EBU_BUSCON0);
danube_map.read = danube_read16;
danube_map.write = danube_write16;
danube_map.copy_from = danube_copy_from;
danube_map.copy_to = danube_copy_to;
- danube_map.phys = DANUBE_FLASH_START;
- danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
- danube_map.size = DANUBE_FLASH_MAX;
+ danube_map.phys = IFXMIPS_FLASH_START;
+ danube_map.virt = ioremap_nocache(IFXMIPS_FLASH_START, IFXMIPS_FLASH_MAX);
+ danube_map.size = IFXMIPS_FLASH_MAX;
if (!danube_map.virt) {
printk(KERN_WARNING "Failed to ioremap!\n");
return -EIO;
@@ -191,4 +191,4 @@ module_exit (cleanup_danube_mtd);
MODULE_LICENSE ("GPL");
MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");
+MODULE_DESCRIPTION ("MTD map driver for IFXMIPS boards");
diff --git a/target/linux/ifxmips/files/drivers/net/danube_mii0.c b/target/linux/ifxmips/files/drivers/net/danube_mii0.c
index 354ccc3..861ff81 100644
--- a/target/linux/ifxmips/files/drivers/net/danube_mii0.c
+++ b/target/linux/ifxmips/files/drivers/net/danube_mii0.c
@@ -57,8 +57,8 @@ danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
- while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
- writel(val, DANUBE_PPE32_MDIO_ACC);
+ while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+ writel(val, IFXMIPS_PPE32_MDIO_ACC);
}
unsigned short
@@ -68,9 +68,9 @@ danube_read_mdio (u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
- writel(val, DANUBE_PPE32_MDIO_ACC);
- while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
- val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+ writel(val, IFXMIPS_PPE32_MDIO_ACC);
+ while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+ val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
@@ -84,7 +84,7 @@ danube_switch_open (struct net_device *dev)
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
{
- if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
+ if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
}
@@ -238,7 +238,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
netif_stop_queue(&danube_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
{
- if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
+ if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
}
break;
@@ -332,15 +332,15 @@ switch_init (struct net_device *dev)
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
{
priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
- priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
+ priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
}
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
if(i == 0)
- priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
else
- priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
}
dma_device_register(priv->dma_device);
@@ -373,17 +373,17 @@ switch_init (struct net_device *dev)
static void
danube_sw_chip_init (int mode)
{
- danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
- danube_pmu_enable(DANUBE_PMU_PWDCR_PPE);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
if(mode == REV_MII_MODE)
- writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
+ writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
- writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
+ writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
- writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
+ writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
- writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
+ writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}
diff --git a/target/linux/ifxmips/files/drivers/serial/danube_asc.c b/target/linux/ifxmips/files/drivers/serial/danube_asc.c
index b50b1e7..90f569c 100644
--- a/target/linux/ifxmips/files/drivers/serial/danube_asc.c
+++ b/target/linux/ifxmips/files/drivers/serial/danube_asc.c
@@ -1,5 +1,5 @@
/*
- * Driver for DANUBEASC serial ports
+ * Driver for IFXMIPSASC serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
@@ -52,7 +52,7 @@
#include <asm/danube/danube_irq.h>
#include <asm/danube/danube_serial.h>
-#define PORT_DANUBEASC 111
+#define PORT_IFXMIPSASC 111
#include <linux/serial_core.h>
@@ -88,7 +88,7 @@ static void
danubeasc_stop_rx (struct uart_port *port)
{
/* clear the RX enable bit */
- writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
+ writel(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
}
static void
@@ -104,12 +104,12 @@ danubeasc_rx_chars (struct uart_port *port)
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
- fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
+ fifocnt = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
- ch = readl(DANUBE_ASC1_RBUF);
- rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+ ch = readl(IFXMIPS_ASC1_RBUF);
+ rsr = (readl(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
@@ -120,14 +120,14 @@ danubeasc_rx_chars (struct uart_port *port)
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
}
rsr &= port->read_status_mask;
@@ -166,11 +166,11 @@ danubeasc_tx_chars (struct uart_port *port)
return;
}
- while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
+ while(((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
{
if (port->x_char) {
- writel(port->x_char, DANUBE_ASC1_TBUF);
+ writel(port->x_char, IFXMIPS_ASC1_TBUF);
port->icount.tx++;
port->x_char = 0;
continue;
@@ -179,7 +179,7 @@ danubeasc_tx_chars (struct uart_port *port)
if (uart_circ_empty(xmit))
break;
- writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
+ writel(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
@@ -191,7 +191,7 @@ danubeasc_tx_chars (struct uart_port *port)
static irqreturn_t
danubeasc_tx_int (int irq, void *port)
{
- writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
+ writel(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
danubeasc_start_tx(port);
mask_and_ack_danube_irq(irq);
@@ -202,8 +202,8 @@ static irqreturn_t
danubeasc_er_int (int irq, void *port)
{
/* clear any pending interrupts */
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
- ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
+ ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
return IRQ_HANDLED;
}
@@ -211,7 +211,7 @@ danubeasc_er_int (int irq, void *port)
static irqreturn_t
danubeasc_rx_int (int irq, void *port)
{
- writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
+ writel(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
danubeasc_rx_chars((struct uart_port *) port);
mask_and_ack_danube_irq(irq);
@@ -223,7 +223,7 @@ danubeasc_tx_empty (struct uart_port *port)
{
int status;
- status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
+ status = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
@@ -251,18 +251,18 @@ danubeasc1_hw_init (void)
{
/* this setup was probably already done in ROM/u-boot but we do it again*/
/* TODO: GPIO pins are multifunction */
- writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
- writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
- writel(0, DANUBE_ASC1_PISEL);
- writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
- ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
- writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
- ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
+ writel((readl(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
+ writel(0, IFXMIPS_ASC1_PISEL);
+ writel(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
+ ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
+ writel(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
+ ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
wmb ();
/*framing, overrun, enable */
- writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
- DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
+ IFXMIPS_ASC1_CON);
}
static int
@@ -281,36 +281,36 @@ danubeasc_startup (struct uart_port *port)
local_irq_save(flags);
- retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
+ retval = request_irq(IFXMIPSASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
if (retval){
printk("failed to request danubeasc_rx_int\n");
return retval;
}
- retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
+ retval = request_irq(IFXMIPSASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
if (retval){
printk("failed to request danubeasc_tx_int\n");
goto err1;
}
- retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
+ retval = request_irq(IFXMIPSASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
if (retval){
printk("failed to request danubeasc_er_int\n");
goto err2;
}
writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
- DANUBE_ASC1_IRNREN);
+ IFXMIPS_ASC1_IRNREN);
local_irq_restore(flags);
return 0;
err2:
- free_irq(DANUBEASC1_TIR, port);
+ free_irq(IFXMIPSASC1_TIR, port);
err1:
- free_irq(DANUBEASC1_RIR, port);
+ free_irq(IFXMIPSASC1_RIR, port);
local_irq_restore(flags);
return retval;
@@ -319,19 +319,19 @@ err1:
static void
danubeasc_shutdown (struct uart_port *port)
{
- free_irq(DANUBEASC1_RIR, port);
- free_irq(DANUBEASC1_TIR, port);
- free_irq(DANUBEASC1_EIR, port);
+ free_irq(IFXMIPSASC1_RIR, port);
+ free_irq(IFXMIPSASC1_TIR, port);
+ free_irq(IFXMIPSASC1_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
- writel(0, DANUBE_ASC1_CON);
+ writel(0, IFXMIPS_ASC1_CON);
/* flush and then disable the fifos */
- writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
- writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
- writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
- writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
+ writel(readl(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
+ writel(readl(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
}
static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
@@ -395,7 +395,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
local_irq_save(flags);
/* set up CON */
- writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@@ -403,22 +403,22 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
quot = quot / 2 - 1;
/* disable the baudrate generator */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
/* make sure the fractional divider is off */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
/* set up to use divisor of 2 */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
/* now we can write the new baudrate into the register */
- writel(quot, DANUBE_ASC1_BG);
+ writel(quot, IFXMIPS_ASC1_BG);
/* turn the baudrate generator back on */
- writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
/* enable rx */
- writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
+ writel(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
local_irq_restore(flags);
}
@@ -426,7 +426,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
static const char*
danubeasc_type (struct uart_port *port)
{
- return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
+ return port->type == PORT_IFXMIPSASC ? "IFXMIPSASC" : NULL;
}
static void
@@ -445,7 +445,7 @@ static void
danubeasc_config_port (struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_DANUBEASC;
+ port->type = PORT_IFXMIPSASC;
danubeasc_request_port(port);
}
}
@@ -454,7 +454,7 @@ static int
danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
@@ -483,14 +483,14 @@ static struct uart_ops danubeasc_pops = {
};
static struct uart_port danubeasc_port = {
- membase: (void *)DANUBE_ASC1_BASE_ADDR,
- mapbase: DANUBE_ASC1_BASE_ADDR,
+ membase: (void *)IFXMIPS_ASC1_BASE_ADDR,
+ mapbase: IFXMIPS_ASC1_BASE_ADDR,
iotype: SERIAL_IO_MEM,
- irq: DANUBEASC1_RIR,
+ irq: IFXMIPSASC1_RIR,
uartclk: 0,
fifosize: 16,
- unused: {DANUBEASC1_TIR, DANUBEASC1_EIR},
- type: PORT_DANUBEASC,
+ unused: {IFXMIPSASC1_TIR, IFXMIPSASC1_EIR},
+ type: PORT_IFXMIPSASC,
ops: &danubeasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
};
@@ -507,9 +507,9 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
/* wait until the FIFO is not full */
do
{
- fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+ } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
if (s[i] == '\0')
{
@@ -518,14 +518,14 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
if (s[i] == '\n')
{
- writel('\r', DANUBE_ASC1_TBUF);
+ writel('\r', IFXMIPS_ASC1_TBUF);
do
{
- fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+ } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
}
- writel(s[i], DANUBE_ASC1_TBUF);
+ writel(s[i], IFXMIPS_ASC1_TBUF);
}
local_irq_restore(flags);
@@ -545,7 +545,7 @@ danubeasc_console_setup (struct console *co, char *options)
co->index = 0;
port = &danubeasc_port;
danubeasc_port.uartclk = uartclk;
- danubeasc_port.type = PORT_DANUBEASC;
+ danubeasc_port.type = PORT_IFXMIPSASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);