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| author | John Crispin <john@openwrt.org> | 2007-12-20 22:29:45 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2007-12-20 22:29:45 +0000 |
| commit | b998d4fa51609b2b1e3a91deb118918c301dd7e8 (patch) | |
| tree | 27cb7ef40b5d90fbcf3fe736719e92367a3990e3 /target/linux/ifxmips/files/include/asm-mips | |
| parent | 498a2e30702494fd3171fdc813bee410cc94661a (diff) | |
| download | mtk-20170518-b998d4fa51609b2b1e3a91deb118918c301dd7e8.zip mtk-20170518-b998d4fa51609b2b1e3a91deb118918c301dd7e8.tar.gz mtk-20170518-b998d4fa51609b2b1e3a91deb118918c301dd7e8.tar.bz2 | |
move danube folder to ifxmips, to allow future integration of the other chips
SVN-Revision: 9815
Diffstat (limited to 'target/linux/ifxmips/files/include/asm-mips')
14 files changed, 4190 insertions, 0 deletions
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube.h new file mode 100644 index 0000000..5bad876 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube.h @@ -0,0 +1,358 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2005 infineon + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_H__ +#define _DANUBE_H__ + + +/*------------ GENERAL */ + +#define BOARD_SYSTEM_TYPE "DANUBE" + +#define IOPORT_RESOURCE_START 0x10000000 +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff + + +/*------------ ASC1 */ + +#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00) + +/* FIFO status register */ +#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048)) +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 + +/* ASC1 transmit buffer */ +#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020)) + +/* channel operating modes */ +#define ASCOPT_CSIZE 0x3 +#define ASCOPT_CS7 0x1 +#define ASCOPT_CS8 0x2 +#define ASCOPT_PARENB 0x4 +#define ASCOPT_STOPB 0x8 +#define ASCOPT_PARODD 0x0 +#define ASCOPT_CREAD 0x20 + +/* hardware modified control register */ +#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018)) + +/* receive buffer register */ +#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024)) + +/* status register */ +#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014)) + +/* interrupt control */ +#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8)) + +#define ASC_IRNCR_TIR 0x4 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 + +/* clock control */ +#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000)) + +#define DANUBE_ASC1_CLC_DISS 0x2 + +/* port input select register */ +#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004)) + +/* tx fifo */ +#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044)) + +/* rx fifo */ +#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040)) + +/* control */ +#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010)) + +/* timer reload */ +#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050)) + +/* int enable */ +#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4)) + +#define ASC_IRNREN_RX_BUF 0x8 +#define ASC_IRNREN_TX_BUF 0x4 +#define ASC_IRNREN_ERR 0x2 +#define ASC_IRNREN_TX 0x1 + + +/*------------ RCU */ + +#define DANUBE_RCU_BASE_ADDR 0xBF203000 + +/* reset request */ +#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010)) +#define DANUBE_RST_ALL 0x40000000 + + +/*------------ MCD */ + +#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000) + +/* chip id */ +#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028)) + + +/*------------ GPTU */ + +#define DANUBE_GPTU_BASE_ADDR 0xB8000300 + +/* clock control register */ +#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000)) + +/* captur reload register */ +#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030)) + +/* timer 6 control register */ +#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020)) + + +/*------------ EBU */ + +#define DANUBE_EBU_BASE_ADDR 0xBE105300 + +/* bus configuration register */ +#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060)) +#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090)) +#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4)) +#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0)) + + +/*------------ CGU */ + +#define DANUBE_CGU_BASE_ADDR 0xBF103000 + +/* clock mux */ +#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010)) +#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018)) +#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034)) + +#define CLOCK_60M 60000000 +#define CLOCK_83M 83333333 +#define CLOCK_111M 111111111 +#define CLOCK_133M 133333333 +#define CLOCK_167M 166666667 +#define CLOCK_333M 333333333 + + +/*------------ CGU */ + +#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000) + +#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C)) +#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020)) + + +/*------------ ICU */ + +#define DANUBE_ICU_BASE_ADDR 0xBF880200 + + +#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000)) +#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008)) +#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010)) +#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018)) +#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020)) + +#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028)) + +#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR) + + +/*------------ ETOP */ + +#define DANUBE_PPE32_BASE_ADDR 0xBE180000 + +#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 + +#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 ) + +#define MII_MODE 1 + +#define REV_MII_MODE 2 + +/* mdio access */ +#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804)) + +#define MDIO_ACC_REQUEST 0x80000000 +#define MDIO_ACC_READ 0x40000000 +#define MDIO_ACC_ADDR_MASK 0x1f +#define MDIO_ACC_ADDR_OFFSET 0x15 +#define MDIO_ACC_REG_MASK 0xff +#define MDIO_ACC_REG_OFFSET 0x10 +#define MDIO_ACC_VAL_MASK 0xffff + +/* configuration */ +#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808)) + +#define PPE32_MII_MASK 0xfffffffc +#define PPE32_MII_NORMAL 0x8 +#define PPE32_MII_REVERSE 0xe + +/* packet length */ +#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820)) + +#define PPE32_PLEN_OVER 0x5ee +#define PPE32_PLEN_UNDER 0x400000 + +/* enet */ +#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840)) + +#define PPE32_CGEN 0x800 + + +/*------------ DMA */ +#define DANUBE_DMA_BASE_ADDR 0xBE104100 + +#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18)) +#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C)) +#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4)) +#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C)) +#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28)) +#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24)) +#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40)) +#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44)) +#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10)) +#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14)) +#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20)) + + +/*------------ PCI */ +#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) + +#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) +#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) +#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) +#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) +#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) +#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) +#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) +#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) +#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000)) +#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030)) +#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080)) +#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) +#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044)) +#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048)) +#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C)) +#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010)) +#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) +#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) +#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C)) + +#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) + +#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004)) + +#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER2_REQ_MASK_2BITS 12 +#define INTERNAL_ARB_ENABLE_BIT 0 + + +/*------------ WDT */ + +#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000) + +#define DANUBE_BIU_WDT_CR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0)) +#define DANUBE_BIU_WDT_SR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8)) + +#define DANUBE_BIU_WDT_CR_GEN (1 << 31) +#define DANUBE_BIU_WDT_CR_DSEN (1 << 30) +#define DANUBE_BIU_WDT_CR_LPEN (1 << 29) + +#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) +#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) +#define DANUBE_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26) +#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) +#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) +#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) + + +/*------------ LED */ + +#define DANUBE_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) +#define DANUBE_LED_CON0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000)) +#define DANUBE_LED_CON1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004)) +#define DANUBE_LED_CPU0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008)) +#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C)) +#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010)) + +#define LED_CON0_SWU (1 << 31) +#define LED_CON0_AD1 (1 << 25) +#define LED_CON0_AD0 (1 << 24) + +#define DANUBE_LED_2HZ (0) +#define DANUBE_LED_4HZ (1 << 23) +#define DANUBE_LED_8HZ (2 << 23) +#define DANUBE_LED_10HZ (3 << 23) +#define DANUBE_LED_MASK (0xf << 23) + +#define DANUBE_LED_UPD_SRC_FPI (1 << 31) +#define DANUBE_LED_UPD_MASK (3 << 30) +#define DANUBE_LED_ADSL_SRC (3 << 24) + +#define DANUBE_LED_GROUP0 (1 << 0) +#define DANUBE_LED_GROUP1 (1 << 1) +#define DANUBE_LED_GROUP2 (1 << 2) + +#define DANUBE_LED_RISING 0 +#define DANUBE_LED_FALLING (1 << 26) +#define DANUBE_LED_EDGE_MASK (1 << 26) + + +/*------------ GPIO */ + +#define DANUBE_GPIO_BASE_ADDR (0xBE100B00) + +#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010)) +#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040)) +#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014)) +#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044)) +#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018)) +#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048)) +#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C)) +#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C)) +#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020)) +#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050)) +#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024)) +#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054)) +#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028)) +#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058)) +#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C)) +#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C)) +#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030)) +#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060)) + + +/*------------ SSC */ + +#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800) + + + + + + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h new file mode 100644 index 0000000..219fd49 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h @@ -0,0 +1,202 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2005 infineon + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_DMA_H__ +#define _DANUBE_DMA_H__ + +#define RCV_INT 1 +#define TX_BUF_FULL_INT 2 +#define TRANSMIT_CPT_INT 4 +#define DANUBE_DMA_CH_ON 1 +#define DANUBE_DMA_CH_OFF 0 +#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100 + +enum attr_t{ + TX = 0, + RX = 1, + RESERVED = 2, + DEFAULT = 3, +}; + +#define DMA_OWN 1 +#define CPU_OWN 0 +#define DMA_MAJOR 250 + +#define DMA_DESC_OWN_CPU 0x0 +#define DMA_DESC_OWN_DMA 0x80000000 +#define DMA_DESC_CPT_SET 0x40000000 +#define DMA_DESC_SOP_SET 0x20000000 +#define DMA_DESC_EOP_SET 0x10000000 + +#define MISCFG_MASK 0x40 +#define RDERR_MASK 0x20 +#define CHOFF_MASK 0x10 +#define DESCPT_MASK 0x8 +#define DUR_MASK 0x4 +#define EOP_MASK 0x2 + +#define DMA_DROP_MASK (1<<31) + +#define DANUBE_DMA_RX -1 +#define DANUBE_DMA_TX 1 + +typedef struct dma_chan_map { + char dev_name[15]; + enum attr_t dir; + int pri; + int irq; + int rel_chan_no; +} _dma_chan_map; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +typedef struct rx_desc{ + u32 data_length:16; + volatile u32 reserved:7; + volatile u32 byte_offset:2; + volatile u32 Burst_length_offset:3; + volatile u32 EoP:1; + volatile u32 Res:1; + volatile u32 C:1; + volatile u32 OWN:1; + volatile u32 Data_Pointer; + /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ +}_rx_desc; + +typedef struct tx_desc{ + volatile u32 data_length:16; + volatile u32 reserved1:7; + volatile u32 byte_offset:5; + volatile u32 EoP:1; + volatile u32 SoP:1; + volatile u32 C:1; + volatile u32 OWN:1; + volatile u32 Data_Pointer;//fix me:should be 28 bits here +}_tx_desc; +#else //BIG +typedef struct rx_desc{ + union + { + struct + { + volatile u32 OWN:1; + volatile u32 C:1; + volatile u32 SoP:1; + volatile u32 EoP:1; + volatile u32 Burst_length_offset:3; + volatile u32 byte_offset:2; + volatile u32 reserve:7; + volatile u32 data_length:16; + }field; + volatile u32 word; + }status; + volatile u32 Data_Pointer; +}_rx_desc; + +typedef struct tx_desc{ + union + { + struct + { + volatile u32 OWN:1; + volatile u32 C:1; + volatile u32 SoP:1; + volatile u32 EoP:1; + volatile u32 byte_offset:5; + volatile u32 reserved:7; + volatile u32 data_length:16; + }field; + volatile u32 word; + }status; + volatile u32 Data_Pointer; +}_tx_desc; +#endif //ENDIAN + +typedef struct dma_channel_info{ + /*relative channel number*/ + int rel_chan_no; + /*class for this channel for QoS*/ + int pri; + /*specify byte_offset*/ + int byte_offset; + /*direction*/ + int dir; + /*irq number*/ + int irq; + /*descriptor parameter*/ + int desc_base; + int desc_len; + int curr_desc; + int prev_desc;/*only used if it is a tx channel*/ + /*weight setting for WFQ algorithm*/ + int weight; + int default_weight; + int packet_size; + int burst_len; + /*on or off of this channel*/ + int control; + /**optional information for the upper layer devices*/ +#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA) + void* opt[64]; +#else + void* opt[25]; +#endif + /*Pointer to the peripheral device who is using this channel*/ + void* dma_dev; + /*channel operations*/ + void (*open)(struct dma_channel_info* pCh); + void (*close)(struct dma_channel_info* pCh); + void (*reset)(struct dma_channel_info* pCh); + void (*enable_irq)(struct dma_channel_info* pCh); + void (*disable_irq)(struct dma_channel_info* pCh); +}_dma_channel_info; + +typedef struct dma_device_info{ + /*device name of this peripheral*/ + char device_name[15]; + int reserved; + int tx_burst_len; + int rx_burst_len; + int default_weight; + int current_tx_chan; + int current_rx_chan; + int num_tx_chan; + int num_rx_chan; + int max_rx_chan_num; + int max_tx_chan_num; + _dma_channel_info* tx_chan[20]; + _dma_channel_info* rx_chan[20]; + /*functions, optional*/ + u8* (*buffer_alloc)(int len,int* offset, void** opt); + void (*buffer_free)(u8* dataptr, void* opt); + int (*intr_handler)(struct dma_device_info* info, int status); + void * priv; /* used by peripheral driver only */ +}_dma_device_info; + +_dma_device_info* dma_device_reserve(char* dev_name); + +void dma_device_release(_dma_device_info* dev); + +void dma_device_register(_dma_device_info* info); + +void dma_device_unregister(_dma_device_info* info); + +int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); + +int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h new file mode 100644 index 0000000..2ea8d9c --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h @@ -0,0 +1,42 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_GPIO_H__ +#define _DANUBE_GPIO_H__ + +extern int danube_port_reserve_pin (unsigned int port, unsigned int pin); +extern int danube_port_free_pin (unsigned int port, unsigned int pin); +extern int danube_port_set_open_drain (unsigned int port, unsigned int pin); +extern int danube_port_clear_open_drain (unsigned int port, unsigned int pin); +extern int danube_port_set_pudsel (unsigned int port, unsigned int pin); +extern int danube_port_clear_pudsel (unsigned int port, unsigned int pin); +extern int danube_port_set_puden (unsigned int port, unsigned int pin); +extern int danube_port_clear_puden (unsigned int port, unsigned int pin); +extern int danube_port_set_stoff (unsigned int port, unsigned int pin); +extern int danube_port_clear_stoff (unsigned int port, unsigned int pin); +extern int danube_port_set_dir_out (unsigned int port, unsigned int pin); +extern int danube_port_set_dir_in (unsigned int port, unsigned int pin); +extern int danube_port_set_output (unsigned int port, unsigned int pin); +extern int danube_port_clear_output (unsigned int port, unsigned int pin); +extern int danube_port_get_input (unsigned int port, unsigned int pin); +extern int danube_port_set_altsel0 (unsigned int port, unsigned int pin); +extern int danube_port_clear_altsel0 (unsigned int port, unsigned int pin); +extern int danube_port_set_altsel1 (unsigned int port, unsigned int pin); +extern int danube_port_clear_altsel1 (unsigned int port, unsigned int pin); + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h new file mode 100644 index 0000000..6d14f5d --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h @@ -0,0 +1,42 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_IOCTL_H__ +#define _DANUBE_IOCTL_H__ + +/*------------ LED */ + +struct danube_port_ioctl_parm +{ + int port; + int pin; + int value; +}; + +#define DANUBE_PORT_IOC_MAGIC 0xbf +#define DANUBE_PORT_IOCOD _IOW(DANUBE_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCPUDSEL _IOW(DANUBE_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCPUDEN _IOW(DANUBE_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCSTOFF _IOW(DANUBE_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCDIR _IOW(DANUBE_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCOUTPUT _IOW(DANUBE_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCINPUT _IOWR(DANUBE_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCALTSEL0 _IOW(DANUBE_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm) +#define DANUBE_PORT_IOCALTSEL1 _IOW(DANUBE_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm) + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h new file mode 100644 index 0000000..4579683 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h @@ -0,0 +1,66 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2005 infineon + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_IRQ__ +#define _DANUBE_IRQ__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) +#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) +#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7) +#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9) +#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10) + +#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15) +#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14) +#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16) + +#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) + +#define MIPS_CPU_TIMER_IRQ 7 + +#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0) +#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) +#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) +#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) +#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) +#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) +#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) +#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) +#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) +#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) +#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) +#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) +#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) +#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) +#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) +#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) +#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) +#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) +#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) +#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) + +extern void mask_and_ack_danube_irq (unsigned int irq_nr); + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h new file mode 100644 index 0000000..6f96ef6 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h @@ -0,0 +1,254 @@ +#ifndef DANUBE_SW_H +#define DANUBE_SW_H + + + +/****************************************************************************** +** +** FILE NAME : danube_sw.h +** PROJECT : Danube +** MODULES : ETH Interface (MII0) +** +** DATE : 11 AUG 2005 +** AUTHOR : Wu Qi Ming +** DESCRIPTION : ETH Interface (MII0) Driver Header File +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 11 AUG 2005 Wu Qi Ming Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +*******************************************************************************/ + + +#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE +#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 +#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 +#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 +#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 +#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 +#define SET_ETH_REG SIOCDEVPRIVATE+6 +#define VLAN_TOOLS SIOCDEVPRIVATE+7 +#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8 +#define SET_VLAN_COS SIOCDEVPRIVATE+9 +#define SET_DSCP_COS SIOCDEVPRIVATE+10 +#define ENABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+11 +#define DISABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+12 +#define VLAN_CLASS_FIRST SIOCDEVPRIVATE+13 +#define VLAN_CLASS_SECOND SIOCDEVPRIVATE+14 +#define ENABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+15 +#define DISABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+16 +#define PASS_UNICAST_PACKETS SIOCDEVPRIVATE+17 +#define FILTER_UNICAST_PACKETS SIOCDEVPRIVATE+18 +#define KEEP_BROADCAST_PACKETS SIOCDEVPRIVATE+19 +#define DROP_BROADCAST_PACKETS SIOCDEVPRIVATE+20 +#define KEEP_MULTICAST_PACKETS SIOCDEVPRIVATE+21 +#define DROP_MULTICAST_PACKETS SIOCDEVPRIVATE+22 + + +/*===mac table commands==*/ +#define RESET_MAC_TABLE 0 +#define READ_MAC_ENTRY 1 +#define WRITE_MAC_ENTRY 2 +#define ADD_MAC_ENTRY 3 + +/*====vlan commands===*/ + +#define CHANGE_VLAN_CTRL 0 +#define READ_VLAN_ENTRY 1 +#define UPDATE_VLAN_ENTRY 2 +#define CLEAR_VLAN_ENTRY 3 +#define RESET_VLAN_TABLE 4 +#define ADD_VLAN_ENTRY 5 + +/* +** MDIO constants. +*/ + +#define MDIO_BASE_STATUS_REG 0x1 +#define MDIO_BASE_CONTROL_REG 0x0 +#define MDIO_PHY_ID_HIGH_REG 0x2 +#define MDIO_PHY_ID_LOW_REG 0x3 +#define MDIO_BC_NEGOTIATE 0x0200 +#define MDIO_BC_FULL_DUPLEX_MASK 0x0100 +#define MDIO_BC_AUTO_NEG_MASK 0x1000 +#define MDIO_BC_SPEED_SELECT_MASK 0x2000 +#define MDIO_STATUS_100_FD 0x4000 +#define MDIO_STATUS_100_HD 0x2000 +#define MDIO_STATUS_10_FD 0x1000 +#define MDIO_STATUS_10_HD 0x0800 +#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800 +#define MDIO_ADVERTISMENT_REG 0x4 +#define MDIO_ADVERT_100_FD 0x100 +#define MDIO_ADVERT_100_HD 0x080 +#define MDIO_ADVERT_10_FD 0x040 +#define MDIO_ADVERT_10_HD 0x020 +#define MDIO_LINK_UP_MASK 0x4 +#define MDIO_START 0x1 +#define MDIO_READ 0x2 +#define MDIO_WRITE 0x1 +#define MDIO_PREAMBLE 0xfffffffful + +#define PHY_RESET 0x8000 +#define AUTO_NEGOTIATION_ENABLE 0X1000 +#define AUTO_NEGOTIATION_COMPLETE 0x20 +#define RESTART_AUTO_NEGOTIATION 0X200 + + +/*ETOP_MDIO_CFG MASKS*/ +#define SMRST_MASK 0X2000 +#define PHYA1_MASK 0X1F00 +#define PHYA0_MASK 0XF8 +#define UMM1_MASK 0X4 +#define UMM0_MASK 0X2 + +/*ETOP_MDIO_ACCESS MASKS*/ +#define MDIO_RA_MASK 0X80000000 +#define MDIO_RW_MASK 0X40000000 + + +/*ENET_MAC_CFG MASKS*/ +#define BP_MASK 1<<12 +#define CGEN_MASK 1<<11 +#define IFG_MASK 0x3F<<5 +#define IPAUS_MASK 1<<4 +#define EPAUS_MASK 1<<3 +#define DUPLEX_MASK 1<<2 +#define SPEED_MASK 0x2 +#define LINK_MASK 1 + +/*ENETS_CoS_CFG MASKS*/ +#define VLAN_MASK 2 +#define DSCP_MASK 1 + +/*ENET_CFG MASKS*/ +#define VL2_MASK 1<<29 +#define FTUC_MASK 1<<25 +#define DPBC_MASK 1<<24 +#define DPMC_MASK 1<<23 + +#define PHY0_ADDR 0 +#define PHY1_ADDR 1 +#define P1M 0 + +#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num)) + +#define OK 0; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +typedef struct mac_table_entry{ + u64 mac_address:48; + u64 p0:1; + u64 p1:1; + u64 p2:1; + u64 cr:1; + u64 ma_st:3; + u64 res:9; +}_mac_table_entry; + +typedef struct IFX_Switch_VLanTableEntry{ + u32 vlan_id:12; + u32 mp0:1; + u32 mp1:1; + u32 mp2:1; + u32 v:1; + u32 res:16; +}_IFX_Switch_VLanTableEntry; + +typedef struct mac_table_req{ + int cmd; + int index; + u32 data; + u64 entry_value; +}_mac_table_req; + +#else //not CONFIG_CPU_LITTLE_ENDIAN +typedef struct mac_table_entry{ + u64 mac_address:48; + u64 p0:1; + u64 p1:1; + u64 p2:1; + u64 cr:1; + u64 ma_st:3; + u64 res:9; +}_mac_table_entry; + +typedef struct IFX_Switch_VLanTableEntry{ + u32 vlan_id:12; + u32 mp0:1; + u32 mp1:1; + u32 mp2:1; + u32 v:1; + u32 res:16; +}_IFX_Switch_VLanTableEntry; + + +typedef struct mac_table_req{ + int cmd; + int index; + u32 data; + u64 entry_value; +}_mac_table_req; + +#endif //CONFIG_CPU_LITTLE_ENDIAN + +typedef struct vlan_cos_req{ + int pri; + int cos_value; +}_vlan_cos_req; + +typedef struct dscp_cos_req{ + int dscp; + int cos_value; +}_dscp_cos_req; + + +typedef struct vlan_req{ + int cmd; + int index; + u32 data; + u32 entry_value; +}_vlan_req; + +typedef struct data_req{ + int index; + u32 value; +}_data_req; + +enum duplex +{ + half, + full, + autoneg +}; + +struct switch_priv { + struct net_device_stats stats; + int rx_packetlen; + u8 *rx_packetdata; + int rx_status; + int tx_packetlen; +#ifdef CONFIG_NET_HW_FLOWCONTROL + int fc_bit; +#endif //CONFIG_NET_HW_FLOWCONTROL + u8 *tx_packetdata; + int tx_status; + struct dma_device_info *dma_device; + struct sk_buff *skb; + spinlock_t lock; + int mdio_phy_addr; + int current_speed; + int current_speed_selection; + int rx_queue_len; + int full_duplex; + enum duplex current_duplex; +}; + +#endif //DANUBE_SW_H diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h new file mode 100644 index 0000000..4197933 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h @@ -0,0 +1,2021 @@ +#ifndef DANUBE_H +#define DANUBE_H +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ + +/***********************************************************************/ +/* Module : WDT register address and bits */ +/***********************************************************************/ + +#define BOARD_SYSTEM_TYPE "DANUBE" + +#define DANUBE_BIU_WDT (KSEG1+0x1F880000) + +/***Watchdog Timer Control Register ***/ +#define DANUBE_BIU_WDT_CR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F0)) +#define DANUBE_BIU_WDT_CR_GEN (1 << 31) +#define DANUBE_BIU_WDT_CR_DSEN (1 << 30) +#define DANUBE_BIU_WDT_CR_LPEN (1 << 29) +#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) +#define DANUBE_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) +#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) +#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) +#define DANUBE_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) +#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) +#define DANUBE_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) +#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***Watchdog Timer Status Register***/ +#define DANUBE_BIU_WDT_SR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F8)) +#define DANUBE_BIU_WDT_SR_EN (1 << 31) +#define DANUBE_BIU_WDT_SR_AE (1 << 30) +#define DANUBE_BIU_WDT_SR_PRW (1 << 29) +#define DANUBE_BIU_WDT_SR_EXP (1 << 28) +#define DANUBE_BIU_WDT_SR_PWD (1 << 27) +#define DANUBE_BIU_WDT_SR_DS (1 << 26) +#define DANUBE_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) +#define DANUBE_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : PMU register address and bits */ +/***********************************************************************/ + +#define DANUBE_PMU (KSEG1+0x1F102000) + +/* PMU Power down Control Register */ +#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C)) +#define DANUBE_PMU_PWDCR_GPT (1 << 12) +#define DANUBE_PMU_PWDCR_FPI (1 << 14) + + +/* PMU Status Register */ +#define DANUBE_PMU_SR ((volatile u32*)(DANUBE_PMU+0x0020)) + +#define DANUBE_PMU_DMA_SHIFT 5 +#define DANUBE_PMU_PPE_SHIFT 13 +#define DANUBE_PMU_SDIO_SHIFT 16 +#define DANUBE_PMU_ETOP_SHIFT 22 +#define DANUBE_PMU_ENET0_SHIFT 24 +#define DANUBE_PMU_ENET1_SHIFT 25 + +/***********************************************************************/ +/* Module : RCU register address and bits */ +/***********************************************************************/ +#define DANUBE_RCU_BASE_ADDR (0xBF203000) + +#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) /* will remove this, pls use DANUBE_RCU_RST_REQ */ + +#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0010)) +#define DANUBE_RCU_RST_STAT ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0014)) +#define DANUBE_RST_ALL (0x40000000) + +/***Reset Request Register***/ +#define DANUBE_RCU_RST_REQ_CPU0 (1 << 31) +#define DANUBE_RCU_RST_REQ_CPU1 (1 << 3) +#define DANUBE_RCU_RST_REQ_CPUSUB (1 << 29) +#define DANUBE_RCU_RST_REQ_HRST (1 << 28) +#define DANUBE_RCU_RST_REQ_WDT0 (1 << 27) +#define DANUBE_RCU_RST_REQ_WDT1 (1 << 26) +#define DANUBE_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) +#define DANUBE_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) +#define DANUBE_RCU_RST_REQ_SWTBOOT (1 << 22) +#define DANUBE_RCU_RST_REQ_DMA (1 << 21) +#define DANUBE_RCU_RST_REQ_ARC_JTAG (1 << 20) +#define DANUBE_RCU_RST_REQ_ETHPHY0 (1 << 19) +#define DANUBE_RCU_RST_REQ_CPU0_BR (1 << 18) + +#define DANBUE_RCU_RST_REQ_AFE (1 << 11) +#define DANBUE_RCU_RST_REQ_DFE (1 << 7) + +/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ +#define DANUBE_RCU_RST_REQ_ALL DANUBE_RST_ALL + +#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR) +#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) /* will remove this, pls use DANUBE_RCU_RST_STAT */ + +/*#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) */ + +/***********************************************************************/ +/* Module : BCU register address and bits */ +/***********************************************************************/ + +#define DANUBE_BCU_BASE_ADDR (KSEG1+0x1E100000) + +/***BCU Control Register (0010H)***/ +#define DANUBE_BCU_CON ((volatile u32*)(0x0010 + DANUBE_BCU_BASE_ADDR)) +#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) +#define DANUBE_BCU_BCU_CON_SPE (1 << 19) +#define DANUBE_BCU_BCU_CON_PSE (1 << 18) +#define DANUBE_BCU_BCU_CON_DBG (1 << 16) +#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***BCU Error Control Capture Register (0020H)***/ +#define DANUBE_BCU_ECON ((volatile u32*)(0x0020 + DANUBE_BCU_BASE_ADDR)) +#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) +#define DANUBE_BCU_BCU_ECON_RDN (1 << 23) +#define DANUBE_BCU_BCU_ECON_WRN (1 << 22) +#define DANUBE_BCU_BCU_ECON_SVM (1 << 21) +#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) +#define DANUBE_BCU_BCU_ECON_ABT (1 << 18) +#define DANUBE_BCU_BCU_ECON_RDY (1 << 17) +#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16) +#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) +#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) + +/***BCU Error Address Capture Register (0024 H)***/ +#define DANUBE_BCU_EADD ((volatile u32*)(0x0024 + DANUBE_BCU_BASE_ADDR)) + +/***BCU Error Data Capture Register (0028H)***/ +#define DANUBE_BCU_EDAT ((volatile u32*)(0x0028 + DANUBE_BCU_BASE_ADDR)) +#define DANUBE_BCU_IRNEN ((volatile u32*)(0x00F4 + DANUBE_BCU_BASE_ADDR)) +#define DANUBE_BCU_IRNICR ((volatile u32*)(0x00F8 + DANUBE_BCU_BASE_ADDR)) +#define DANUBE_BCU_IRNCR ((volatile u32*)(0x00FC + DANUBE_BCU_BASE_ADDR)) + +/***********************************************************************/ +/* Module : MBC register address and bits */ +/***********************************************************************/ + +#define DANUBE_MBC (0xBF103000) +/***********************************************************************/ + +/***Mailbox CPU Configuration Register***/ +#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080)) +#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) +#define DANUBE_MBC_MBC_CFG_RES (1 << 5) +#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) +#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0) + +/***Mailbox CPU Interrupt Status Register***/ +#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084)) +#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31) +#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30) +#define DANUBE_MBC_MBC_ISR_B1E (1 << 29) +#define DANUBE_MBC_MBC_ISR_B0E (1 << 28) +#define DANUBE_MBC_MBC_ISR_WDT (1 << 27) +#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask Register***/ +#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088)) +#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31) +#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30) +#define DANUBE_MBC_MBC_MSK_B1E (1 << 29) +#define DANUBE_MBC_MBC_MSK_B0E (1 << 28) +#define DANUBE_MBC_MBC_MSK_WDT (1 << 27) +#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask 01 Register***/ +#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C)) +#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31) +#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30) +#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29) +#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28) +#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27) +#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask 10 Register***/ +#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090)) +#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31) +#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30) +#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29) +#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28) +#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27) +#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Short Command Register***/ +#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094)) +#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***Mailbox CPU Input Data of Buffer 0***/ +#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000)) +#define DANUBE_MBC_MBC_ID0_INDATA + +/***Mailbox CPU Input Data of Buffer 1***/ +#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020)) +#define DANUBE_MBC_MBC_ID1_INDATA + +/***Mailbox CPU Output Data of Buffer 2***/ +#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040)) +#define DANUBE_MBC_MBC_OD2_OUTDATA + +/***Mailbox CPU Output Data of Buffer 3***/ +#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060)) +#define DANUBE_MBC_MBC_OD3_OUTDATA + +/***Mailbox CPU Control Register of Buffer 0***/ +#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004)) +#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 1***/ +#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024)) +#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 2***/ +#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044)) +#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 3***/ +#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064)) +#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Free Space of Buffer 0***/ +#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008)) +#define DANUBE_MBC_MBC_FS0_FS + +/***Mailbox CPU Free Space of Buffer 1***/ +#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028)) +#define DANUBE_MBC_MBC_FS1_FS + +/***Mailbox CPU Free Space of Buffer 2***/ +#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048)) +#define DANUBE_MBC_MBC_FS2_FS + +/***Mailbox CPU Free Space of Buffer 3***/ +#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068)) +#define DANUBE_MBC_MBC_FS3_FS + +/***Mailbox CPU Data Available in Buffer 0***/ +#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C)) +#define DANUBE_MBC_MBC_DA0_DA + +/***Mailbox CPU Data Available in Buffer 1***/ +#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C)) +#define DANUBE_MBC_MBC_DA1_DA + +/***Mailbox CPU Data Available in Buffer 2***/ +#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C)) +#define DANUBE_MBC_MBC_DA2_DA + +/***Mailbox CPU Data Available in Buffer 3***/ +#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C)) +#define DANUBE_MBC_MBC_DA3_DA + +/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ +#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010)) +#define DANUBE_MBC_MBC_IABS0_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ +#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030)) +#define DANUBE_MBC_MBC_IABS1_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ +#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050)) +#define DANUBE_MBC_MBC_IABS2_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ +#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070)) +#define DANUBE_MBC_MBC_IABS3_IABS + +/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ +#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014)) +#define DANUBE_MBC_MBC_ITMP0_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ +#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034)) +#define DANUBE_MBC_MBC_ITMP1_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ +#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054)) +#define DANUBE_MBC_MBC_ITMP2_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ +#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074)) +#define DANUBE_MBC_MBC_ITMP3_ITMP + +/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ +#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018)) +#define DANUBE_MBC_MBC_OABS0_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ +#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038)) +#define DANUBE_MBC_MBC_OABS1_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ +#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058)) +#define DANUBE_MBC_MBC_OABS2_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ +#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078)) +#define DANUBE_MBC_MBC_OABS3_OABS + +/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ +#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C)) +#define DANUBE_MBC_MBC_OTMP0_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ +#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C)) +#define DANUBE_MBC_MBC_OTMP1_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ +#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C)) +#define DANUBE_MBC_MBC_OTMP2_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ +#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C)) +#define DANUBE_MBC_MBC_OTMP3_OTMP + +/***DSP Control Register***/ +#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0)) +#define DANUBE_MBC_DCTRL_BA (1 << 0) +#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) +#define DANUBE_MBC_DCTRL_IDL (1 << 4) +#define DANUBE_MBC_DCTRL_RES (1 << 15) + +/***DSP Status Register***/ +#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4)) +#define DANUBE_MBC_DSTA_IDLE (1 << 0) +#define DANUBE_MBC_DSTA_PD (1 << 1) + +/***DSP Test 1 Register***/ +#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8)) +#define DANUBE_MBC_DTST1_ABORT (1 << 0) +#define DANUBE_MBC_DTST1_HWF32 (1 << 1) +#define DANUBE_MBC_DTST1_HWF4M (1 << 2) +#define DANUBE_MBC_DTST1_HWFOP (1 << 3) + +/***********************************************************************/ +/* Module : MEI register address and bits */ +/***********************************************************************/ +#define MEI_SPACE_ACCESS 0xBE116000 + +/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ +#define MEI_DATA_XFR ((volatile u32*)(0x0000 + MEI_SPACE_ACCESS)) +#define MEI_VERSION ((volatile u32*)(0x0004 + MEI_SPACE_ACCESS)) +#define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + MEI_SPACE_ACCESS)) +#define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + MEI_SPACE_ACCESS)) +#define MEI_XFR_ADDR ((volatile u32*)(0x0010 + MEI_SPACE_ACCESS)) +#define MEI_MAX_WAIT ((volatile u32*)(0x0014 + MEI_SPACE_ACCESS)) +#define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + MEI_SPACE_ACCESS)) +#define ARC_TO_MEI_INT ((volatile u32*)(0x001C + MEI_SPACE_ACCESS)) +#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + MEI_SPACE_ACCESS)) +#define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + MEI_SPACE_ACCESS)) +#define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + MEI_SPACE_ACCESS)) +#define MEI_DEBUG_DATA ((volatile u32*)(0x002C + MEI_SPACE_ACCESS)) +#define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + MEI_SPACE_ACCESS)) +#define MEI_CONFIG ((volatile u32*)(0x0034 + MEI_SPACE_ACCESS)) +#define MEI_RST_CONTROL ((volatile u32*)(0x0038 + MEI_SPACE_ACCESS)) +#define MEI_DBG_MASTER ((volatile u32*)(0x003C + MEI_SPACE_ACCESS)) +#define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + MEI_SPACE_ACCESS)) +#define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + MEI_SPACE_ACCESS)) +#define MEI_BIST_STAT ((volatile u32*)(0x0048 + MEI_SPACE_ACCESS)) +#define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + MEI_SPACE_ACCESS)) +#define MEI_XDATA_BASE ((volatile u32*)(0x0050 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + MEI_SPACE_ACCESS))) +#define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + MEI_SPACE_ACCESS)) +#define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + MEI_SPACE_ACCESS)) + +/***********************************************************************/ +/* Module : SSC1 register address and bits */ +/***********************************************************************/ + +#define DANUBE_SSC1 (KSEG1+0x1e100800) +/***********************************************************************/ +/***SSC Clock Control Register***/ +#define DANUBE_SSC_CLC (0x0000) +#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) +#define DANUBE_SSC_CLC_DISS (1 << 1) +#define DANUBE_SSC_CLC_DISR (1 << 0) +/***SSC Port Input Selection Register***/ +#define DANUBE_SSC_PISEL (0x0004) +/***SSC Identification Register***/ +#define DANUBE_SSC_ID (0x0008) +/***Control Register (Programming Mode)***/ +#define DANUBE_SSC_CON (0x0010) +#define DANUBE_SSC_CON_RUEN (1 << 12) +#define DANUBE_SSC_CON_TUEN (1 << 11) +#define DANUBE_SSC_CON_AEN (1 << 10) +#define DANUBE_SSC_CON_REN (1 << 9) +#define DANUBE_SSC_CON_TEN (1 << 8) +#define DANUBE_SSC_CON_LB (1 << 7) +#define DANUBE_SSC_CON_PO (1 << 6) +#define DANUBE_SSC_CON_PH (1 << 5) +#define DANUBE_SSC_CON_HB (1 << 4) +#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16) +#define DANUBE_SSC_CON_RX_OFF (1 << 1) +#define DANUBE_SSC_CON_TX_OFF (1 << 0) +/***SCC Status Register***/ +#define DANUBE_SSC_STATE (0x0014) +#define DANUBE_SSC_STATE_EN (1 << 0) +#define DANUBE_SSC_STATE_MS (1 << 1) +#define DANUBE_SSC_STATE_BSY (1 << 13) +#define DANUBE_SSC_STATE_RUE (1 << 12) +#define DANUBE_SSC_STATE_TUE (1 << 11) +#define DANUBE_SSC_STATE_AE (1 << 10) +#define DANUBE_SSC_STATE_RE (1 << 9) +#define DANUBE_SSC_STATE_TE (1 << 8) +#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16) +/***SSC Write Hardware Modified Control Register***/ +#define DANUBE_SSC_WHBSTATE ( 0x0018) +#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15) +#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14) +#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13) +#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12) +#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11) +#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10) +#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9) +#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8) +/***SSC Transmitter Buffer Register***/ +#define DANUBE_SSC_TB (0x0020) +#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) +/***SSC Receiver Buffer Register***/ +#define DANUBE_SSC_RB (0x0024) +#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) +/***SSC Receive FIFO Control Register***/ +#define DANUBE_SSC_RXFCON (0x0030) +#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2) +#define DANUBE_SSC_RXFCON_RXFLU (1 << 1) +#define DANUBE_SSC_RXFCON_RXFEN (1 << 0) +/***SSC Transmit FIFO Control Register***/ +#define DANUBE_SSC_TXFCON ( 0x0034) +#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2) +#define DANUBE_SSC_TXFCON_TXFLU (1 << 1) +#define DANUBE_SSC_TXFCON_TXFEN (1 << 0) +/***SSC FIFO Status Register***/ +#define DANUBE_SSC_FSTAT (0x0038) +#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) +/***SSC Baudrate Timer Reload Register***/ +#define DANUBE_SSC_BR (0x0040) +#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) +#define DANUBE_SSC_BRSTAT (0x0044) +#define DANUBE_SSC_SFCON (0x0060) +#define DANUBE_SSC_SFSTAT (0x0064) +#define DANUBE_SSC_GPOCON (0x0070) +#define DANUBE_SSC_GPOSTAT (0x0074) +#define DANUBE_SSC_WHBGPOSTAT (0x0078) +#define DANUBE_SSC_RXREQ (0x0080) +#define DANUBE_SSC_RXCNT (0x0084) +/*DMA Registers in Bus Clock Domain*/ +#define DANUBE_SSC_DMA_CON (0x00EC) +/*interrupt Node Registers in Bus Clock Domain*/ +#define DANUBE_SSC_IRNEN (0x00F4) +#define DANUBE_SSC_IRNCR (0x00F8) +#define DANUBE_SSC_IRNICR (0x00FC) +#define DANUBE_SSC_IRN_FIR 0x8 +#define DANUBE_SSC_IRN_EIR 0x4 +#define DANUBE_SSC_IRN_RIR 0x2 +#define DANUBE_SSC_IRN_TIR 0x1 + +#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC)) +#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID)) +#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON)) +#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE)) +#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE)) +#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB)) +#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB)) +#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT)) +#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL)) +#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON)) +#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON)) +#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR)) +#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT)) +#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON)) +#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT)) +#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON)) +#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT)) +#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT)) +#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ)) +#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT)) +#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON)) +#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN)) +#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR)) +#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR)) + +/***********************************************************************/ +/* Module : GPIO register address and bits */ +/***********************************************************************/ +#define DANUBE_GPIO (0xBE100B00) +/***Port 0 Data Output Register (0010H)***/ +#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010)) +/***Port 1 Data Output Register (0040H)***/ +#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040)) +/***Port 0 Data Input Register (0014H)***/ +#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014)) +/***Port 1 Data Input Register (0044H)***/ +#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044)) +/***Port 0 Direction Register (0018H)***/ +#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018)) +/***Port 1 Direction Register (0048H)***/ +#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048)) +/***Port 0 Alternate Function Select Register 0 (001C H) ***/ +#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C)) +/***Port 1 Alternate Function Select Register 0 (004C H) ***/ +#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C)) +/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ +#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020)) +/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ +#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050)) +/***Port 0 Open Drain Control Register (0024H)***/ +#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024)) +/***Port 1 Open Drain Control Register (0054H)***/ +#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054)) +/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ +#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028)) +/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ +#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058)) +/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ +#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C)) +/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ +#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C)) +/***Port 0 Pull Up Device Enable Register (0030 H)***/ +#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030)) +/***Port 1 Pull Up Device Enable Register (0060 H)***/ +#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060)) +/***********************************************************************/ +/* Module : CGU register address and bits */ +/***********************************************************************/ + +#define DANUBE_CGU (0xBF103000) +/***********************************************************************/ +/***CGU Clock PLL0 ***/ +#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004)) +/***CGU Clock PLL1 ***/ +#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008)) +/***CGU Clock SYS Mux Register***/ +#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010)) +/***CGU Interface Clock Control Register***/ +#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) +/***CGU PCI Clock Control Register**/ +#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034)) +#define CLOCK_60M 60000000 +#define CLOCK_83M 83333333 +#define CLOCK_111M 111111111 +#define CLOCK_133M 133333333 +#define CLOCK_167M 166666667 +#define CLOCK_333M 333333333 + +/***********************************************************************/ +/* Module : MCD register address and bits */ +/***********************************************************************/ +#define DANUBE_MCD (KSEG1+0x1F106000) + +/***Manufacturer Identification Register***/ +#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024)) +#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) + +/***Chip Identification Register***/ +#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028)) +#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) +#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) +#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) +#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) +#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) +#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) + +#define DANUBE_CHIPID_STANDARD 0x00EB +#define DANUBE_CHIPID_YANGTSE 0x00ED + +/***Redesign Tracing Identification Register***/ +#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C)) +#define DANUBE_MCD_RTID_LC (1 << 15) +#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : EBU register address and bits */ +/***********************************************************************/ + +#define DANUBE_EBU (0xBE105300) + +/***********************************************************************/ + +/***EBU Clock Control Register***/ +#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000)) +#define DANUBE_EBU_CLC_DISS (1 << 1) +#define DANUBE_EBU_CLC_DISR (1 << 0) + +/***EBU Global Control Register***/ +#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010)) +#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) +#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) +#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) +#define DANUBE_EBU_CON_ARBSYNC (1 << 5) +#define DANUBE_EBU_CON_1 (1 << 3) + +/***EBU Address Select Register 0***/ +#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020)) +#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1) +#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0) + +/***EBU Address Select Register 1***/ +#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024)) +#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1) +#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0) + +/***EBU Address Select Register 2***/ +#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028)) +#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1) +#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0) + +/***EBU Address Select Register 3***/ +#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028)) +#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1) +#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0) + +/***EBU Bus Configuration Register 0***/ +#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060)) +#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31) +#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19) +#define DANUBE_EBU_BUSCON0_SETUP (1 << 18) +#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 1***/ +#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064)) +#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31) +#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19) +#define DANUBE_EBU_BUSCON1_SETUP (1 << 18) +#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 2***/ +#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068)) +#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31) +#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19) +#define DANUBE_EBU_BUSCON2_SETUP (1 << 18) +#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +#define DANUBE_EBU_PCC_CON ((volatile u32*)(DANUBE_EBU+ 0x0090)) +#define DANUBE_EBU_PCC_STAT ((volatile u32*)(DANUBE_EBU+ 0x0094)) +#define DANUBE_EBU_PCC_ISTAT ((volatile u32*)(DANUBE_EBU+ 0x00A0)) +#define DANUBE_EBU_PCC_IEN ((volatile u32*)(DANUBE_EBU+ 0x00A4)) +/***********************************************************************/ +/* Module : SDRAM register address and bits */ +/***********************************************************************/ + +#define DANUBE_SDRAM (0xBF800000) +/***********************************************************************/ + +/***MC Access Error Cause Register***/ +#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100)) +#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31) +#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) +#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) +#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) + +/***MC Access Error Address Register***/ +#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108)) +#define DANUBE_SDRAM_MC_ERRADDR_ADDR + +/***MC I/O General Purpose Register***/ +#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800)) +#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) +#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) +#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) +#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) +#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) +#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11) +#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) +#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***MC Self Refresh Register***/ +#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00)) +#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1) +#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0) +#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) + +/***MC Enable Register***/ +#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000)) +#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0) +#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) + +/***MC Mode Register Setup Code***/ +#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008)) +#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) +#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) +#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3) +#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***MC Configuration Data-word Width Register***/ +#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010)) +#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) +#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) + +/***MC Configuration Physical Bank 0 Register***/ +#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018)) +#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) +#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) +#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) +#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) + +/***MC Latency Register***/ +#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038)) +#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) +#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) +#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) +#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) +#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) + +/***MC Refresh Cycle Time Register***/ +#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040)) +#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) +#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) + +/***********************************************************************/ +/* Module : GPTC register address and bits */ +/***********************************************************************/ + +#define DANUBE_GPTC (KSEG1 + 0x1E100A00) +#define DANUBE_GPTC_CLC ((volatile u32*) (DANUBE_GPTC + 0x0000)) +#define DANUBE_GPTC_ID ((volatile u32*) (DANUBE_GPTC + 0x0008)) +#define DANUBE_GPTC_IRNEN ((volatile u32*) (DANUBE_GPTC + 0x00F4)) +#define DANUBE_GPTC_IRNICR ((volatile u32*) (DANUBE_GPTC + 0x00F8) +#define DANUBE_GPTC_IRNCR ((volatile u32*) (DANUBE_GPTC + 0x00FC)) + +#define DANUBE_GPTC_CON_1A ((volatile u32*) (DANUBE_GPTC + 0x0010)) +#define DANUBE_GPTC_RUN_1A ((volatile u32*) (DANUBE_GPTC + 0x0018)) +#define DANUBE_GPTC_RELOAD_1A ((volatile u32*) (DANUBE_GPTC + 0x0020)) +#define DANUBE_GPTC_COUNT_1A ((volatile u32*) (DANUBE_GPTC + 0x0028)) + +#define DANUBE_GPTC_CON_1B ((volatile u32*) (DANUBE_GPTC + 0x0014)) +#define DANUBE_GPTC_RUN_1B ((volatile u32*) (DANUBE_GPTC + 0x001C)) +#define DANUBE_GPTC_RELOAD_1B ((volatile u32*) (DANUBE_GPTC + 0x0024)) +#define DANUBE_GPTC_COUNT_1B ((volatile u32*) (DANUBE_GPTC + 0x002C)) + +#define DANUBE_GPTC_CON_2A ((volatile u32*) (DANUBE_GPTC + 0x0030)) +#define DANUBE_GPTC_RUN_2A ((volatile u32*) (DANUBE_GPTC + 0x0038)) +#define DANUBE_GPTC_RELOAD_2A ((volatile u32*) (DANUBE_GPTC + 0x0040)) +#define DANUBE_GPTC_COUNT_2A ((volatile u32*) (DANUBE_GPTC + 0x0048)) + +#define DANUBE_GPTC_CON_2B ((volatile u32*) (DANUBE_GPTC + 0x0034)) +#define DANUBE_GPTC_RUN_2B ((volatile u32*) (DANUBE_GPTC + 0x003C)) +#define DANUBE_GPTC_RELOAD_2B ((volatile u32*) (DANUBE_GPTC + 0x0044)) +#define DANUBE_GPTC_COUNT_2B ((volatile u32*) (DANUBE_GPTC + 0x004C)) + +/***********************************************************************/ +/* Module : GPTU register address and bits */ +/***********************************************************************/ + +#define DANUBE_GPTU (0xB8000300) +/***********************************************************************/ + +/***GPT Clock Control Register***/ +#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000)) +#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1) +#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0) + +/***GPT Timer 3 Control Register***/ +#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014)) +#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15) +#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14) +#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13) +#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) +#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10) +#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7) +#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6) +#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write Hardware Modified Timer 3 Control Register +If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C)) +#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) +#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) +#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) +#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) +#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) +#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) + +/***GPT Timer 2 Control Register***/ +#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010)) +#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15) +#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14) +#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13) +#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12) +#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9) +#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7) +#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6) +#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) +#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Timer 4 Control Register***/ +#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018)) +#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15) +#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14) +#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13) +#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12) +#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9) +#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7) +#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6) +#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) +#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 2 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048)) +#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) +#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) +#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) +#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) + +/***GPT Write HW Modified Timer 4 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050)) +#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) +#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) +#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) +#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) + +/***GPT Capture Reload Register***/ +#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030)) +#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 2 Register***/ +#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034)) +#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 3 Register***/ +#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038)) +#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 4 Register***/ +#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C)) +#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 5 Register***/ +#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040)) +#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Register***/ +#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044)) +#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Control Register***/ +#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020)) +#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15) +#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14) +#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) +#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10) +#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7) +#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6) +#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 6 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054)) +#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) +#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) + +/***GPT Timer 5 Control Register***/ +#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C)) +#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15) +#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14) +#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) +#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11) +#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10) +#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9) +#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8) +#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7) +#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6) +#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : IOM register address and bits */ +/***********************************************************************/ + +#define DANUBE_IOM (0xBF105000) +/***********************************************************************/ + +/***Receive FIFO***/ +#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) +#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Transmit FIFO***/ +#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) +#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Interrupt Status Register HDLC***/ +#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080)) +#define DANUBE_IOM_ISTAH_RME (1 << 7) +#define DANUBE_IOM_ISTAH_RPF (1 << 6) +#define DANUBE_IOM_ISTAH_RFO (1 << 5) +#define DANUBE_IOM_ISTAH_XPR (1 << 4) +#define DANUBE_IOM_ISTAH_XMR (1 << 3) +#define DANUBE_IOM_ISTAH_XDU (1 << 2) + +/***Interrupt Mask Register HDLC***/ +#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080)) +#define DANUBE_IOM_MASKH_RME (1 << 7) +#define DANUBE_IOM_MASKH_RPF (1 << 6) +#define DANUBE_IOM_MASKH_RFO (1 << 5) +#define DANUBE_IOM_MASKH_XPR (1 << 4) +#define DANUBE_IOM_MASKH_XMR (1 << 3) +#define DANUBE_IOM_MASKH_XDU (1 << 2) + +/***Status Register***/ +#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084)) +#define DANUBE_IOM_STAR_XDOV (1 << 7) +#define DANUBE_IOM_STAR_XFW (1 << 6) +#define DANUBE_IOM_STAR_RACI (1 << 3) +#define DANUBE_IOM_STAR_XACI (1 << 1) + +/***Command Register***/ +#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084)) +#define DANUBE_IOM_CMDR_RMC (1 << 7) +#define DANUBE_IOM_CMDR_RRES (1 << 6) +#define DANUBE_IOM_CMDR_XTF (1 << 3) +#define DANUBE_IOM_CMDR_XME (1 << 1) +#define DANUBE_IOM_CMDR_XRES (1 << 0) + +/***Mode Register***/ +#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088)) +#define DANUBE_IOM_MODEH_MDS2 (1 << 7) +#define DANUBE_IOM_MODEH_MDS1 (1 << 6) +#define DANUBE_IOM_MODEH_MDS0 (1 << 5) +#define DANUBE_IOM_MODEH_RAC (1 << 3) +#define DANUBE_IOM_MODEH_DIM2 (1 << 2) +#define DANUBE_IOM_MODEH_DIM1 (1 << 1) +#define DANUBE_IOM_MODEH_DIM0 (1 << 0) + +/***Extended Mode Register***/ +#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C)) +#define DANUBE_IOM_EXMR_XFBS (1 << 7) +#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) +#define DANUBE_IOM_EXMR_SRA (1 << 4) +#define DANUBE_IOM_EXMR_XCRC (1 << 3) +#define DANUBE_IOM_EXMR_RCRC (1 << 2) +#define DANUBE_IOM_EXMR_ITF (1 << 0) + +/***SAPI1 Register***/ +#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094)) +#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define DANUBE_IOM_SAP1_MHA (1 << 0) + +/***Receive Frame Byte Count Low***/ +#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098)) +#define DANUBE_IOM_RBCL_RBC(value) (1 << value) + +/***SAPI2 Register***/ +#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098)) +#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define DANUBE_IOM_SAP2_MLA (1 << 0) + +/***Receive Frame Byte Count High***/ +#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C)) +#define DANUBE_IOM_RBCH_OV (1 << 4) +#define DANUBE_IOM_RBCH_RBC11 (1 << 3) +#define DANUBE_IOM_RBCH_RBC10 (1 << 2) +#define DANUBE_IOM_RBCH_RBC9 (1 << 1) +#define DANUBE_IOM_RBCH_RBC8 (1 << 0) + +/***TEI1 Register 1***/ +#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C)) +#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) +#define DANUBE_IOM_TEI1_EA (1 << 0) + +/***Receive Status Register***/ +#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0)) +#define DANUBE_IOM_RSTA_VFR (1 << 7) +#define DANUBE_IOM_RSTA_RDO (1 << 6) +#define DANUBE_IOM_RSTA_CRC (1 << 5) +#define DANUBE_IOM_RSTA_RAB (1 << 4) +#define DANUBE_IOM_RSTA_SA1 (1 << 3) +#define DANUBE_IOM_RSTA_SA0 (1 << 2) +#define DANUBE_IOM_RSTA_TA (1 << 0) +#define DANUBE_IOM_RSTA_CR (1 << 1) + +/***TEI2 Register***/ +#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0)) +#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) +#define DANUBE_IOM_TEI2_EA (1 << 0) + +/***Test Mode Register HDLC***/ +#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4)) +#define DANUBE_IOM_TMH_TLP (1 << 0) + +/***Command/Indication Receive 0***/ +#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) +#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_IOM_CIR0_CIC0 (1 << 3) +#define DANUBE_IOM_CIR0_CIC1 (1 << 2) +#define DANUBE_IOM_CIR0_SG (1 << 1) +#define DANUBE_IOM_CIR0_BAS (1 << 0) + +/***Command/Indication Transmit 0***/ +#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) +#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define DANUBE_IOM_CIX0_TBA2 (1 << 3) +#define DANUBE_IOM_CIX0_TBA1 (1 << 2) +#define DANUBE_IOM_CIX0_TBA0 (1 << 1) +#define DANUBE_IOM_CIX0_BAC (1 << 0) + +/***Command/Indication Receive 1***/ +#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) +#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) + +/***Command/Indication Transmit 1***/ +#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) +#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define DANUBE_IOM_CIX1_CICW (1 << 1) +#define DANUBE_IOM_CIX1_CI1E (1 << 0) + +/***Controller Data Access Reg. (CH10)***/ +#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100)) +#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH11)***/ +#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104)) +#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH20)***/ +#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108)) +#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH21)***/ +#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C)) +#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH10)***/ +#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110)) +#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7) +#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH11)***/ +#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114)) +#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7) +#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH20)***/ +#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118)) +#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7) +#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH21)***/ +#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C)) +#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7) +#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH10)***/ +#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120)) +#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7) +#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH11)***/ +#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124)) +#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7) +#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH20)***/ +#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128)) +#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7) +#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH21)***/ +#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C)) +#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7) +#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Ctrl. Reg. Contr. Data Access CH1x***/ +#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138)) +#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5) +#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4) +#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3) +#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2) +#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1) +#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0) + +/***Ctrl. Reg. Contr. Data Access CH1x***/ +#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C)) +#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5) +#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4) +#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3) +#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2) +#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1) +#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0) + +/***Control Register B-Channel Data***/ +#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144)) +#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4) +#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3) + +/***Control Register B-Channel Data***/ +#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148)) +#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4) +#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3) + +/***Control Reg. for HDLC and CI1 Data***/ +#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) +#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7) +#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6) +#define DANUBE_IOM_DCI_CR_EN_D (1 << 5) + +/***Control Reg. for HDLC and CI1 Data***/ +#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) +#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7) +#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6) +#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5) + +/***Control Reg. Serial Data Strobe x***/ +#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154)) +#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7) +#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6) +#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5) +#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Control Register IOM Data***/ +#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C)) +#define DANUBE_IOM_IOM_CR_SPU (1 << 7) +#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5) +#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4) +#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3) +#define DANUBE_IOM_IOM_CR_CLKM (1 << 2) +#define DANUBE_IOM_IOM_CR_Res (1 << 1) +#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0) + +/***Synchronous Transfer Interrupt***/ +#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160)) +#define DANUBE_IOM_STI_STOV21 (1 << 7) +#define DANUBE_IOM_STI_STOV20 (1 << 6) +#define DANUBE_IOM_STI_STOV11 (1 << 5) +#define DANUBE_IOM_STI_STOV10 (1 << 4) +#define DANUBE_IOM_STI_STI21 (1 << 3) +#define DANUBE_IOM_STI_STI20 (1 << 2) +#define DANUBE_IOM_STI_STI11 (1 << 1) +#define DANUBE_IOM_STI_STI10 (1 << 0) + +/***Acknowledge Synchronous Transfer Interrupt***/ +#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160)) +#define DANUBE_IOM_ASTI_ACK21 (1 << 3) +#define DANUBE_IOM_ASTI_ACK20 (1 << 2) +#define DANUBE_IOM_ASTI_ACK11 (1 << 1) +#define DANUBE_IOM_ASTI_ACK10 (1 << 0) + +/***Mask Synchronous Transfer Interrupt***/ +#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164)) +#define DANUBE_IOM_MSTI_STOV21 (1 << 7) +#define DANUBE_IOM_MSTI_STOV20 (1 << 6) +#define DANUBE_IOM_MSTI_STOV11 (1 << 5) +#define DANUBE_IOM_MSTI_STOV10 (1 << 4) +#define DANUBE_IOM_MSTI_STI21 (1 << 3) +#define DANUBE_IOM_MSTI_STI20 (1 << 2) +#define DANUBE_IOM_MSTI_STI11 (1 << 1) +#define DANUBE_IOM_MSTI_STI10 (1 << 0) + +/***Configuration Register for Serial Data Strobes***/ +#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168)) +#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0) + +/***Monitoring CDA Bits***/ +#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C)) +#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) +#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) +#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) +#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : ASC0 register address and bits */ +/***********************************************************************/ +#define DANUBE_ASC0 (KSEG1+0x1E100400) +/***********************************************************************/ +#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020)) +#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024)) +#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048)) +#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) +#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) +#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) +#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) +#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) +#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) +#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : ASC1 register address and bits */ +/***********************************************************************/ + +#define DANUBE_ASC1 (KSEG1+0x1E100C00) +/***********************************************************************/ +/***ASC Clock Control Register***/ +#define DANUBE_ASC1_CLC ((volatile u32*)(DANUBE_ASC1+ 0x0000)) +#define DANUBE_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) +#define DANUBE_ASC1_CLC_DISS (1 << 1) +#define DANUBE_ASC1_CLC_DISR (1 << 0) + +/***ASC Port Input Select Register***/ +#define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004)) +#define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004)) +#define DANUBE_ASC1_PISEL_RIS (1 << 0) + +/***ASC Control Register***/ +#define DANUBE_ASC1_CON ((volatile u32*)(DANUBE_ASC1+ 0x0010)) +#define DANUBE_ASC1_CON_BEN (1 << 20) +#define DANUBE_ASC1_CON_TOEN (1 << 20) +#define DANUBE_ASC1_CON_ROEN (1 << 19) +#define DANUBE_ASC1_CON_RUEN (1 << 18) +#define DANUBE_ASC1_CON_FEN (1 << 17) +#define DANUBE_ASC1_CON_PAL (1 << 16) +#define DANUBE_ASC1_CON_R (1 << 15) +#define DANUBE_ASC1_CON_ACO (1 << 14) +#define DANUBE_ASC1_CON_LB (1 << 13) +#define DANUBE_ASC1_CON_ERCLK (1 << 10) +#define DANUBE_ASC1_CON_FDE (1 << 9) +#define DANUBE_ASC1_CON_BRS (1 << 8) +#define DANUBE_ASC1_CON_STP (1 << 7) +#define DANUBE_ASC1_CON_SP (1 << 6) +#define DANUBE_ASC1_CON_ODD (1 << 5) +#define DANUBE_ASC1_CON_PEN (1 << 4) +#define DANUBE_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***ASC Staus Register***/ +#define DANUBE_ASC1_STATE ((volatile u32*)(DANUBE_ASC1+ 0x0014)) +/***ASC Write Hardware Modified Control Register***/ +#define DANUBE_ASC1_WHBSTATE ((volatile u32*)(DANUBE_ASC1+ 0x0018)) +#define DANUBE_ASC1_WHBSTATE_SETBE (1 << 113) +#define DANUBE_ASC1_WHBSTATE_SETTOE (1 << 12) +#define DANUBE_ASC1_WHBSTATE_SETROE (1 << 11) +#define DANUBE_ASC1_WHBSTATE_SETRUE (1 << 10) +#define DANUBE_ASC1_WHBSTATE_SETFE (1 << 19) +#define DANUBE_ASC1_WHBSTATE_SETPE (1 << 18) +#define DANUBE_ASC1_WHBSTATE_CLRBE (1 << 17) +#define DANUBE_ASC1_WHBSTATE_CLRTOE (1 << 6) +#define DANUBE_ASC1_WHBSTATE_CLRROE (1 << 5) +#define DANUBE_ASC1_WHBSTATE_CLRRUE (1 << 4) +#define DANUBE_ASC1_WHBSTATE_CLRFE (1 << 3) +#define DANUBE_ASC1_WHBSTATE_CLRPE (1 << 2) +#define DANUBE_ASC1_WHBSTATE_SETREN (1 << 1) +#define DANUBE_ASC1_WHBSTATE_CLRREN (1 << 0) + +/***ASC Baudrate Timer/Reload Register***/ +#define DANUBE_ASC1_BG ((volatile u32*)(DANUBE_ASC1+ 0x0050)) +#define DANUBE_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) + +/***ASC Fractional Divider Register***/ +#define DANUBE_ASC1_FDV ((volatile u32*)(DANUBE_ASC1+ 0x0018)) +#define DANUBE_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Transmit Buffer Register***/ +#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1+ 0x0020)) +#define DANUBE_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Receive Buffer Register***/ +#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1+ 0x0024)) +#define DANUBE_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Autobaud Control Register***/ +#define DANUBE_ASC1_ABCON ((volatile u32*)(DANUBE_ASC1+ 0x0030)) +#define DANUBE_ASC1_ABCON_RXINV (1 << 11) +#define DANUBE_ASC1_ABCON_TXINV (1 << 10) +#define DANUBE_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) +#define DANUBE_ASC1_ABCON_FCDETEN (1 << 4) +#define DANUBE_ASC1_ABCON_ABDETEN (1 << 3) +#define DANUBE_ASC1_ABCON_ABSTEN (1 << 2) +#define DANUBE_ASC1_ABCON_AUREN (1 << 1) +#define DANUBE_ASC1_ABCON_ABEN (1 << 0) + +/***Receive FIFO Control Register***/ +#define DANUBE_ASC1_RXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0040)) +#define DANUBE_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_ASC1_RXFCON_RXFFLU (1 << 1) +#define DANUBE_ASC1_RXFCON_RXFEN (1 << 0) + +/***Transmit FIFO Control Register***/ +#define DANUBE_ASC1_TXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0044)) +#define DANUBE_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_ASC1_TXFCON_TXFFLU (1 << 1) +#define DANUBE_ASC1_TXFCON_TXFEN (1 << 0) + +/***FIFO Status Register***/ +#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0048)) +#define DANUBE_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) +#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) +#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) +#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) +#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) +#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) +#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) +#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) +#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) + +/***ASC Autobaud Status Register***/ +#define DANUBE_ASC1_ABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0034)) +#define DANUBE_ASC1_ABSTAT_DETWAIT (1 << 4) +#define DANUBE_ASC1_ABSTAT_SCCDET (1 << 3) +#define DANUBE_ASC1_ABSTAT_SCSDET (1 << 2) +#define DANUBE_ASC1_ABSTAT_FCCDET (1 << 1) +#define DANUBE_ASC1_ABSTAT_FCSDET (1 << 0) + +/***ASC Write HW Modified Autobaud Status Register***/ +#define DANUBE_ASC1_WHBABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x003C)) +#define DANUBE_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) +#define DANUBE_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) +#define DANUBE_ASC1_WHBABSTAT_SETSCCDET (1 << 7) +#define DANUBE_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) +#define DANUBE_ASC1_WHBABSTAT_SETSCSDET (1 << 5) +#define DANUBE_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) +#define DANUBE_ASC1_WHBABSTAT_SETFCCDET (1 << 3) +#define DANUBE_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) +#define DANUBE_ASC1_WHBABSTAT_SETFCSDET (1 << 1) +#define DANUBE_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) + +/***ASC IRNCR0 **/ +#define DANUBE_ASC1_IRNREN ((volatile u32*)(DANUBE_ASC1+ 0x00F4)) +#define DANUBE_ASC1_IRNICR ((volatile u32*)(DANUBE_ASC1+ 0x00FC)) +/***ASC IRNCR1 **/ +#define DANUBE_ASC1_IRNCR ((volatile u32*)(DANUBE_ASC1+ 0x00F8)) +#define ASC_IRNCR_TIR 0x4 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 + +/***********************************************************************/ +/* Module : DMA register address and bits */ +/***********************************************************************/ + +#define DANUBE_DMA (0xBE104100) +/***********************************************************************/ + +#define DANUBE_DMA_BASE DANUBE_DMA +#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE +#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08) +#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10) +#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14) +#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18) +#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C) +#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20) +#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24) +#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28) +#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C) + +#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40) +#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44) + +#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4) +#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8) +#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc) +/***********************************************************************/ +/* Module : Debug register address and bits */ +/***********************************************************************/ + +#define DANUBE_Debug (0xBF106000) +/***********************************************************************/ + +/***MCD Break Bus Switch Register***/ +#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000)) +#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19) +#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18) +#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17) +#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16) +#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15) +#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14) +#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13) +#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12) +#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7) +#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6) +#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5) +#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4) + +/***MCD Multiplexer Control Register***/ +#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008)) +#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4) +#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3) +#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0) + +/***********************************************************************/ +/* Module : SRAM register address and bits */ +/***********************************************************************/ + +#define DANUBE_SRAM (0xBF980000) +/***********************************************************************/ + +/***SRAM Size Register***/ +#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800)) +#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : BIU register address and bits */ +/***********************************************************************/ + +#define DANUBE_BIU (0xBFA80000) +/***********************************************************************/ + +/***BIU Identification Register***/ +#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000)) +#define DANUBE_BIU_BIU_ID_ARCH (1 << 16) +#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) +#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***BIU Access Error Cause Register***/ +#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100)) +#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31) +#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) +#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***BIU Access Error Address Register***/ +#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108)) +#define DANUBE_BIU_BIU_ERRADDR_ADDR + +/***********************************************************************/ +/* Module : ICU register address and bits */ +/***********************************************************************/ + +#define DANUBE_ICU (0xBF880200) +/***********************************************************************/ +#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU + 0x0000)) +#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU + 0x0008)) +#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU + 0x0010)) +#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU + 0x0018)) +#define DANUBE_ICU_IM0_IMR ((volatile u32*)(DANUBE_ICU + 0x0020)) +#define DANUBE_ICU_IM0_IMR_IID (1 << 31) +#define DANUBE_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM0_IR(value) (1 << (value)) + +#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU + 0x0028)) +#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU + 0x0030)) +#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU + 0x0038)) +#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU + 0x0040)) +#define DANUBE_ICU_IM1_IMR ((volatile u32*)(DANUBE_ICU + 0x0048)) +#define DANUBE_ICU_IM1_IMR_IID (1 << 31) +#define DANUBE_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM1_IR(value) (1 << (value)) + +#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU + 0x0050)) +#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU + 0x0058)) +#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU + 0x0060)) +#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU + 0x0068)) +#define DANUBE_ICU_IM2_IMR ((volatile u32*)(DANUBE_ICU + 0x0070)) +#define DANUBE_ICU_IM2_IMR_IID (1 << 31) +#define DANUBE_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM2_IR(value) (1 << (value)) + +#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU + 0x0078)) +#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU + 0x0080)) +#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU + 0x0088)) +#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU + 0x0090)) +#define DANUBE_ICU_IM3_IMR ((volatile u32*)(DANUBE_ICU + 0x0098)) +#define DANUBE_ICU_IM3_IMR_IID (1 << 31) +#define DANUBE_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM3_IR(value) (1 << (value)) + +#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU + 0x00A0)) +#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU + 0x00A8)) +#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU + 0x00B0)) +#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU + 0x00B8)) +#define DANUBE_ICU_IM4_IMR ((volatile u32*)(DANUBE_ICU + 0x00C0)) +#define DANUBE_ICU_IM4_IMR_IID (1 << 31) +#define DANUBE_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM4_IR(value) (1 << (value)) + +#define DANUBE_ICU_IM5_ISR ((volatile u32*)(DANUBE_ICU + 0x00C8)) +#define DANUBE_ICU_IM5_IER ((volatile u32*)(DANUBE_ICU + 0x00D0)) +#define DANUBE_ICU_IM5_IOSR ((volatile u32*)(DANUBE_ICU + 0x00D8)) +#define DANUBE_ICU_IM5_IRSR ((volatile u32*)(DANUBE_ICU + 0x00E0)) +#define DANUBE_ICU_IM5_IMR ((volatile u32*)(DANUBE_ICU + 0x00E8)) +#define DANUBE_ICU_IM5_IMR_IID (1 << 31) +#define DANUBE_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) +#define DANUBE_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) +#define DANUBE_ICU_IM5_IR(value) (1 << (value)) + +/***Interrupt Vector Value Register***/ +//#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00f0)) +#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00EC)) + +/***Interrupt Vector Value Mask***/ +#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f +#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0 +#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00 +#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000 +#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000 + +#define DANUBE_ICU_IM0_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM0_IER_IR(value) (1<<(value)) +#define DANUBE_ICU_IM1_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM1_IER_IR(value) (1<<(value)) +#define DANUBE_ICU_IM2_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM2_IER_IR(value) (1<<(value)) +#define DANUBE_ICU_IM3_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM3_IER_IR(value) (1<<(value)) +#define DANUBE_ICU_IM4_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM4_IER_IR(value) (1<<(value)) +#define DANUBE_ICU_IM5_ISR_IR(value) (1<<(value)) +#define DANUBE_ICU_IM5_IER_IR(value) (1<<(value)) + +/***DMA Interrupt Mask Value***/ +#define DANUBE_DMA_H_MASK 0x00000fff + +/***External Interrupt Control Register***/ +#define DANUBE_ICU_EIU (KSEG1+0x1f101000) +#define DANUBE_ICU_EIU_EXIN_C ((volatile u32*)(DANUBE_ICU_EIU+ 0x0000)) +#define DANUBE_ICU_EIU_INIC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0004)) +#define DANUBE_ICU_EIU_INC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0008)) +#define DANUBE_ICU_EIU_INEN ((volatile u32*)(DANUBE_ICU_EIU+ 0x000c)) + +/***********************************************************************/ +/* Module : MPS register address and bits */ +/***********************************************************************/ + +#define DANUBE_MPS (KSEG1+0x1F107000) +/***********************************************************************/ + +#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344)) +#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) +#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) +#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) +#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) +#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) +#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) + +/* voice channel 0 ... 3 interrupt enable register */ +#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000)) +#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004)) +#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008)) +#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C)) +/* voice channel 0 ... 3 interrupt status read register */ +#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010)) +#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014)) +#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018)) +#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C)) +/* voice channel 0 ... 3 interrupt status set register */ +#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020)) +#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024)) +#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028)) +#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C)) +/* voice channel 0 ... 3 interrupt status clear register */ +#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030)) +#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034)) +#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038)) +#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C)) +/* common status 0 and 1 read register */ +#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040)) +#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044)) +/* common status 0 and 1 set register */ +#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048)) +#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C)) +/* common status 0 and 1 clear register */ +#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050)) +#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054)) +/* common status 0 and 1 enable register */ +#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058)) +#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C)) +/* notification enable register */ +#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060)) +#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064)) +/* CPU to CPU interrup request register */ +#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070)) +#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074)) +/* Global interrupt request and request enable register */ +#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078)) +#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C)) + +#define DANUBE_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000)) + +#define DANUBE_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0)) + +#define DANUBE_FUSE_BASE_ADDR (KSEG1+0x1F107354) + +/************************************************************************/ +/* Module : DEU register address and bits */ +/************************************************************************/ +//#define DANUBE_DEU_BASE_ADDR (0xBE102000) +#define DANUBE_DEU_BASE_ADDR (KSEG1 + 0x1E103100) +/* DEU Control Register */ +#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000)) +#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008)) + +/* DEU control register */ +#define DANUBE_DES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010)) +#define DANUBE_DES_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014)) +#define DANUBE_DES_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018)) +#define DANUBE_DES_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C)) +#define DANUBE_DES_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020)) +#define DANUBE_DES_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024)) +#define DANUBE_DES_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028)) +#define DANUBE_DES_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C)) +#define DANUBE_DES_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030)) +#define DANUBE_DES_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040)) +#define DANUBE_DES_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) + +/* AES DEU register */ +#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) +#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054)) +#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058)) +#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C)) +#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060)) + +/* AES Key register */ +#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064)) +#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068)) +#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C)) +#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070)) +#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074)) +#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078)) +#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C)) +#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080)) + +/* AES vector register */ +#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084)) +#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088)) +#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C)) +#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090)) +#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094)) +#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098)) +#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C)) +#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0)) + +/* hash control registe */ +#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0)) +#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4)) +#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 )) +#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC )) +#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 )) +#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4)) +#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8)) + +#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC)) + +#define DANUBE_DEU_IRNEN ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F4)) +#define DANUBE_DEU_IRNCR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F8)) +#define DANUBE_DEU_IRNICR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00FC)) + +/************************************************************************/ +/* Module : PPE register address and bits */ +/************************************************************************/ +#define DANUBE_PPE32_BASE 0xBE180000 +#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) +#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) +#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) +#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) +#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) +#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) + +#define DANUBE_PPE32_SRST (DANUBE_PPE32_BASE + 0x10080) + +/* + * ETOP MDIO Registers + */ +#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) +#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) +#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) +#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) +#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) +#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) +#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) +#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) +#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) +#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) +#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) +#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) + +/* ENET Register */ +#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) +#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) +#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) + +/* Sharebuff SB RAM2 control data */ + +#define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4))) +#define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4))) +/************************************************************************/ +/* Module : PPE register address and bits */ +/************************************************************************/ +#define DANUBE_PPE32_BASE 0xBE180000 +#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) +#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) +#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) +#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) +#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) +#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) + +/* + * ETOP MDIO Registers + */ +#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) +#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) +#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) +#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) +#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) +#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) +#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) +#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) +#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) +#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) +#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) +#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) +#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) +#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) +#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) +#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) +#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) +#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) +#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) +#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) +#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) +#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) +#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) +#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) + +#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) +#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) +#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) +#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) +#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) +#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) +#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) + +#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) +#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) +#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) +#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) +#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) +#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) + +/* ENET Register */ +#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) +#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) +#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) + +/* Sharebuff SB RAM2 control data */ + +#define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4))) +#define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4))) + +/***********************************************************************/ +/* Module : PCI register address and bits */ +/***********************************************************************/ +#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) +#define PCI_CFG_BASE (KSEG1+0x17000000) +#define PCI_MEM_BASE (KSEG1+0x18000000) +#define PCI_CS_PR_OFFSET (KSEG1+0x17000000) + +/* PCI CONTROLLER REGISTER ADDRESS MAP */ +#define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000) +#define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004) +#define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010) +#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014) +#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018) +#define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C) +#define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020) +#define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024) +#define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028) +#define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C) +#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) +#define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034) +#define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038) +#define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C) +#define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040) +#define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044) +#define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048) +#define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C) +#define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050) +#define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054) +#define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058) +#define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C) +#define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060) +#define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064) +#define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068) +#define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C) +#define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070) +#define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074) +#define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078) +#define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C) +#define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080) +#define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084) +#define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088) +#define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C) +#define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090) +#define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094) +#define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098) +#define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C) +#define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0) +#define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4) +#define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8) +#define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC) +#define PCI_CR_PCI_ADDR_MAP24_REG (PCI_CR_PR_OFFSET + 0x00B0) +#define PCI_CR_PCI_ADDR_MAP25_REG (PCI_CR_PR_OFFSET + 0x00B4) +#define PCI_CR_PCI_ADDR_MAP26_REG (PCI_CR_PR_OFFSET + 0x00B8) +#define PCI_CR_FPI_ADDR_MASK_REG (PCI_CR_PR_OFFSET + 0x00BC) +#define PCI_CR_FCI_ADDR_MAP0_REG (PCI_CR_PR_OFFSET + 0x00C0) +#define PCI_CR_FCI_ADDR_MAP1_REG (PCI_CR_PR_OFFSET + 0x00C4) +#define PCI_CR_FCI_ADDR_MAP2_REG (PCI_CR_PR_OFFSET + 0x00C8) +#define PCI_CR_FCI_ADDR_MAP3_REG (PCI_CR_PR_OFFSET + 0x00CC) +#define PCI_CR_FCI_ADDR_MAP4_REG (PCI_CR_PR_OFFSET + 0x00D0) +#define PCI_CR_FCI_ADDR_MAP5_REG (PCI_CR_PR_OFFSET + 0x00D4) +#define PCI_CR_FCI_ADDR_MAP6_REG (PCI_CR_PR_OFFSET + 0x00D8) +#define PCI_CR_FCI_ADDR_MAP7_REG (PCI_CR_PR_OFFSET + 0x00DC) +#define PCI_CR_FCI_ADDR_MAP11lo_REG (PCI_CR_PR_OFFSET + 0x00E0) +#define PCI_CR_FCI_ADDR_MAP11hg_REG (PCI_CR_PR_OFFSET + 0x00E4) +#define PCI_CR_FCI_BURST_LENGTH_REG (PCI_CR_PR_OFFSET + 0x00E8) +#define PCI_CR_PCI_SET_SERR_REG (PCI_CR_PR_OFFSET + 0x00EC) +#define PCI_CR_DMA_FPI_ST_ADDR_REG (PCI_CR_PR_OFFSET + 0x00F0) +#define PCI_CR_DMA_PCI_ST_ADDR_REG (PCI_CR_PR_OFFSET + 0x00F4) +#define PCI_CR_DMA_TRAN_CNT_REG (PCI_CR_PR_OFFSET + 0x00F8) +#define PCI_CR_DMA_TRAN_CTL_REG (PCI_CR_PR_OFFSET + 0x00FC) + +/* PCI CONFIGURATION SPACE REGISTER Base Address */ +#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x0800 +#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x1000 +#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x1800 +#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x2000 +#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x2800 +#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x3000 +#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x3800 +#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x4000 +#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x4800 +#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x5000 +#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x5800 +#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x6000 +#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x6800 +#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x7000 +#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x7800 +#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0XF000 + +/* PCI CONFIGURATION SPACE REGISTER ADDRESS MAP */ +#define PCI_CS_DEV_VEN_ID_REG (PCI_CS_PR_OFFSET + 0x0000) +#define PCI_CS_STS_CMD_REG (PCI_CS_PR_OFFSET + 0x0004) +#define PCI_CS_CL_CODE_REVIDG (PCI_CS_PR_OFFSET + 0x0008) +#define PCI_CS_BST_HT_LT_CLS_REG (PCI_CS_PR_OFFSET + 0x000C) +#define PCI_CS_BASE_ADDR1_REG (PCI_CS_PR_OFFSET + 0x0010) +#define PCI_CS_BASE_ADDR2_REG (PCI_CS_PR_OFFSET + 0x0014) +#define PCI_CS_BASE_ADDR3_REG (PCI_CS_PR_OFFSET + 0x0018) +#define PCI_CS_BASE_ADDR4_REG (PCI_CS_PR_OFFSET + 0x001C) +#define PCI_CS_BASE_ADDR5_REG (PCI_CS_PR_OFFSET + 0x0020) +#define PCI_CS_BASE_ADDR6_REG (PCI_CS_PR_OFFSET + 0x0024) +#define PCI_CS_CARDBUS_CIS_PT_REG (PCI_CS_PR_OFFSET + 0x0028) +#define PCI_CS_SUBSYS_VEN_ID_REG (PCI_CS_PR_OFFSET + 0x002C) +#define PCI_CS_EXROM_BAS_ADDR_REG (PCI_CS_PR_OFFSET + 0x0030) +#define PCI_CS_RES1_REG (PCI_CS_PR_OFFSET + 0x0034) +#define PCI_CS_RES2_REG (PCI_CS_PR_OFFSET + 0x0038) +#define PCI_CS_LAT_GNT_INTR_REG (PCI_CS_PR_OFFSET + 0x003C) +#define PCI_CS_PM_PT_CPID_REG (PCI_CS_PR_OFFSET + 0x0040) +#define PCI_CS_DAT_PMCSR_PM_REG (PCI_CS_PR_OFFSET + 0x0044) +#define PCI_CS_RES3_REG (PCI_CS_PR_OFFSET + 0x0048) +#define PCI_CS_RES4_REG (PCI_CS_PR_OFFSET + 0x004C) +#define PCI_CS_ERR_ADDR_PCI_FPI_REG (PCI_CS_PR_OFFSET + 0x0050) +#define PCI_CS_ERR_ADDR_FPI_PCI_REG (PCI_CS_PR_OFFSET + 0x0054) +#define PCI_CS_ERR_TAG_FPI_PCI_REG (PCI_CS_PR_OFFSET + 0x0058) +#define PCI_CS_PC_ARB_REG (PCI_CS_PR_OFFSET + 0x005C) +#define PCI_CS_FPI_PCI_INT_STS_REG (PCI_CS_PR_OFFSET + 0x0060) +#define PCI_CS_FPI_PCI_INT_ACK_REG (PCI_CS_PR_OFFSET + 0x0064) +#define PCI_CS_FPI_PCI_INT_MASK_REG (PCI_CS_PR_OFFSET + 0x0068) +#define PCI_CS_CARDBUS_CTL_STS_REG (PCI_CS_PR_OFFSET + 0x006C) + +// PCI CONTROLLER ADDRESS SPACE +#define PCI_CA_PR_OFFSET 0xB8000000 +#define PCI_CA_PR_END 0xBBFFFFFF + +// PCI CONTROLLER REGISTER ADDRESS MASK +#define PCI_CR_CLK_CTRL_MSK 0x82000000 +#define PCI_CR_PCI_ID_MSK 0x00000000 +#define PCI_CR_SFT_RST_MSK 0x00000002 +#define PCI_CR_PCI_FPI_ERR_ADDR_MSK 0x00000000 +#define PCI_CR_FCI_PCI_ERR_ADDR_MSK 0x00000000 +#define PCI_CR_FPI_ERR_TAG_MSK 0x00000000 +#define PCI_CR_PCI_IRR_MSK 0x07013B2F +#define PCI_CR_PCI_IRA_MSK 0x07013B2F +#define PCI_CR_PCI_IRM_MSK 0x07013B2F +#define PCI_CR_PCI_EOI_MSK 0x07013B2F +#define PCI_CR_PCI_MOD_MSK 0x1107070F +#define PCI_CR_DV_ID_MSK 0x00000000 +#define PCI_CR_SUBSYS_ID_MSK 0x00000000 +#define PCI_CR_PCI_PM_MSK 0x0000001F +#define PCI_CR_CLASS_CODE1_MSK 0x00000000 +#define PCI_CR_BAR11MASK_MSK 0x8FFFFFF8 +#define PCI_CR_BAR12MASK_MSK 0x80001F08 +#define PCI_CR_BAR13MASK_MSK 0x8FF00008 +#define PCI_CR_BAR14MASK_MSK 0x8FFFFF08 +#define PCI_CR_BAR15MASK_MSK 0x8FFFFF08 +#define PCI_CR_BAR16MASK_MSK 0x8FFFFFF9 +#define PCI_CR_CIS_PT1_MSK 0x03FFFFFF +#define PCI_CR_SUBSYS_ID1_MSK 0x00000000 +#define PCI_CR_PCI_ADDR_MAP11_MSK 0x7FFF0001 +#define PCI_CR_PCI_ADDR_MAP12_MSK 0x7FFFFF01 +#define PCI_CR_PCI_ADDR_MAP13_MSK 0x7FF00001 +#define PCI_CR_PCI_ADDR_MAP14_MSK 0x7FFFFF01 +#define PCI_CR_PCI_ADDR_MAP15_MSK 0x7FF00001 +#define PCI_CR_PCI_ADDR_MAP16_MSK 0x7FF00001 +#define PCI_CR_FPI_SEG_EN_MSK 0x000003FF +#define PCI_CR_CLASS_CODE2_MSK 0x00000000 +#define PCI_CR_BAR21MASK_MSK 0x800F0008 +#define PCI_CR_BAR22MASK_MSK 0x807F0008 +#define PCI_CR_BAR23MASK_MSK 0x8FF00008 +#define PCI_CR_BAR24MASK_MSK 0x8FFFFF08 +#define PCI_CR_BAR25MASK_MSK 0x8FFFFF08 +#define PCI_CR_BAR26MASK_MSK 0x8FFFFFF9 +#define PCI_CR_CIS_PT2_MSK 0x03FFFFFF +#define PCI_CR_SUBSYS_ID2_MSK 0x00000000 +#define PCI_CR_PCI_ADDR_MAP21_MSK 0x7FFE0001 +#define PCI_CR_PCI_ADDR_MAP22_MSK 0x7FFF0001 +#define PCI_CR_PCI_ADDR_MAP23_MSK 0x7FF00001 +#define PCI_CR_PCI_ADDR_MAP24_MSK 0x7FFFFF01 +#define PCI_CR_PCI_ADDR_MAP25_MSK 0x7FFFFF01 +#define PCI_CR_PCI_ADDR_MAP26_MSK 0x7FF00001 +#define PCI_CR_FPI_ADDR_MASK_MSK 0x00070000 +#define PCI_CR_FCI_ADDR_MAP0_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP1_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP2_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP3_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP4_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP5_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP6_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP7_MSK 0xFFF00000 +#define PCI_CR_FCI_ADDR_MAP11lo_MSK 0xFFFF0000 +#define PCI_CR_FCI_ADDR_MAP11hg_MSK 0xFFF00000 +#define PCI_CR_FCI_BURST_LENGTH_MSK 0x00000303 +#define PCI_CR_PCI_SET_SERR_MSK 0x00000001 +#define PCI_CR_DMA_FPI_ST_ADDR_MSK 0xFFFFFFFF +#define PCI_CR_DMA_PCI_ST_ADDR_MSK 0xFFFFFFFF +#define PCI_CR_DMA_TRAN_CNT_MSK 0x000003FF +#define PCI_CR_DMA_TRAN_CTL_MSK 0x00000003 + +#define INTERNAL_ARB_ENABLE_BIT 0 +#define ARB_SCHEME_BIT 1 +#define PCI_MASTER0_PRIOR_2BITS 2 +#define PCI_MASTER1_PRIOR_2BITS 4 +#define PCI_MASTER2_PRIOR_2BITS 6 +#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER2_REQ_MASK_2BITS 12 + +#define IOPORT_RESOURCE_START 0x10000000 +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff + +/***********************************************************************/ +#define DANUBE_REG32(addr) *((volatile u32 *)(addr)) +/***********************************************************************/ +#endif //DANUBE_H diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h new file mode 100644 index 0000000..b404b26 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h @@ -0,0 +1,31 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ +#ifndef _DANUBE_PMU_H__ +#define _DANUBE_PMU_H__ + +#define DANUBE_PMU_PWDCR_DMA 0x20 +#define DANUBE_PMU_PWDCR_LED 0x800 +#define DANUBE_PMU_PWDCR_GPT 0x1000 +#define DANUBE_PMU_PWDCR_PPE 0x2000 +#define DANUBE_PMU_PWDCR_FPI 0x4000 + +void danube_pmu_enable (unsigned int module); +void danube_pmu_disable (unsigned int module); + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h new file mode 100644 index 0000000..7b79947 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h @@ -0,0 +1,194 @@ +/* incaAscSio.h - (DANUBE) ASC UART tty driver header */ + +#ifndef __DANUBE_ASC_H +#define __DANUBE_ASC_H + +/****************************************************************************** +** +** FILE NAME : serial.c +** PROJECT : Danube +** MODULES : ASC/UART +** +** DATE : 27 MAR 2006 +** AUTHOR : Liu Peng +** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7) +** 23 OCT 2006 Xu Liang Add GPL header. +*******************************************************************************/ + +/* channel operating modes */ +/*#define ASCOPT_CSIZE 0x00000003 +#define ASCOPT_CS7 0x00000001 +#define ASCOPT_CS8 0x00000002 +#define ASCOPT_PARENB 0x00000004 +#define ASCOPT_STOPB 0x00000008 +#define ASCOPT_PARODD 0x00000010 +#define ASCOPT_CREAD 0x00000020 +*/ +#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) + +/* ASC input select (0 or 1) */ +#define CONSOLE_TTY 0 + +#define DANUBEASC_TXFIFO_FL 1 +#define DANUBEASC_RXFIFO_FL 1 +#define DANUBEASC_TXFIFO_FULL 16 + +/* interrupt lines masks for the ASC device interrupts*/ +/* change these macroses if it's necessary */ +#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */ + +#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */ +#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */ +#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */ +#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */ +#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */ +#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */ +#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */ + +/* interrupt controller access macros */ +#define ASC_INTERRUPTS_ENABLE(X) \ +*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X; +#define ASC_INTERRUPTS_DISABLE(X) \ +*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X; +#define ASC_INTERRUPTS_CLEAR(X) \ +*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X; + +/* CLC register's bits and bitfields */ +#define ASCCLC_DISR 0x00000001 +#define ASCCLC_DISS 0x00000002 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 + +/* CON register's bits and bitfields */ +#define ASCCON_MODEMASK 0x0000000f +#define ASCCON_M_8ASYNC 0x0 +#define ASCCON_M_8IRDA 0x1 +#define ASCCON_M_7ASYNC 0x2 +#define ASCCON_M_7IRDA 0x3 +#define ASCCON_WLSMASK 0x0000000c +#define ASCCON_WLSOFFSET 2 +#define ASCCON_WLS_8BIT 0x0 +#define ASCCON_WLS_7BIT 0x1 +#define ASCCON_PEN 0x00000010 +#define ASCCON_ODD 0x00000020 +#define ASCCON_SP 0x00000040 +#define ASCCON_STP 0x00000080 +#define ASCCON_BRS 0x00000100 +#define ASCCON_FDE 0x00000200 +#define ASCCON_ERRCLK 0x00000400 +#define ASCCON_EMMASK 0x00001800 +#define ASCCON_EMOFFSET 11 +#define ASCCON_EM_ECHO_OFF 0x0 +#define ASCCON_EM_ECHO_AB 0x1 +#define ASCCON_EM_ECHO_ON 0x2 +#define ASCCON_LB 0x00002000 +#define ASCCON_ACO 0x00004000 +#define ASCCON_R 0x00008000 +#define ASCCON_PAL 0x00010000 +#define ASCCON_FEN 0x00020000 +#define ASCCON_RUEN 0x00040000 +#define ASCCON_ROEN 0x00080000 +#define ASCCON_TOEN 0x00100000 +#define ASCCON_BEN 0x00200000 +#define ASCCON_TXINV 0x01000000 +#define ASCCON_RXINV 0x02000000 +#define ASCCON_TXMSB 0x04000000 +#define ASCCON_RXMSB 0x08000000 + +/* STATE register's bits and bitfields */ +#define ASCSTATE_REN 0x00000001 +#define ASCSTATE_PE 0x00010000 +#define ASCSTATE_FE 0x00020000 +#define ASCSTATE_RUE 0x00040000 +#define ASCSTATE_ROE 0x00080000 +#define ASCSTATE_TOE 0x00100000 +#define ASCSTATE_BE 0x00200000 +#define ASCSTATE_TXBVMASK 0x07000000 +#define ASCSTATE_TXBVOFFSET 24 +#define ASCSTATE_TXEOM 0x08000000 +#define ASCSTATE_RXBVMASK 0x70000000 +#define ASCSTATE_RXBVOFFSET 28 +#define ASCSTATE_RXEOM 0x80000000 +#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) + +/* WHBSTATE register's bits and bitfields */ +#define ASCWHBSTATE_CLRREN 0x00000001 +#define ASCWHBSTATE_SETREN 0x00000002 +#define ASCWHBSTATE_CLRPE 0x00000004 +#define ASCWHBSTATE_CLRFE 0x00000008 +#define ASCWHBSTATE_CLRRUE 0x00000010 +#define ASCWHBSTATE_CLRROE 0x00000020 +#define ASCWHBSTATE_CLRTOE 0x00000040 +#define ASCWHBSTATE_CLRBE 0x00000080 +#define ASCWHBSTATE_SETPE 0x00000100 +#define ASCWHBSTATE_SETFE 0x00000200 +#define ASCWHBSTATE_SETRUE 0x00000400 +#define ASCWHBSTATE_SETROE 0x00000800 +#define ASCWHBSTATE_SETTOE 0x00001000 +#define ASCWHBSTATE_SETBE 0x00002000 + +/* ABCON register's bits and bitfields */ +#define ASCABCON_ABEN 0x0001 +#define ASCABCON_AUREN 0x0002 +#define ASCABCON_ABSTEN 0x0004 +#define ASCABCON_ABDETEN 0x0008 +#define ASCABCON_FCDETEN 0x0010 + +/* FDV register mask, offset and bitfields*/ +#define ASCFDV_VALUE_MASK 0x000001FF + +/* WHBABCON register's bits and bitfields */ +#define ASCWHBABCON_CLRABEN 0x0001 +#define ASCWHBABCON_SETABEN 0x0002 + +/* ABSTAT register's bits and bitfields */ +#define ASCABSTAT_FCSDET 0x0001 +#define ASCABSTAT_FCCDET 0x0002 +#define ASCABSTAT_SCSDET 0x0004 +#define ASCABSTAT_SCCDET 0x0008 +#define ASCABSTAT_DETWAIT 0x0010 + +/* WHBABSTAT register's bits and bitfields */ +#define ASCWHBABSTAT_CLRFCSDET 0x0001 +#define ASCWHBABSTAT_SETFCSDET 0x0002 +#define ASCWHBABSTAT_CLRFCCDET 0x0004 +#define ASCWHBABSTAT_SETFCCDET 0x0008 +#define ASCWHBABSTAT_CLRSCSDET 0x0010 +#define ASCWHBABSTAT_SETSCSDET 0x0020 +#define ASCWHBABSTAT_CLRSCCDET 0x0040 +#define ASCWHBABSTAT_SETSCCDET 0x0080 +#define ASCWHBABSTAT_CLRDETWAIT 0x0100 +#define ASCWHBABSTAT_SETDETWAIT 0x0200 + +/* TXFCON register's bits and bitfields */ +#define ASCTXFCON_TXFIFO1 0x00000400 +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 + +/* RXFCON register's bits and bitfields */ +#define ASCRXFCON_RXFIFO1 0x00000400 +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 + +/* FSTAT register's bits and bitfields */ +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 + +#endif /* __DANUBE_ASC_H */ diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h new file mode 100644 index 0000000..1c31fc9 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2005 infineon + * Copyright (C) 2007 John Crispin <blogic@openwrt.org> + * + */ + +#ifndef DANUBE_WDT_H +#define DANUBE_WDT_H + +/* Danube wdt ioctl control */ +#define DANUBE_WDT_IOC_MAGIC 0xc0 +#define DANUBE_WDT_IOC_START _IOW(DANUBE_WDT_IOC_MAGIC, 0, int) +#define DANUBE_WDT_IOC_STOP _IO(DANUBE_WDT_IOC_MAGIC, 1) +#define DANUBE_WDT_IOC_PING _IO(DANUBE_WDT_IOC_MAGIC, 2) +#define DANUBE_WDT_IOC_SET_PWL _IOW(DANUBE_WDT_IOC_MAGIC, 3, int) +#define DANUBE_WDT_IOC_SET_DSEN _IOW(DANUBE_WDT_IOC_MAGIC, 4, int) +#define DANUBE_WDT_IOC_SET_LPEN _IOW(DANUBE_WDT_IOC_MAGIC, 5, int) +#define DANUBE_WDT_IOC_GET_STATUS _IOR(DANUBE_WDT_IOC_MAGIC, 6, int) +#define DANUBE_WDT_IOC_SET_CLKDIV _IOW(DANUBE_WDT_IOC_MAGIC, 7, int) + +/* password 1 and 2 */ +#define DANUBE_WDT_PW1 0x000000BE +#define DANUBE_WDT_PW2 0x000000DC + +#define DANUBE_WDT_CLKDIV0_VAL 1 +#define DANUBE_WDT_CLKDIV1_VAL 64 +#define DANUBE_WDT_CLKDIV2_VAL 4096 +#define DANUBE_WDT_CLKDIV3_VAL 262144 +#define DANUBE_WDT_CLKDIV0 0 +#define DANUBE_WDT_CLKDIV1 1 +#define DANUBE_WDT_CLKDIV2 2 +#define DANUBE_WDT_CLKDIV3 3 + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h new file mode 100644 index 0000000..5bd788f --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h @@ -0,0 +1,119 @@ +//************************************************************************* +//* Summary of definitions which are used in each peripheral * +//************************************************************************* + +#ifndef peripheral_definitions_h +#define peripheral_definitions_h + +////#include "cpu.h" +// +///* These files have to be included by each peripheral */ +//#include <sysdefs.h> +//#include <excep.h> +//#include <cpusubsys.h> +//#include <sys_api.h> +//#include <mips.h> +//#include "SRAM_address_map.h" +// +///* common header files for all CPU's */ +//#include "iiu.h" +//#include "bcu.h" +//#include "FPI_address_map.h" +//#include "direct_interrupts.h" + +///////////////////////////////////////////////////////////////////////// + +//extern int _clz(); +//extern void _nop(); +//extern void _sleep(); +//extern void sys_enable_int(); + +typedef unsigned char UINT8; +typedef signed char INT8; +typedef unsigned short UINT16; +typedef signed short INT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; +typedef signed long long INT64; + +#define REG8( addr ) (*(volatile UINT8 *) (addr)) +#define REG16( addr ) (*(volatile UINT16 *)(addr)) +#define REG32( addr ) (*(volatile UINT32 *)(addr)) +#define REG64( addr ) (*(volatile UINT64 *)(addr)) + +/* define routine to set FPI access in Supervisor Mode */ +#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01 +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00 +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG) +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm +/* enable all Interrupts in IIU */ +//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask +///* get all high priority interrupt bits in IIU */ +//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED) +///* signal ends of interrupt to IIU */ +//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit +///* force IIU interrupt register */ +//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data +///* get all bits of interrupt register */ +//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR) +/* insert a NOP instruction */ +#define NOP _nop() +/* CPU goes to power down mode until interrupt occurs */ +#define IFX_CPU_SLEEP _sleep() +/* enable all interrupts to CPU */ +#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int() +/* get all low priority interrupt bits in peripheral */ +#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg) +/* clear low priority interrupt bit in peripheral */ +#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit +/* write FPI bus */ +#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data +#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data +#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data +/* read FPI bus */ +#define READ_FPI_BYTE(addr) REG8(addr) +#define READ_FPI_16BIT(addr) REG16(addr) +#define READ_FPI_32BIT(addr) REG32(addr) +/* write peripheral register */ +#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data +#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data +#else //not CONFIG_CPU_LITTLE_ENDIAN +#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data +#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data +#endif //CONFIG_CPU_LITTLE_ENDIAN + +/* read peripheral register */ +#define READ_PERIPHERAL_REGISTER(addr) REG32(addr) + +/* read/modify(or)/write peripheral register */ +#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data +/* read/modify(and)/write peripheral register */ +#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data + +/* CPU-independent mnemonic constants */ +/* CLC register bits */ +#define IFX_CLC_ENABLE 0x00000000 +#define IFX_CLC_DISABLE 0x00000001 +#define IFX_CLC_DISABLE_STATUS 0x00000002 +#define IFX_CLC_SUSPEND_ENABLE 0x00000004 +#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008 +#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010 +#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020 +#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00 +#define IFX_CLC_RUN_DIVIDER_OFFSET 8 +#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000 +#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16 +#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000 +#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24 + +/* number of cycles to wait for interrupt service routine to be called */ +#define WAIT_CYCLES 50 + +#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */ diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc.h b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc.h new file mode 100644 index 0000000..e541c8e --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc.h @@ -0,0 +1,258 @@ +/* + * ifx_ssc.h defines some data sructures used in ifx_ssc.c + * + * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT) + * + * + */ + +#ifndef __IFX_SSC_H +#define __IFX_SSC_H +#ifdef __KERNEL__ +#include <asm/danube/ifx_ssc_defines.h> +#endif //__KERNEL__ + +#define PORT_CNT 1 // assume default value + +/* symbolic constants to be used in SSC routines */ + +// ### TO DO: bad performance +#define IFX_SSC_TXFIFO_ITL 1 +#define IFX_SSC_RXFIFO_ITL 1 + +struct ifx_ssc_statistics { + unsigned int abortErr; /* abort error */ + unsigned int modeErr; /* master/slave mode error */ + unsigned int txOvErr; /* TX Overflow error */ + unsigned int txUnErr; /* TX Underrun error */ + unsigned int rxOvErr; /* RX Overflow error */ + unsigned int rxUnErr; /* RX Underrun error */ + unsigned int rxBytes; + unsigned int txBytes; +}; + +struct ifx_ssc_hwopts { + unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */ + unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */ + unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */ + unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */ + unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */ + unsigned int echoMode:1; /* Echo mode */ + unsigned int loopBack:1; /* Loopback mode */ + unsigned int idleValue:1; /* Idle value */ + unsigned int clockPolarity:1; /* Idle clock is high or low */ + unsigned int clockPhase:1; /* Tx on trailing or leading edge */ + unsigned int headingControl:1; /* LSB first or MSB first */ + unsigned int dataWidth:6; /* from 2 up to 32 bits */ + unsigned int masterSelect:1; /* Master or Slave mode */ + unsigned int modeRxTx:2; /* rx/tx mode */ + unsigned int gpoCs:8; /* choose outputs to use for chip select */ + unsigned int gpoInv:8; /* invert GPO outputs */ +}; + +struct ifx_ssc_frm_opts { + bool FrameEnable; // SFCON.SFEN + unsigned int DataLength; // SFCON.DLEN + unsigned int PauseLength; // SFCON.PLEN + unsigned int IdleData; // SFCON.IDAT + unsigned int IdleClock; // SFCON.ICLK + bool StopAfterPause; // SFCON.STOP +}; + +struct ifx_ssc_frm_status { + bool DataBusy; // SFSTAT.DBSY + bool PauseBusy; // SFSTAT.PBSY + unsigned int DataCount; // SFSTAT.DCNT + unsigned int PauseCount; // SFSTAT.PCNT + bool EnIntAfterData; // SFCON.IBEN + bool EnIntAfterPause; // SFCON.IAEN +}; + +typedef struct { + char *buf; + size_t len; +} ifx_ssc_buf_item_t; + +// data structures for batch execution +typedef union { + struct { + bool save_options; + } init; + ifx_ssc_buf_item_t read; + ifx_ssc_buf_item_t write; + ifx_ssc_buf_item_t rd_wr; + unsigned int set_baudrate; + struct ifx_ssc_frm_opts set_frm; + unsigned int set_gpo; + struct ifx_ssc_hwopts set_hwopts; +} ifx_ssc_batch_cmd_param; + +struct ifx_ssc_batch_list { + unsigned int cmd; + ifx_ssc_batch_cmd_param cmd_param; + struct ifx_ssc_batch_list *next; +}; + +#ifdef __KERNEL__ +#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE) + +struct ifx_ssc_port { + unsigned long mapbase; + struct ifx_ssc_hwopts opts; + struct ifx_ssc_statistics stats; + struct ifx_ssc_frm_status frm_status; + struct ifx_ssc_frm_opts frm_opts; + /* wait queue for ifx_ssc_read() */ + wait_queue_head_t rwait, pwait; + int port_nr; + char port_is_open; /* exclusive open - boolean */ +// int no_of_bits; /* number of _valid_ bits */ +// int elem_size; /* shift for element (no of bytes)*/ + /* buffer and pointers to the read/write position */ + char *rxbuf; /* buffer for RX */ + char *rxbuf_end; /* buffer end pointer for RX */ + volatile char *rxbuf_ptr; /* buffer write pointer for RX */ + char *txbuf; /* buffer for TX */ + char *txbuf_end; /* buffer end pointer for TX */ + volatile char *txbuf_ptr; /* buffer read pointer for TX */ + unsigned int baud; + /* each channel has its own interrupts */ + /* (transmit/receive/error/frame) */ + unsigned int txirq, rxirq, errirq, frmirq; +}; +/* default values for SSC configuration */ +// values of CON +#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */ +#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */ +#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */ +#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */ +#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */ +#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */ +#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */ +#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */ +#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST +#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX +// other values +#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */ +#ifdef CONFIG_USE_EMULATOR +#define IFX_SSC_DEF_BAUDRATE 10000 +#else +#define IFX_SSC_DEF_BAUDRATE 2000000 +#endif +#define IFX_SSC_DEF_RMC 0x10 + +#define IFX_SSC_DEF_TXFIFO_FL 8 +#define IFX_SSC_DEF_RXFIFO_FL 1 + +#if 1 //TODO +#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */ +#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */ +#else +#error "what is ur Chip Select???" +#endif +#define IFX_SSC_DEF_SFCON 0 /* no serial framing */ +#if 0 +#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ + IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT +#endif +#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ + IFX_SSC_R_BIT | IFX_SSC_E_BIT +#endif /* __KERNEL__ */ + +// batch execution commands +#define IFX_SSC_BATCH_CMD_INIT 1 +#define IFX_SSC_BATCH_CMD_READ 2 +#define IFX_SSC_BATCH_CMD_WRITE 3 +#define IFX_SSC_BATCH_CMD_RD_WR 4 +#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5 +#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6 +#define IFX_SSC_BATCH_CMD_SET_FRM 7 +#define IFX_SSC_BATCH_CMD_SET_GPO 8 +#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9 +//#define IFX_SSC_BATCH_CMD_ +//#define IFX_SSC_BATCH_CMD_ +#define IFX_SSC_BATCH_CMD_END_EXEC 0 + +/* Macros to configure SSC hardware */ +/* headingControl: */ +#define IFX_SSC_LSB_FIRST 0 +#define IFX_SSC_MSB_FIRST 1 +/* dataWidth: */ +#define IFX_SSC_MIN_DATA_WIDTH 2 +#define IFX_SSC_MAX_DATA_WIDTH 32 +/* master/slave mode select */ +#define IFX_SSC_MASTER_MODE 1 +#define IFX_SSC_SLAVE_MODE 0 +/* rx/tx mode */ +// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h +#define IFX_SSC_MODE_RXTX 0 +#define IFX_SSC_MODE_RX 1 +#define IFX_SSC_MODE_TX 2 +#define IFX_SSC_MODE_OFF 3 +#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX + +/* GPO values */ +#define IFX_SSC_MAX_GPO_OUT 7 + +#define IFX_SSC_RXREQ_BLOCK_SIZE 32768 + +/***********************/ +/* defines for ioctl's */ +/***********************/ +#define IFX_SSC_IOCTL_MAGIC 'S' +/* read out the statistics */ +#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics) +/* clear the statistics */ +#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2) +/* set the baudrate */ +#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int) +/* get the current baudrate */ +#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int) +/* set hardware options */ +#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts) +/* get the current hardware options */ +#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts) +/* set transmission mode */ +#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int) +/* get the current transmission mode */ +#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int) +/* abort transmission */ +#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9) +#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9) + +/* set general purpose outputs */ +#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int) +/* clear general purpose outputs */ +#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int) +/* get general purpose outputs */ +#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int) + +/*** serial framing ***/ +/* get status of serial framing */ +#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status) +/* get counter reload values and control bits */ +#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts) +/* set counter reload values and control bits */ +#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts) + +/*** batch execution ***/ +/* do batch execution */ +#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list) + +#ifdef __KERNEL__ +// routines from ifx_ssc.c +// ### TO DO +/* kernel interface for read and write */ +ssize_t ifx_ssc_kread (int, char *, size_t); +ssize_t ifx_ssc_kwrite (int, const char *, size_t); + +#ifdef CONFIG_IFX_VP_KERNEL_TEST +void ifx_ssc_tc (void); +#endif // CONFIG_IFX_VP_KERNEL_TEST + +#endif //__KERNEL__ +#endif // __IFX_SSC_H diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc_defines.h b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc_defines.h new file mode 100644 index 0000000..805d48a --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc_defines.h @@ -0,0 +1,547 @@ +#ifndef IFX_SSC_DEFINES_H +#define IFX_SSC_DEFINES_H + +#include "ifx_peripheral_definitions.h" + +/* maximum SSC FIFO size */ +#define IFX_SSC_MAX_FIFO_SIZE 32 + +/* register map of SSC */ + +/* address of the Clock Control Register of the SSC */ +#define IFX_SSC_CLC 0x00000000 +/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 + bit 1 is hardware modified*/ +#define IFX_SSC_CLC_readmask 0x00FFFFEF +#define IFX_SSC_CLC_writemask 0x00FFFF3D +#define IFX_SSC_CLC_hwmask 0x00000002 +#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) + +/* address of Port Input Select Register of the SSC */ +#define IFX_SSC_PISEL 0x00000004 +/* IFX_SSC_PISEL register is significant in lowest three bits only */ +#define IFX_SSC_PISEL_readmask 0x00000007 +#define IFX_SSC_PISEL_writemask 0x00000007 +#define IFX_SSC_PISEL_hwmask 0x00000000 +#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) + +/* address of Identification Register of the SSC */ +#define IFX_SSC_ID 0x00000008 +/* IFX_SSC_ID register is significant in no bit */ +#define IFX_SSC_ID_readmask 0x0000FF3F +#define IFX_SSC_ID_writemask 0x00000000 +#define IFX_SSC_ID_hwmask 0x00000000 +#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) + +/* address of the Control Register of the SSC */ +#define IFX_SSC_CON 0x00000010 +/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ +#define IFX_SSC_CON_readmask 0x01DF1FFF +#define IFX_SSC_CON_writemask 0x01DF1FFF +#define IFX_SSC_CON_hwmask 0x00000000 +#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) + +/* address of the Status Register of the SSC */ +#define IFX_SSC_STATE 0x00000014 +/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 + all bits except 1:0 are hardware modified */ +#define IFX_SSC_STATE_readmask 0x771F3F87 +#define IFX_SSC_STATE_writemask 0x00000000 +#define IFX_SSC_STATE_hwmask 0x771F3F84 +#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) + +/* address of the Write Hardware Modified Control Register Bits of the SSC */ +#define IFX_SSC_WHBSTATE 0x00000018 +/* IFX_SSC_WHBSTATE register is write only */ +#define IFX_SSC_WHBSTATE_readmask 0x00000000 +#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF +#define IFX_SSC_WHBSTATE_hwmask 0x00000000 +#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) + +/* address of the Baudrate Timer Reload Register of the SSC */ +#define IFX_SSC_BR 0x00000040 +/* IFX_SSC_BR register is significant in bit 15 downto 0*/ +#define IFX_SSC_BR_readmask 0x0000FFFF +#define IFX_SSC_BR_writemask 0x0000FFFF +#define IFX_SSC_BR_hwmask 0x00000000 +#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) + +/* address of the Baudrate Timer Status Register of the SSC */ +#define IFX_SSC_BRSTAT 0x00000044 +/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ +#define IFX_SSC_BRSTAT_readmask 0x0000FFFF +#define IFX_SSC_BRSTAT_writemask 0x00000000 +#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF +#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) + +/* address of the Transmitter Buffer Register of the SSC */ +#define IFX_SSC_TB 0x00000020 +/* IFX_SSC_TB register is significant in bit 31 downto 0*/ +#define IFX_SSC_TB_readmask 0xFFFFFFFF +#define IFX_SSC_TB_writemask 0xFFFFFFFF +#define IFX_SSC_TB_hwmask 0x00000000 +#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) + +/* address of the Reciver Buffer Register of the SSC */ +#define IFX_SSC_RB 0x00000024 +/* IFX_SSC_RB register is significant in no bits*/ +#define IFX_SSC_RB_readmask 0xFFFFFFFF +#define IFX_SSC_RB_writemask 0x00000000 +#define IFX_SSC_RB_hwmask 0xFFFFFFFF +#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) + +/* address of the Receive FIFO Control Register of the SSC */ +#define IFX_SSC_RXFCON 0x00000030 +/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ +#define IFX_SSC_RXFCON_readmask 0x00003F03 +#define IFX_SSC_RXFCON_writemask 0x00003F03 +#define IFX_SSC_RXFCON_hwmask 0x00000000 +#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) + +/* address of the Transmit FIFO Control Register of the SSC */ +#define IFX_SSC_TXFCON 0x00000034 +/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ +#define IFX_SSC_TXFCON_readmask 0x00003F03 +#define IFX_SSC_TXFCON_writemask 0x00003F03 +#define IFX_SSC_TXFCON_hwmask 0x00000000 +#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) + +/* address of the FIFO Status Register of the SSC */ +#define IFX_SSC_FSTAT 0x00000038 +/* IFX_SSC_FSTAT register is significant in no bit*/ +#define IFX_SSC_FSTAT_readmask 0x00003F3F +#define IFX_SSC_FSTAT_writemask 0x00000000 +#define IFX_SSC_FSTAT_hwmask 0x00003F3F +#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) + +/* address of the Data Frame Control register of the SSC */ +#define IFX_SSC_SFCON 0x00000060 +#define IFX_SSC_SFCON_readmask 0xFFDFFFFD +#define IFX_SSC_SFCON_writemask 0xFFDFFFFD +#define IFX_SSC_SFCON_hwmask 0x00000000 +#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) + +/* address of the Data Frame Status register of the SSC */ +#define IFX_SSC_SFSTAT 0x00000064 +#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 +#define IFX_SSC_SFSTAT_writemask 0x00000000 +#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 +#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) + +/* address of the General Purpose Output Control register of the SSC */ +#define IFX_SSC_GPOCON 0x00000070 +#define IFX_SSC_GPOCON_readmask 0x0000FFFF +#define IFX_SSC_GPOCON_writemask 0x0000FFFF +#define IFX_SSC_GPOCON_hwmask 0x00000000 +#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) + +/* address of the General Purpose Output Status register of the SSC */ +#define IFX_SSC_GPOSTAT 0x00000074 +#define IFX_SSC_GPOSTAT_readmask 0x000000FF +#define IFX_SSC_GPOSTAT_writemask 0x00000000 +#define IFX_SSC_GPOSTAT_hwmask 0x00000000 +#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) + +/* address of the Force GPO Status register of the SSC */ +#define IFX_SSC_WHBGPOSTAT 0x00000078 +#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 +#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF +#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 +#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) + +/* address of the Receive Request Register of the SSC */ +#define IFX_SSC_RXREQ 0x00000080 +#define IFX_SSC_RXREQ_readmask 0x0000FFFF +#define IFX_SSC_RXREQ_writemask 0x0000FFFF +#define IFX_SSC_RXREQ_hwmask 0x00000000 +#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) + +/* address of the Receive Count Register of the SSC */ +#define IFX_SSC_RXCNT 0x00000084 +#define IFX_SSC_RXCNT_readmask 0x0000FFFF +#define IFX_SSC_RXCNT_writemask 0x00000000 +#define IFX_SSC_RXCNT_hwmask 0x0000FFFF +#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) + +/* address of the DMA Configuration Register of the SSC */ +#define IFX_SSC_DMACON 0x000000EC +#define IFX_SSC_DMACON_readmask 0x0000FFFF +#define IFX_SSC_DMACON_writemask 0x00000000 +#define IFX_SSC_DMACON_hwmask 0x0000FFFF +#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) + +//------------------------------------------------------ +// interrupt register for enabling interrupts, mask register of irq_reg +#define IFX_SSC_IRN_EN 0xF4 +// read/write +#define IFX_SSC_IRN_EN_readmask 0x0000000F +#define IFX_SSC_IRN_EN_writemask 0x0000000F +#define IFX_SSC_IRN_EN_hwmask 0x00000000 +#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) + +// interrupt register for accessing interrupts +#define IFX_SSC_IRN_CR 0xF8 +// read/write +#define IFX_SSC_IRN_CR_readmask 0x0000000F +#define IFX_SSC_IRN_CR_writemask 0x0000000F +#define IFX_SSC_IRN_CR_hwmask 0x0000000F +#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) + +// interrupt register for stimulating interrupts +#define IFX_SSC_IRN_ICR 0xFC +// read/write +#define IFX_SSC_IRN_ICR_readmask 0x0000000F +#define IFX_SSC_IRN_ICR_writemask 0x0000000F +#define IFX_SSC_IRN_ICR_hwmask 0x00000000 +#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) + +//--------------------------------------------------------------------- +// Number of IRQs and bitposition of IRQ +#define IFX_SSC_NUM_IRQ 4 +#define IFX_SSC_T_BIT 0x00000001 +#define IFX_SSC_R_BIT 0x00000002 +#define IFX_SSC_E_BIT 0x00000004 +#define IFX_SSC_F_BIT 0x00000008 + +/* bit masks for SSC registers */ + +/* ID register */ +#define IFX_SSC_PERID_REV_MASK 0x0000001F +#define IFX_SSC_PERID_CFG_MASK 0x00000020 +#define IFX_SSC_PERID_ID_MASK 0x0000FF00 +#define IFX_SSC_PERID_REV_OFFSET 0 +#define IFX_SSC_PERID_CFG_OFFSET 5 +#define IFX_SSC_PERID_ID_OFFSET 8 +#define IFX_SSC_PERID_ID 0x45 +#define IFX_SSC_PERID_DMA_ON 0x00000020 +#define IFX_SSC_PERID_RXFS_MASK 0x003F0000 +#define IFX_SSC_PERID_RXFS_OFFSET 16 +#define IFX_SSC_PERID_TXFS_MASK 0x3F000000 +#define IFX_SSC_PERID_TXFS_OFFSET 24 + +/* PISEL register */ +#define IFX_SSC_PISEL_MASTER_IN_A 0x0000 +#define IFX_SSC_PISEL_MASTER_IN_B 0x0001 +#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 +#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 +#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 +#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 + +/* IFX_SSC_CON register */ +#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 +#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 +#define IFX_SSC_CON_IDLE_HIGH 0x00800000 +#define IFX_SSC_CON_IDLE_LOW 0x00000000 +#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 +#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 +#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 +#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 +#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) + +#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 +#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 + +#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 +#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 +#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 +#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 +#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 +#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 +#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 +#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 +#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 +#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 +#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 +#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 + +#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 +#define IFX_SSC_CON_NO_LOOPBACK 0x00000000 +#define IFX_SSC_CON_HALF_DUPLEX 0x00000080 +#define IFX_SSC_CON_FULL_DUPLEX 0x00000000 +#define IFX_SSC_CON_CLOCK_FALL 0x00000040 +#define IFX_SSC_CON_CLOCK_RISE 0x00000000 +#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 +#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 +#define IFX_SSC_CON_MSB_FIRST 0x00000010 +#define IFX_SSC_CON_LSB_FIRST 0x00000000 +#define IFX_SSC_CON_ENABLE_CSB 0x00000008 +#define IFX_SSC_CON_DISABLE_CSB 0x00000000 +#define IFX_SSC_CON_INVERT_CSB 0x00000004 +#define IFX_SSC_CON_TRUE_CSB 0x00000000 +#define IFX_SSC_CON_RX_OFF 0x00000002 +#define IFX_SSC_CON_RX_ON 0x00000000 +#define IFX_SSC_CON_TX_OFF 0x00000001 +#define IFX_SSC_CON_TX_ON 0x00000000 + +/* IFX_SSC_STATE register */ +#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 +#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 +#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) +#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 +#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 +#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) +#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 +#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 +#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) +#define IFX_SSC_STATE_BUSY 0x00002000 +#define IFX_SSC_STATE_RX_UFL 0x00001000 +#define IFX_SSC_STATE_TX_UFL 0x00000800 +#define IFX_SSC_STATE_ABORT_ERR 0x00000400 +#define IFX_SSC_STATE_RX_OFL 0x00000200 +#define IFX_SSC_STATE_TX_OFL 0x00000100 +#define IFX_SSC_STATE_MODE_ERR 0x00000080 +#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 +#define IFX_SSC_STATE_IS_MASTER 0x00000002 +#define IFX_SSC_STATE_IS_ENABLED 0x00000001 + +/* WHBSTATE register */ +#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 +#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 +#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 + +#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 +#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 +#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 + +#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 +#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 + +#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 +#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 + +#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 +#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 + +#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 +#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 + +#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 +#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 +#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 +#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 +#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 +#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 +#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 +#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 +#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 +#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 + +/* BR register */ +#define IFX_SSC_BR_BAUDRATE_OFFSET 0 +#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF + +/* BR_STAT register */ +#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 +#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF + +/* TB register */ +#define IFX_SSC_TB_DATA_OFFSET 0 +#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF + +/* RB register */ +#define IFX_SSC_RB_DATA_OFFSET 0 +#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF + +/* RXFCON and TXFCON registers */ +#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 +#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 +#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 +#define IFX_SSC_XFCON_ITL_MASK 0x00003F00 +#define IFX_SSC_XFCON_ITL_OFFSET 8 + +/* FSTAT register */ +#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 +#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F +#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 +#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 + +/* GPOCON register */ +#define IFX_SSC_GPOCON_INVOUT0_POS 0 +#define IFX_SSC_GPOCON_INV_OUT0 0x00000001 +#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 +#define IFX_SSC_GPOCON_INVOUT1_POS 1 +#define IFX_SSC_GPOCON_INV_OUT1 0x00000002 +#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 +#define IFX_SSC_GPOCON_INVOUT2_POS 2 +#define IFX_SSC_GPOCON_INV_OUT2 0x00000003 +#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 +#define IFX_SSC_GPOCON_INVOUT3_POS 3 +#define IFX_SSC_GPOCON_INV_OUT3 0x00000008 +#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 +#define IFX_SSC_GPOCON_INVOUT4_POS 4 +#define IFX_SSC_GPOCON_INV_OUT4 0x00000010 +#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 +#define IFX_SSC_GPOCON_INVOUT5_POS 5 +#define IFX_SSC_GPOCON_INV_OUT5 0x00000020 +#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 +#define IFX_SSC_GPOCON_INVOUT6_POS 6 +#define IFX_SSC_GPOCON_INV_OUT6 0x00000040 +#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 +#define IFX_SSC_GPOCON_INVOUT7_POS 7 +#define IFX_SSC_GPOCON_INV_OUT7 0x00000080 +#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 +#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF +#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 + +#define IFX_SSC_GPOCON_ISCSB0_POS 8 +#define IFX_SSC_GPOCON_IS_CSB0 0x00000100 +#define IFX_SSC_GPOCON_IS_GPO0 0x00000000 +#define IFX_SSC_GPOCON_ISCSB1_POS 9 +#define IFX_SSC_GPOCON_IS_CSB1 0x00000200 +#define IFX_SSC_GPOCON_IS_GPO1 0x00000000 +#define IFX_SSC_GPOCON_ISCSB2_POS 10 +#define IFX_SSC_GPOCON_IS_CSB2 0x00000400 +#define IFX_SSC_GPOCON_IS_GPO2 0x00000000 +#define IFX_SSC_GPOCON_ISCSB3_POS 11 +#define IFX_SSC_GPOCON_IS_CSB3 0x00000800 +#define IFX_SSC_GPOCON_IS_GPO3 0x00000000 +#define IFX_SSC_GPOCON_ISCSB4_POS 12 +#define IFX_SSC_GPOCON_IS_CSB4 0x00001000 +#define IFX_SSC_GPOCON_IS_GPO4 0x00000000 +#define IFX_SSC_GPOCON_ISCSB5_POS 13 +#define IFX_SSC_GPOCON_IS_CSB5 0x00002000 +#define IFX_SSC_GPOCON_IS_GPO5 0x00000000 +#define IFX_SSC_GPOCON_ISCSB6_POS 14 +#define IFX_SSC_GPOCON_IS_CSB6 0x00004000 +#define IFX_SSC_GPOCON_IS_GPO6 0x00000000 +#define IFX_SSC_GPOCON_ISCSB7_POS 15 +#define IFX_SSC_GPOCON_IS_CSB7 0x00008000 +#define IFX_SSC_GPOCON_IS_GPO7 0x00000000 +#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 +#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 + +/* GPOSTAT register */ +#define IFX_SSC_GPOSTAT_OUT0 0x00000001 +#define IFX_SSC_GPOSTAT_OUT1 0x00000002 +#define IFX_SSC_GPOSTAT_OUT2 0x00000004 +#define IFX_SSC_GPOSTAT_OUT3 0x00000008 +#define IFX_SSC_GPOSTAT_OUT4 0x00000010 +#define IFX_SSC_GPOSTAT_OUT5 0x00000020 +#define IFX_SSC_GPOSTAT_OUT6 0x00000040 +#define IFX_SSC_GPOSTAT_OUT7 0x00000080 +#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF + +/* WHBGPOSTAT register */ +#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 +#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 +#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 +#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 +#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 +#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 +#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 +#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF + +#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 +#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 +#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 +#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 +#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 +#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 +#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 +#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 + +#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 +#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 +#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 +#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 +#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 +#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 +#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 +#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 +#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 +#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 +#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 +#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 +#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 +#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 +#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 +#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 +#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 + +/* SFCON register */ +#define IFX_SSC_SFCON_SF_ENABLE 0x00000001 +#define IFX_SSC_SFCON_SF_DISABLE 0x00000000 +#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 +#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 +#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 +#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 +#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 +#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 +#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 +#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 +#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 +#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 +#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 +#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 +#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 +#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 +#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 +#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 +#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 +#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 + +#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) +#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) +#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) +#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) + +/* SFSTAT register */ +#define IFX_SSC_SFSTAT_IN_DATA 0x00000001 +#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 +#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 +#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 +#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 +#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 + +#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) +#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) + +/* RXREQ register */ +#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF +#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 + +/* RXCNT register */ +#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF +#define IFX_SSC_RXCNT_TODO_OFFSET 0 + +/* DMACON register */ +#define IFX_SSC_DMACON_RXON 0x00000001 +#define IFX_SSC_DMACON_RXOFF 0x00000000 +#define IFX_SSC_DMACON_TXON 0x00000002 +#define IFX_SSC_DMACON_TXOFF 0x00000000 +#define IFX_SSC_DMACON_DMAON 0x00000003 +#define IFX_SSC_DMACON_DMAOFF 0x00000000 +#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C +#define IFX_SSC_DMACON_CLASS_OFFSET 2 + +/* register access macros */ +#define ifx_ssc_fstat_received_words(status) (status & 0x003F) +#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) + +#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) +#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) +#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) +#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) +#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) +#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) +#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) +#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) + +#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) +#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) + +#endif diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h b/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h new file mode 100644 index 0000000..7f1e7d3 --- /dev/null +++ b/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h @@ -0,0 +1,8 @@ +#ifndef __DANUBE_IRQ_H +#define __DANUBE_IRQ_H + +#define NR_IRQS 256 +#include_next <irq.h> + +#endif + |