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author | John Crispin <john@openwrt.org> | 2008-05-11 14:13:15 +0000 |
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committer | John Crispin <john@openwrt.org> | 2008-05-11 14:13:15 +0000 |
commit | 4d4f7d4c845901f0353c492f05c4f837dfd1e049 (patch) | |
tree | 8cad938f65f89fb196fadb1ebae436282f4ee313 /target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h | |
parent | 2b05ed626c650657e29575f209ea80e6553f8a55 (diff) | |
download | mtk-20170518-4d4f7d4c845901f0353c492f05c4f837dfd1e049.zip mtk-20170518-4d4f7d4c845901f0353c492f05c4f837dfd1e049.tar.gz mtk-20170518-4d4f7d4c845901f0353c492f05c4f837dfd1e049.tar.bz2 |
add u-boot sources for danube
SVN-Revision: 11108
Diffstat (limited to 'target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h')
-rwxr-xr-x | target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h b/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h new file mode 100755 index 0000000..54bb6c9 --- /dev/null +++ b/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_PROMOSDDR400.h @@ -0,0 +1,50 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xa02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x0 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x4e20 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 |